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#define | RX_MPDU_QUEUE 0 |
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#define | RX_CMD_QUEUE 1 |
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#define | RX_MAX_QUEUE 2 |
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#define | SHORT_SLOT_TIME 9 |
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#define | NON_SHORT_SLOT_TIME 20 |
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#define | RX_SMOOTH_FACTOR 20 |
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#define | QSLT_BK 0x2 |
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#define | QSLT_BE 0x0 |
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#define | QSLT_VI 0x5 |
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#define | QSLT_VO 0x6 |
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#define | QSLT_BEACON 0x10 |
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#define | QSLT_HIGH 0x11 |
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#define | QSLT_MGNT 0x12 |
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#define | QSLT_CMD 0x13 |
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#define | PHY_RSSI_SLID_WIN_MAX 100 |
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#define | PHY_LINKQUALITY_SLID_WIN_MAX 20 |
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#define | PHY_BEACON_RSSI_SLID_WIN_MAX 10 |
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#define | TX_DESC_SIZE_RTL8192S (16 * 4) |
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#define | TX_CMDDESC_SIZE_RTL8192S (16 * 4) |
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#define | SHIFT_AND_MASK_LE(__pdesc, __shift, __mask) |
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#define | SET_BITS_OFFSET_LE(__pdesc, __shift, __len, __val) |
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#define | SET_TX_DESC_PKT_SIZE(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc, 0, 16, __val) |
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#define | SET_TX_DESC_OFFSET(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc, 16, 8, __val) |
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#define | SET_TX_DESC_TYPE(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc, 24, 2, __val) |
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#define | SET_TX_DESC_LAST_SEG(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val) |
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#define | SET_TX_DESC_FIRST_SEG(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val) |
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#define | SET_TX_DESC_LINIP(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val) |
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#define | SET_TX_DESC_AMSDU(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc, 29, 1, __val) |
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#define | SET_TX_DESC_GREEN_FIELD(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val) |
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#define | SET_TX_DESC_OWN(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val) |
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#define | GET_TX_DESC_OWN(__pdesc) SHIFT_AND_MASK_LE(__pdesc, 31, 1) |
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#define | SET_TX_DESC_MACID(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 4, 0, 5, __val) |
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#define | SET_TX_DESC_MORE_DATA(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 4, 5, 1, __val) |
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#define | SET_TX_DESC_MORE_FRAG(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 4, 6, 1, __val) |
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#define | SET_TX_DESC_PIFS(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 4, 7, 1, __val) |
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#define | SET_TX_DESC_QUEUE_SEL(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 4, 8, 5, __val) |
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#define | SET_TX_DESC_ACK_POLICY(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 4, 13, 2, __val) |
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#define | SET_TX_DESC_NO_ACM(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 4, 15, 1, __val) |
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#define | SET_TX_DESC_NON_QOS(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 4, 16, 1, __val) |
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#define | SET_TX_DESC_KEY_ID(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 4, 17, 2, __val) |
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#define | SET_TX_DESC_OUI(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 4, 19, 1, __val) |
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#define | SET_TX_DESC_PKT_TYPE(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 4, 20, 1, __val) |
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#define | SET_TX_DESC_EN_DESC_ID(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 4, 21, 1, __val) |
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#define | SET_TX_DESC_SEC_TYPE(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 4, 22, 2, __val) |
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#define | SET_TX_DESC_WDS(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 4, 24, 1, __val) |
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#define | SET_TX_DESC_HTC(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 4, 25, 1, __val) |
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#define | SET_TX_DESC_PKT_OFFSET(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 4, 26, 5, __val) |
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#define | SET_TX_DESC_HWPC(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 4, 27, 1, __val) |
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#define | SET_TX_DESC_DATA_RETRY_LIMIT(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 8, 0, 6, __val) |
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#define | SET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 8, 6, 1, __val) |
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#define | SET_TX_DESC_TSFL(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 8, 7, 5, __val) |
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#define | SET_TX_DESC_RTS_RETRY_COUNT(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 8, 12, 6, __val) |
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#define | SET_TX_DESC_DATA_RETRY_COUNT(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 8, 18, 6, __val) |
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#define | SET_TX_DESC_RSVD_MACID(__pdesc, __val) SET_BITS_OFFSET_LE(((__pdesc) + 8), 24, 5, __val) |
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#define | SET_TX_DESC_AGG_ENABLE(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 8, 29, 1, __val) |
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#define | SET_TX_DESC_AGG_BREAK(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 8, 30, 1, __val) |
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#define | SET_TX_DESC_OWN_MAC(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 8, 31, 1, __val) |
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#define | SET_TX_DESC_NEXT_HEAP_PAGE(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 12, 0, 8, __val) |
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#define | SET_TX_DESC_TAIL_PAGE(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 12, 8, 8, __val) |
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#define | SET_TX_DESC_SEQ(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 12, 16, 12, __val) |
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#define | SET_TX_DESC_FRAG(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 12, 28, 4, __val) |
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#define | SET_TX_DESC_RTS_RATE(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 16, 0, 6, __val) |
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#define | SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 16, 6, 1, __val) |
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#define | SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 16, 7, 4, __val) |
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#define | SET_TX_DESC_CTS_ENABLE(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 16, 11, 1, __val) |
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#define | SET_TX_DESC_RTS_ENABLE(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 16, 12, 1, __val) |
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#define | SET_TX_DESC_RA_BRSR_ID(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 16, 13, 3, __val) |
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#define | SET_TX_DESC_TXHT(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 16, 16, 1, __val) |
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#define | SET_TX_DESC_TX_SHORT(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 16, 17, 1, __val) |
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#define | SET_TX_DESC_TX_BANDWIDTH(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 16, 18, 1, __val) |
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#define | SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 16, 19, 2, __val) |
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#define | SET_TX_DESC_TX_STBC(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 16, 21, 2, __val) |
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#define | SET_TX_DESC_TX_REVERSE_DIRECTION(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 16, 23, 1, __val) |
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#define | SET_TX_DESC_RTS_HT(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 16, 24, 1, __val) |
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#define | SET_TX_DESC_RTS_SHORT(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 16, 25, 1, __val) |
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#define | SET_TX_DESC_RTS_BANDWIDTH(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 16, 26, 1, __val) |
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#define | SET_TX_DESC_RTS_SUB_CARRIER(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 16, 27, 2, __val) |
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#define | SET_TX_DESC_RTS_STBC(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 16, 29, 2, __val) |
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#define | SET_TX_DESC_USER_RATE(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 16, 31, 1, __val) |
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#define | SET_TX_DESC_PACKET_ID(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 20, 0, 9, __val) |
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#define | SET_TX_DESC_TX_RATE(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 20, 9, 6, __val) |
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#define | SET_TX_DESC_DISABLE_FB(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 20, 15, 1, __val) |
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#define | SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 20, 16, 5, __val) |
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#define | SET_TX_DESC_TX_AGC(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 20, 21, 11, __val) |
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#define | SET_TX_DESC_IP_CHECK_SUM(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 24, 0, 16, __val) |
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#define | SET_TX_DESC_TCP_CHECK_SUM(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 24, 16, 16, __val) |
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#define | SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 28, 0, 16, __val) |
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#define | SET_TX_DESC_IP_HEADER_OFFSET(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 28, 16, 8, __val) |
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#define | SET_TX_DESC_TCP_ENABLE(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 28, 31, 1, __val) |
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#define | SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 32, 0, 32, __val) |
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#define | GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc) SHIFT_AND_MASK_LE(__pdesc + 32, 0, 32) |
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#define | SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 36, 0, 32, __val) |
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#define | TX_DESC_NEXT_DESC_OFFSET 36 |
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#define | CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) memset(__pdesc, 0, min_t(size_t, _size, TX_DESC_NEXT_DESC_OFFSET)) |
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#define | RX_STATUS_DESC_SIZE 24 |
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#define | RX_DRV_INFO_SIZE_UNIT 8 |
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#define | SET_RX_STATUS_DESC_PKT_LEN(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc, 0, 14, __val) |
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#define | SET_RX_STATUS_DESC_CRC32(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc, 14, 1, __val) |
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#define | SET_RX_STATUS_DESC_ICV(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc, 15, 1, __val) |
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#define | SET_RX_STATUS_DESC_DRVINFO_SIZE(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc, 16, 4, __val) |
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#define | SET_RX_STATUS_DESC_SECURITY(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc, 20, 3, __val) |
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#define | SET_RX_STATUS_DESC_QOS(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc, 23, 1, __val) |
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#define | SET_RX_STATUS_DESC_SHIFT(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc, 24, 2, __val) |
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#define | SET_RX_STATUS_DESC_PHY_STATUS(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val) |
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#define | SET_RX_STATUS_DESC_SWDEC(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val) |
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#define | SET_RX_STATUS_DESC_LAST_SEG(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val) |
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#define | SET_RX_STATUS_DESC_FIRST_SEG(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc, 29, 1, __val) |
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#define | SET_RX_STATUS_DESC_EOR(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val) |
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#define | SET_RX_STATUS_DESC_OWN(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val) |
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#define | GET_RX_STATUS_DESC_PKT_LEN(__pdesc) SHIFT_AND_MASK_LE(__pdesc, 0, 14) |
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#define | GET_RX_STATUS_DESC_CRC32(__pdesc) SHIFT_AND_MASK_LE(__pdesc, 14, 1) |
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#define | GET_RX_STATUS_DESC_ICV(__pdesc) SHIFT_AND_MASK_LE(__pdesc, 15, 1) |
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#define | GET_RX_STATUS_DESC_DRVINFO_SIZE(__pdesc) SHIFT_AND_MASK_LE(__pdesc, 16, 4) |
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#define | GET_RX_STATUS_DESC_SECURITY(__pdesc) SHIFT_AND_MASK_LE(__pdesc, 20, 3) |
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#define | GET_RX_STATUS_DESC_QOS(__pdesc) SHIFT_AND_MASK_LE(__pdesc, 23, 1) |
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#define | GET_RX_STATUS_DESC_SHIFT(__pdesc) SHIFT_AND_MASK_LE(__pdesc, 24, 2) |
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#define | GET_RX_STATUS_DESC_PHY_STATUS(__pdesc) SHIFT_AND_MASK_LE(__pdesc, 26, 1) |
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#define | GET_RX_STATUS_DESC_SWDEC(__pdesc) SHIFT_AND_MASK_LE(__pdesc, 27, 1) |
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#define | GET_RX_STATUS_DESC_LAST_SEG(__pdesc) SHIFT_AND_MASK_LE(__pdesc, 28, 1) |
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#define | GET_RX_STATUS_DESC_FIRST_SEG(__pdesc) SHIFT_AND_MASK_LE(__pdesc, 29, 1) |
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#define | GET_RX_STATUS_DESC_EOR(__pdesc) SHIFT_AND_MASK_LE(__pdesc, 30, 1) |
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#define | GET_RX_STATUS_DESC_OWN(__pdesc) SHIFT_AND_MASK_LE(__pdesc, 31, 1) |
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#define | SET_RX_STATUS_DESC_MACID(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 4, 0, 5, __val) |
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#define | SET_RX_STATUS_DESC_TID(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 4, 5, 4, __val) |
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#define | SET_RX_STATUS_DESC_PAGGR(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 4, 14, 1, __val) |
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#define | SET_RX_STATUS_DESC_FAGGR(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 4, 15, 1, __val) |
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#define | SET_RX_STATUS_DESC_A1_FIT(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 4, 16, 4, __val) |
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#define | SET_RX_STATUS_DESC_A2_FIT(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 4, 20, 4, __val) |
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#define | SET_RX_STATUS_DESC_PAM(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 4, 24, 1, __val) |
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#define | SET_RX_STATUS_DESC_PWR(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 4, 25, 1, __val) |
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#define | SET_RX_STATUS_DESC_MOREDATA(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 4, 26, 1, __val) |
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#define | SET_RX_STATUS_DESC_MOREFRAG(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 4, 27, 1, __val) |
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#define | SET_RX_STATUS_DESC_TYPE(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 4, 28, 2, __val) |
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#define | SET_RX_STATUS_DESC_MC(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 4, 30, 1, __val) |
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#define | SET_RX_STATUS_DESC_BC(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 4, 31, 1, __val) |
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#define | GET_RX_STATUS_DEC_MACID(__pdesc) SHIFT_AND_MASK_LE(__pdesc + 4, 0, 5) |
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#define | GET_RX_STATUS_DESC_TID(__pdesc) SHIFT_AND_MASK_LE(__pdesc + 4, 5, 4) |
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#define | GET_RX_STATUS_DESC_PAGGR(__pdesc) SHIFT_AND_MASK_LE(__pdesc + 4, 14, 1) |
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#define | GET_RX_STATUS_DESC_FAGGR(__pdesc) SHIFT_AND_MASK_LE(__pdesc + 4, 15, 1) |
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#define | GET_RX_STATUS_DESC_A1_FIT(__pdesc) SHIFT_AND_MASK_LE(__pdesc + 4, 16, 4) |
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#define | GET_RX_STATUS_DESC_A2_FIT(__pdesc) SHIFT_AND_MASK_LE(__pdesc + 4, 20, 4) |
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#define | GET_RX_STATUS_DESC_PAM(__pdesc) SHIFT_AND_MASK_LE(__pdesc + 4, 24, 1) |
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#define | GET_RX_STATUS_DESC_PWR(__pdesc) SHIFT_AND_MASK_LE(__pdesc + 4, 25, 1) |
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#define | GET_RX_STATUS_DESC_MORE_DATA(__pdesc) SHIFT_AND_MASK_LE(__pdesc + 4, 26, 1) |
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#define | GET_RX_STATUS_DESC_MORE_FRAG(__pdesc) SHIFT_AND_MASK_LE(__pdesc + 4, 27, 1) |
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#define | GET_RX_STATUS_DESC_TYPE(__pdesc) SHIFT_AND_MASK_LE(__pdesc + 4, 28, 2) |
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#define | GET_RX_STATUS_DESC_MC(__pdesc) SHIFT_AND_MASK_LE(__pdesc + 4, 30, 1) |
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#define | GET_RX_STATUS_DESC_BC(__pdesc) SHIFT_AND_MASK_LE(__pdesc + 4, 31, 1) |
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#define | SET_RX_STATUS_DESC_SEQ(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 8, 0, 12, __val) |
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#define | SET_RX_STATUS_DESC_FRAG(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 8, 12, 4, __val) |
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#define | SET_RX_STATUS_DESC_NEXT_PKTLEN(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 8, 16, 8, __val) |
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#define | SET_RX_STATUS_DESC_NEXT_IND(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 8, 30, 1, __val) |
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#define | GET_RX_STATUS_DESC_SEQ(__pdesc) SHIFT_AND_MASK_LE(__pdesc + 8, 0, 12) |
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#define | GET_RX_STATUS_DESC_FRAG(__pdesc) SHIFT_AND_MASK_LE(__pdesc + 8, 12, 4) |
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#define | GET_RX_STATUS_DESC_NEXT_PKTLEN(__pdesc) SHIFT_AND_MASK_LE(__pdesc + 8, 16, 8) |
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#define | GET_RX_STATUS_DESC_NEXT_IND(__pdesc) SHIFT_AND_MASK_LE(__pdesc + 8, 30, 1) |
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#define | SET_RX_STATUS_DESC_RX_MCS(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 12, 0, 6, __val) |
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#define | SET_RX_STATUS_DESC_RX_HT(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 12, 6, 1, __val) |
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#define | SET_RX_STATUS_DESC_AMSDU(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 12, 7, 1, __val) |
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#define | SET_RX_STATUS_DESC_SPLCP(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 12, 8, 1, __val) |
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#define | SET_RX_STATUS_DESC_BW(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 12, 9, 1, __val) |
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#define | SET_RX_STATUS_DESC_HTC(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 12, 10, 1, __val) |
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#define | SET_RX_STATUS_DESC_TCP_CHK_RPT(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 12, 11, 1, __val) |
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#define | SET_RX_STATUS_DESC_IP_CHK_RPT(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 12, 12, 1, __val) |
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#define | SET_RX_STATUS_DESC_TCP_CHK_VALID(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 12, 13, 1, __val) |
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#define | SET_RX_STATUS_DESC_HWPC_ERR(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 12, 14, 1, __val) |
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#define | SET_RX_STATUS_DESC_HWPC_IND(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 12, 15, 1, __val) |
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#define | SET_RX_STATUS_DESC_IV0(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 12, 16, 16, __val) |
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#define | GET_RX_STATUS_DESC_RX_MCS(__pdesc) SHIFT_AND_MASK_LE(__pdesc + 12, 0, 6) |
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#define | GET_RX_STATUS_DESC_RX_HT(__pdesc) SHIFT_AND_MASK_LE(__pdesc + 12, 6, 1) |
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#define | GET_RX_STATUS_DESC_AMSDU(__pdesc) SHIFT_AND_MASK_LE(__pdesc + 12, 7, 1) |
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#define | GET_RX_STATUS_DESC_SPLCP(__pdesc) SHIFT_AND_MASK_LE(__pdesc + 12, 8, 1) |
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#define | GET_RX_STATUS_DESC_BW(__pdesc) SHIFT_AND_MASK_LE(__pdesc + 12, 9, 1) |
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#define | GET_RX_STATUS_DESC_HTC(__pdesc) SHIFT_AND_MASK_LE(__pdesc + 12, 10, 1) |
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#define | GET_RX_STATUS_DESC_TCP_CHK_RPT(__pdesc) SHIFT_AND_MASK_LE(__pdesc + 12, 11, 1) |
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#define | GET_RX_STATUS_DESC_IP_CHK_RPT(__pdesc) SHIFT_AND_MASK_LE(__pdesc + 12, 12, 1) |
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#define | GET_RX_STATUS_DESC_TCP_CHK_VALID(__pdesc) SHIFT_AND_MASK_LE(__pdesc + 12, 13, 1) |
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#define | GET_RX_STATUS_DESC_HWPC_ERR(__pdesc) SHIFT_AND_MASK_LE(__pdesc + 12, 14, 1) |
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#define | GET_RX_STATUS_DESC_HWPC_IND(__pdesc) SHIFT_AND_MASK_LE(__pdesc + 12, 15, 1) |
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#define | GET_RX_STATUS_DESC_IV0(__pdesc) SHIFT_AND_MASK_LE(__pdesc + 12, 16, 16) |
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#define | SET_RX_STATUS_DESC_IV1(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 16, 0, 32, __val) |
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#define | GET_RX_STATUS_DESC_IV1(__pdesc) SHIFT_AND_MASK_LE(__pdesc + 16, 0, 32) |
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#define | SET_RX_STATUS_DESC_TSFL(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 20, 0, 32, __val) |
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#define | GET_RX_STATUS_DESC_TSFL(__pdesc) SHIFT_AND_MASK_LE(__pdesc + 20, 0, 32) |
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#define | SET_RX_STATUS__DESC_BUFF_ADDR(__pdesc, __val) SET_BITS_OFFSET_LE(__pdesc + 24, 0, 32, __val) |
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#define | SE_RX_HAL_IS_CCK_RATE(_pdesc) |
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