|
| #define | pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| |
| #define | RF_CHANGE_BY_INIT 0 |
| |
| #define | RF_CHANGE_BY_IPS BIT(28) |
| |
| #define | RF_CHANGE_BY_PS BIT(29) |
| |
| #define | RF_CHANGE_BY_HW BIT(30) |
| |
| #define | RF_CHANGE_BY_SW BIT(31) |
| |
| #define | IQK_ADDA_REG_NUM 16 |
| |
| #define | IQK_MAC_REG_NUM 4 |
| |
| #define | MAX_KEY_LEN 61 |
| |
| #define | KEY_BUF_SIZE 5 |
| |
| #define | AC0_BE 0 |
| |
| #define | AC1_BK 1 |
| |
| #define | AC2_VI 2 |
| |
| #define | AC3_VO 3 |
| |
| #define | AC_MAX 4 |
| |
| #define | QOS_QUEUE_NUM 4 |
| |
| #define | RTL_MAC80211_NUM_QUEUE 5 |
| |
| #define | REALTEK_USB_VENQT_MAX_BUF_SIZE 254 |
| |
| #define | RTL_USB_MAX_RX_COUNT 100 |
| |
| #define | QBSS_LOAD_SIZE 5 |
| |
| #define | MAX_WMMELE_LENGTH 64 |
| |
| #define | TOTAL_CAM_ENTRY 32 |
| |
| #define | RTL_SLOT_TIME_9 9 |
| |
| #define | RTL_SLOT_TIME_20 20 |
| |
| #define | ETH_P_PAE 0x888E /*Port Access Entity (IEEE 802.1X) */ |
| |
| #define | ETH_P_IP 0x0800 /*Internet Protocol packet */ |
| |
| #define | ETH_P_ARP 0x0806 /*Address Resolution packet */ |
| |
| #define | SNAP_SIZE 6 |
| |
| #define | PROTOC_TYPE_SIZE 2 |
| |
| #define | MAC80211_3ADDR_LEN 24 |
| |
| #define | MAC80211_4ADDR_LEN 30 |
| |
| #define | CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */ |
| |
| #define | CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */ |
| |
| #define | MAX_PG_GROUP 13 |
| |
| #define | CHANNEL_GROUP_MAX_2G 3 |
| |
| #define | CHANNEL_GROUP_IDX_5GL 3 |
| |
| #define | CHANNEL_GROUP_IDX_5GM 6 |
| |
| #define | CHANNEL_GROUP_IDX_5GH 9 |
| |
| #define | CHANNEL_GROUP_MAX_5G 9 |
| |
| #define | CHANNEL_MAX_NUMBER_2G 14 |
| |
| #define | AVG_THERMAL_NUM 8 |
| |
| #define | MAX_TID_COUNT 9 |
| |
| #define | FCS_LEN 4 |
| |
| #define | EM_HDR_LEN 8 |
| |
| #define | IS_HARDWARE_TYPE_8192SU(rtlhal) (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU) |
| |
| #define | IS_HARDWARE_TYPE_8192SE(rtlhal) (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) |
| |
| #define | IS_HARDWARE_TYPE_8192CE(rtlhal) (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE) |
| |
| #define | IS_HARDWARE_TYPE_8192CU(rtlhal) (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU) |
| |
| #define | IS_HARDWARE_TYPE_8192DE(rtlhal) (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) |
| |
| #define | IS_HARDWARE_TYPE_8192DU(rtlhal) (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU) |
| |
| #define | IS_HARDWARE_TYPE_8723E(rtlhal) (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E) |
| |
| #define | IS_HARDWARE_TYPE_8723U(rtlhal) (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U) |
| |
| #define | IS_HARDWARE_TYPE_8192S(rtlhal) (IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal)) |
| |
| #define | IS_HARDWARE_TYPE_8192C(rtlhal) (IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal)) |
| |
| #define | IS_HARDWARE_TYPE_8192D(rtlhal) (IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal)) |
| |
| #define | IS_HARDWARE_TYPE_8723(rtlhal) (IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal)) |
| |
| #define | IS_HARDWARE_TYPE_8723U(rtlhal) (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U) |
| |
| #define | RX_HAL_IS_CCK_RATE(_pdesc) |
| |
| #define | IS_WIRELESS_MODE_A(wirelessmode) (wirelessmode == WIRELESS_MODE_A) |
| |
| #define | IS_WIRELESS_MODE_B(wirelessmode) (wirelessmode == WIRELESS_MODE_B) |
| |
| #define | IS_WIRELESS_MODE_G(wirelessmode) (wirelessmode == WIRELESS_MODE_G) |
| |
| #define | IS_WIRELESS_MODE_N_24G(wirelessmode) (wirelessmode == WIRELESS_MODE_N_24G) |
| |
| #define | IS_WIRELESS_MODE_N_5G(wirelessmode) (wirelessmode == WIRELESS_MODE_N_5G) |
| |
| #define | IQK_MATRIX_REG_NUM 8 |
| |
| #define | IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21) |
| |
| #define | MAX_TID_COUNT 9 |
| |
| #define | RTL_AGG_STOP 0 |
| |
| #define | RTL_AGG_PROGRESS 1 |
| |
| #define | RTL_AGG_START 2 |
| |
| #define | RTL_AGG_OPERATIONAL 3 |
| |
| #define | RTL_AGG_OFF 0 |
| |
| #define | RTL_AGG_ON 1 |
| |
| #define | RTL_RX_AGG_START 1 |
| |
| #define | RTL_RX_AGG_STOP 0 |
| |
| #define | RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2 |
| |
| #define | RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3 |
| |
| #define | EFUSE_MAX_LOGICAL_SIZE 256 |
| |
| #define | MIMO_PS_STATIC 0 |
| |
| #define | MIMO_PS_DYNAMIC 1 |
| |
| #define | MIMO_PS_NOLIMIT 3 |
| |
| #define | rtl_priv(hw) (((struct rtl_priv *)(hw)->priv)) |
| |
| #define | rtl_mac(rtlpriv) (&((rtlpriv)->mac80211)) |
| |
| #define | rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal)) |
| |
| #define | rtl_efuse(rtlpriv) (&((rtlpriv)->efuse)) |
| |
| #define | rtl_psc(rtlpriv) (&((rtlpriv)->psc)) |
| |
| #define | EF1BYTE(_val) ((u8)(_val)) |
| |
| #define | EF2BYTE(_val) (le16_to_cpu(_val)) |
| |
| #define | EF4BYTE(_val) (le32_to_cpu(_val)) |
| |
| #define | READEF1BYTE(_ptr) EF1BYTE(*((u8 *)(_ptr))) |
| |
| #define | READEF2BYTE(_ptr) EF2BYTE(*(_ptr)) |
| |
| #define | READEF4BYTE(_ptr) EF4BYTE(*(_ptr)) |
| |
| #define | WRITEEF1BYTE(_ptr, _val) (*((u8 *)(_ptr))) = EF1BYTE(_val) |
| |
| #define | WRITEEF2BYTE(_ptr, _val) (*((u16 *)(_ptr))) = EF2BYTE(_val) |
| |
| #define | WRITEEF4BYTE(_ptr, _val) (*((u32 *)(_ptr))) = EF2BYTE(_val) |
| |
| #define | BIT_LEN_MASK_32(__bitlen) (0xFFFFFFFF >> (32 - (__bitlen))) |
| |
| #define | BIT_LEN_MASK_16(__bitlen) (0xFFFF >> (16 - (__bitlen))) |
| |
| #define | BIT_LEN_MASK_8(__bitlen) (0xFF >> (8 - (__bitlen))) |
| |
| #define | BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) (BIT_LEN_MASK_32(__bitlen) << (__bitoffset)) |
| |
| #define | BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) (BIT_LEN_MASK_16(__bitlen) << (__bitoffset)) |
| |
| #define | BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) (BIT_LEN_MASK_8(__bitlen) << (__bitoffset)) |
| |
| #define | LE_P4BYTE_TO_HOST_4BYTE(__pstart) (EF4BYTE(*((__le32 *)(__pstart)))) |
| |
| #define | LE_P2BYTE_TO_HOST_2BYTE(__pstart) (EF2BYTE(*((__le16 *)(__pstart)))) |
| |
| #define | LE_P1BYTE_TO_HOST_1BYTE(__pstart) (EF1BYTE(*((u8 *)(__pstart)))) |
| |
| #define | LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) |
| |
| #define | LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) |
| |
| #define | LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) |
| |
| #define | LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) |
| |
| #define | LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) |
| |
| #define | LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) |
| |
| #define | SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) |
| |
| #define | SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) |
| |
| #define | SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) |
| |
| #define | N_BYTE_ALIGMENT(__value, __aligment) |
| |
| #define | byte(x, n) ((x >> (8 * n)) & 0xff) |
| |
| #define | packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC) |
| |
| #define | RTL_WATCH_DOG_TIME 2000 |
| |
| #define | MSECS(t) msecs_to_jiffies(t) |
| |
| #define | WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS) |
| |
| #define | WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) |
| |
| #define | WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) |
| |
| #define | WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA) |
| |
| #define | SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4) |
| |
| #define | SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ) |
| |
| #define | MAX_SN ((IEEE80211_SCTL_SEQ) >> 4) |
| |
| #define | RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */ |
| |
| #define | RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */ |
| |
| #define | RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */ |
| |
| #define | RT_RF_OFF_LEVL_HALT_NIC BIT(3) |
| |
| #define | RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */ |
| |
| #define | RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */ |
| |
| #define | RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6) |
| |
| #define | RT_PS_LEVEL_ASPM BIT(7) |
| |
| #define | RT_RF_LPS_DISALBE_2R BIT(30) |
| |
| #define | RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */ |
| |
| #define | RT_IN_PS_LEVEL(ppsc, _ps_flg) ((ppsc->cur_ps_level & _ps_flg) ? true : false) |
| |
| #define | RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) (ppsc->cur_ps_level &= (~(_ps_flg))) |
| |
| #define | RT_SET_PS_LEVEL(ppsc, _ps_flg) (ppsc->cur_ps_level |= _ps_flg) |
| |
| #define | container_of_dwork_rtl(x, y, z) container_of(container_of(x, struct delayed_work, work), y, z) |
| |
| #define | FILL_OCTET_STRING(_os, _octet, _len) |
| |
| #define | CP_MACADDR(des, src) |
| |
|
| enum | intf_type { INTF_PCI = 0,
INTF_USB = 1
} |
| |
| enum | radio_path { RF90_PATH_A = 0,
RF90_PATH_B = 1,
RF90_PATH_C = 2,
RF90_PATH_D = 3
} |
| |
| enum | rt_eeprom_type {
EEPROM_93C46,
EEPROM_93C56,
EEPROM_BOOT_EFUSE,
EEPROM_93C46,
EEPROM_93C56,
EEPROM_BOOT_EFUSE
} |
| |
| enum | ttl_status { RTL_STATUS_INTERFACE_START = 0
} |
| |
| enum | hardware_type {
HARDWARE_TYPE_RTL8192E,
HARDWARE_TYPE_RTL8192U,
HARDWARE_TYPE_RTL8192SE,
HARDWARE_TYPE_RTL8192SU,
HARDWARE_TYPE_RTL8192CE,
HARDWARE_TYPE_RTL8192CU,
HARDWARE_TYPE_RTL8192DE,
HARDWARE_TYPE_RTL8192DU,
HARDWARE_TYPE_RTL8723AE,
HARDWARE_TYPE_RTL8723U,
HARDWARE_TYPE_NUM
} |
| |
| enum | scan_operation_backup_opt { SCAN_OPT_BACKUP = 0,
SCAN_OPT_RESTORE,
SCAN_OPT_MAX
} |
| |
| enum | rf_pwrstate { ERFON,
ERFSLEEP,
ERFOFF
} |
| |
| enum | io_type { IO_CMD_PAUSE_DM_BY_SCAN = 0,
IO_CMD_RESUME_DM_BY_SCAN = 1
} |
| |
| enum | hw_variables {
HW_VAR_ETHER_ADDR,
HW_VAR_MULTICAST_REG,
HW_VAR_BASIC_RATE,
HW_VAR_BSSID,
HW_VAR_MEDIA_STATUS,
HW_VAR_SECURITY_CONF,
HW_VAR_BEACON_INTERVAL,
HW_VAR_ATIM_WINDOW,
HW_VAR_LISTEN_INTERVAL,
HW_VAR_CS_COUNTER,
HW_VAR_DEFAULTKEY0,
HW_VAR_DEFAULTKEY1,
HW_VAR_DEFAULTKEY2,
HW_VAR_DEFAULTKEY3,
HW_VAR_SIFS,
HW_VAR_DIFS,
HW_VAR_EIFS,
HW_VAR_SLOT_TIME,
HW_VAR_ACK_PREAMBLE,
HW_VAR_CW_CONFIG,
HW_VAR_CW_VALUES,
HW_VAR_RATE_FALLBACK_CONTROL,
HW_VAR_CONTENTION_WINDOW,
HW_VAR_RETRY_COUNT,
HW_VAR_TR_SWITCH,
HW_VAR_COMMAND,
HW_VAR_WPA_CONFIG,
HW_VAR_AMPDU_MIN_SPACE,
HW_VAR_SHORTGI_DENSITY,
HW_VAR_AMPDU_FACTOR,
HW_VAR_MCS_RATE_AVAILABLE,
HW_VAR_AC_PARAM,
HW_VAR_ACM_CTRL,
HW_VAR_DIS_Req_Qsize,
HW_VAR_CCX_CHNL_LOAD,
HW_VAR_CCX_NOISE_HISTOGRAM,
HW_VAR_CCX_CLM_NHM,
HW_VAR_TxOPLimit,
HW_VAR_TURBO_MODE,
HW_VAR_RF_STATE,
HW_VAR_RF_OFF_BY_HW,
HW_VAR_BUS_SPEED,
HW_VAR_SET_DEV_POWER,
HW_VAR_RCR,
HW_VAR_RATR_0,
HW_VAR_RRSR,
HW_VAR_CPU_RST,
HW_VAR_CECHK_BSSID,
HW_VAR_LBK_MODE,
HW_VAR_AES_11N_FIX,
HW_VAR_USB_RX_AGGR,
HW_VAR_USER_CONTROL_TURBO_MODE,
HW_VAR_RETRY_LIMIT,
HW_VAR_INIT_TX_RATE,
HW_VAR_TX_RATE_REG,
HW_VAR_EFUSE_USAGE,
HW_VAR_EFUSE_BYTES,
HW_VAR_AUTOLOAD_STATUS,
HW_VAR_RF_2R_DISABLE,
HW_VAR_SET_RPWM,
HW_VAR_H2C_FW_PWRMODE,
HW_VAR_H2C_FW_JOINBSSRPT,
HW_VAR_FW_PSMODE_STATUS,
HW_VAR_1X1_RECV_COMBINE,
HW_VAR_STOP_SEND_BEACON,
HW_VAR_TSF_TIMER,
HW_VAR_IO_CMD,
HW_VAR_RF_RECOVERY,
HW_VAR_H2C_FW_UPDATE_GTK,
HW_VAR_WF_MASK,
HW_VAR_WF_CRC,
HW_VAR_WF_IS_MAC_ADDR,
HW_VAR_H2C_FW_OFFLOAD,
HW_VAR_RESET_WFCRC,
HW_VAR_HANDLE_FW_C2H,
HW_VAR_DL_FW_RSVD_PAGE,
HW_VAR_AID,
HW_VAR_HW_SEQ_ENABLE,
HW_VAR_CORRECT_TSF,
HW_VAR_BCN_VALID,
HW_VAR_FWLPS_RF_ON,
HW_VAR_DUAL_TSF_RST,
HW_VAR_SWITCH_EPHY_WoWLAN,
HW_VAR_INT_MIGRATION,
HW_VAR_INT_AC,
HW_VAR_RF_TIMING,
HW_VAR_MRC,
HW_VAR_MGT_FILTER,
HW_VAR_CTRL_FILTER,
HW_VAR_DATA_FILTER,
HW_VAR_ETHER_ADDR,
HW_VAR_MULTICAST_REG,
HW_VAR_BASIC_RATE,
HW_VAR_BSSID,
HW_VAR_MEDIA_STATUS,
HW_VAR_SECURITY_CONF,
HW_VAR_BEACON_INTERVAL,
HW_VAR_ATIM_WINDOW,
HW_VAR_LISTEN_INTERVAL,
HW_VAR_CS_COUNTER,
HW_VAR_DEFAULTKEY0,
HW_VAR_DEFAULTKEY1,
HW_VAR_DEFAULTKEY2,
HW_VAR_DEFAULTKEY3,
HW_VAR_SIFS,
HW_VAR_DIFS,
HW_VAR_EIFS,
HW_VAR_SLOT_TIME,
HW_VAR_ACK_PREAMBLE,
HW_VAR_CW_CONFIG,
HW_VAR_CW_VALUES,
HW_VAR_RATE_FALLBACK_CONTROL,
HW_VAR_CONTENTION_WINDOW,
HW_VAR_RETRY_COUNT,
HW_VAR_TR_SWITCH,
HW_VAR_COMMAND,
HW_VAR_WPA_CONFIG,
HW_VAR_AMPDU_MIN_SPACE,
HW_VAR_SHORTGI_DENSITY,
HW_VAR_AMPDU_FACTOR,
HW_VAR_MCS_RATE_AVAILABLE,
HW_VAR_AC_PARAM,
HW_VAR_ACM_CTRL,
HW_VAR_DIS_Req_Qsize,
HW_VAR_CCX_CHNL_LOAD,
HW_VAR_CCX_NOISE_HISTOGRAM,
HW_VAR_CCX_CLM_NHM,
HW_VAR_TxOPLimit,
HW_VAR_TURBO_MODE,
HW_VAR_RF_STATE,
HW_VAR_RF_OFF_BY_HW,
HW_VAR_BUS_SPEED,
HW_VAR_SET_DEV_POWER,
HW_VAR_RCR,
HW_VAR_RATR_0,
HW_VAR_RRSR,
HW_VAR_CPU_RST,
HW_VAR_CECHK_BSSID,
HW_VAR_LBK_MODE,
HW_VAR_AES_11N_FIX,
HW_VAR_USB_RX_AGGR,
HW_VAR_USER_CONTROL_TURBO_MODE,
HW_VAR_RETRY_LIMIT,
HW_VAR_INIT_TX_RATE,
HW_VAR_TX_RATE_REG,
HW_VAR_EFUSE_USAGE,
HW_VAR_EFUSE_BYTES,
HW_VAR_AUTOLOAD_STATUS,
HW_VAR_RF_2R_DISABLE,
HW_VAR_SET_RPWM,
HW_VAR_H2C_FW_PWRMODE,
HW_VAR_H2C_FW_JOINBSSRPT,
HW_VAR_1X1_RECV_COMBINE,
HW_VAR_STOP_SEND_BEACON,
HW_VAR_TSF_TIMER,
HW_VAR_IO_CMD,
HW_VAR_RF_RECOVERY,
HW_VAR_H2C_FW_UPDATE_GTK,
HW_VAR_WF_MASK,
HW_VAR_WF_CRC,
HW_VAR_WF_IS_MAC_ADDR,
HW_VAR_H2C_FW_OFFLOAD,
HW_VAR_RESET_WFCRC,
HW_VAR_HANDLE_FW_C2H,
HW_VAR_DL_FW_RSVD_PAGE,
HW_VAR_AID,
HW_VAR_HW_SEQ_ENABLE,
HW_VAR_CORRECT_TSF,
HW_VAR_BCN_VALID,
HW_VAR_FWLPS_RF_ON,
HW_VAR_DUAL_TSF_RST,
HW_VAR_SWITCH_EPHY_WoWLAN,
HW_VAR_INT_MIGRATION,
HW_VAR_INT_AC,
HW_VAR_RF_TIMING
} |
| |
| enum | _RT_MEDIA_STATUS { RT_MEDIA_DISCONNECT = 0,
RT_MEDIA_CONNECT = 1
} |
| |
| enum | rt_oem_id {
RT_CID_DEFAULT = 0,
RT_CID_8187_ALPHA0 = 1,
RT_CID_8187_SERCOMM_PS = 2,
RT_CID_8187_HW_LED = 3,
RT_CID_8187_NETGEAR = 4,
RT_CID_WHQL = 5,
RT_CID_819x_CAMEO = 6,
RT_CID_819x_RUNTOP = 7,
RT_CID_819x_Senao = 8,
RT_CID_TOSHIBA = 9,
RT_CID_819x_Netcore = 10,
RT_CID_Nettronix = 11,
RT_CID_DLINK = 12,
RT_CID_PRONET = 13,
RT_CID_COREGA = 14,
RT_CID_819x_ALPHA = 15,
RT_CID_819x_Sitecom = 16,
RT_CID_CCX = 17,
RT_CID_819x_Lenovo = 18,
RT_CID_819x_QMI = 19,
RT_CID_819x_Edimax_Belkin = 20,
RT_CID_819x_Sercomm_Belkin = 21,
RT_CID_819x_CAMEO1 = 22,
RT_CID_819x_MSI = 23,
RT_CID_819x_Acer = 24,
RT_CID_819x_HP = 27,
RT_CID_819x_CLEVO = 28,
RT_CID_819x_Arcadyan_Belkin = 29,
RT_CID_819x_SAMSUNG = 30,
RT_CID_819x_WNC_COREGA = 31,
RT_CID_819x_Foxcoon = 32,
RT_CID_819x_DELL = 33
} |
| |
| enum | hw_descs {
HW_DESC_OWN,
HW_DESC_RXOWN,
HW_DESC_TX_NEXTDESC_ADDR,
HW_DESC_TXBUFF_ADDR,
HW_DESC_RXBUFF_ADDR,
HW_DESC_RXPKT_LEN,
HW_DESC_RXERO
} |
| |
| enum | prime_sc { PRIME_CHNL_OFFSET_DONT_CARE = 0,
PRIME_CHNL_OFFSET_LOWER = 1,
PRIME_CHNL_OFFSET_UPPER = 2
} |
| |
| enum | rf_type { RF_1T1R = 0,
RF_1T2R = 1,
RF_2T2R = 2,
RF_2T2R_GREEN = 3
} |
| |
| enum | ht_channel_width { HT_CHANNEL_WIDTH_20 = 0,
HT_CHANNEL_WIDTH_20_40 = 1,
HT_CHANNEL_WIDTH_20 = 0,
HT_CHANNEL_WIDTH_20_40 = 1
} |
| |
| enum | rt_enc_alg {
NO_ENCRYPTION = 0,
WEP40_ENCRYPTION = 1,
TKIP_ENCRYPTION = 2,
RSERVED_ENCRYPTION = 3,
AESCCMP_ENCRYPTION = 4,
WEP104_ENCRYPTION = 5,
AESCMAC_ENCRYPTION = 6
} |
| |
| enum | rtl_hal_state { _HAL_STATE_STOP = 0,
_HAL_STATE_START = 1
} |
| |
| enum | rtl_desc92_rate {
DESC92_RATE1M = 0x00,
DESC92_RATE2M = 0x01,
DESC92_RATE5_5M = 0x02,
DESC92_RATE11M = 0x03,
DESC92_RATE6M = 0x04,
DESC92_RATE9M = 0x05,
DESC92_RATE12M = 0x06,
DESC92_RATE18M = 0x07,
DESC92_RATE24M = 0x08,
DESC92_RATE36M = 0x09,
DESC92_RATE48M = 0x0a,
DESC92_RATE54M = 0x0b,
DESC92_RATEMCS0 = 0x0c,
DESC92_RATEMCS1 = 0x0d,
DESC92_RATEMCS2 = 0x0e,
DESC92_RATEMCS3 = 0x0f,
DESC92_RATEMCS4 = 0x10,
DESC92_RATEMCS5 = 0x11,
DESC92_RATEMCS6 = 0x12,
DESC92_RATEMCS7 = 0x13,
DESC92_RATEMCS8 = 0x14,
DESC92_RATEMCS9 = 0x15,
DESC92_RATEMCS10 = 0x16,
DESC92_RATEMCS11 = 0x17,
DESC92_RATEMCS12 = 0x18,
DESC92_RATEMCS13 = 0x19,
DESC92_RATEMCS14 = 0x1a,
DESC92_RATEMCS15 = 0x1b,
DESC92_RATEMCS15_SG = 0x1c,
DESC92_RATEMCS32 = 0x20
} |
| |
| enum | rtl_var_map {
SYS_ISO_CTRL = 0,
SYS_FUNC_EN,
SYS_CLK,
MAC_RCR_AM,
MAC_RCR_AB,
MAC_RCR_ACRC32,
MAC_RCR_ACF,
MAC_RCR_AAP,
EFUSE_TEST,
EFUSE_CTRL,
EFUSE_CLK,
EFUSE_CLK_CTRL,
EFUSE_PWC_EV12V,
EFUSE_FEN_ELDR,
EFUSE_LOADER_CLK_EN,
EFUSE_ANA8M,
EFUSE_HWSET_MAX_SIZE,
EFUSE_MAX_SECTION_MAP,
EFUSE_REAL_CONTENT_SIZE,
EFUSE_OOB_PROTECT_BYTES_LEN,
RWCAM,
WCAMI,
RCAMO,
CAMDBG,
SECR,
SEC_CAM_NONE,
SEC_CAM_WEP40,
SEC_CAM_TKIP,
SEC_CAM_AES,
SEC_CAM_WEP104,
RTL_IMR_BCNDMAINT6,
RTL_IMR_BCNDMAINT5,
RTL_IMR_BCNDMAINT4,
RTL_IMR_BCNDMAINT3,
RTL_IMR_BCNDMAINT2,
RTL_IMR_BCNDMAINT1,
RTL_IMR_BCNDOK8,
RTL_IMR_BCNDOK7,
RTL_IMR_BCNDOK6,
RTL_IMR_BCNDOK5,
RTL_IMR_BCNDOK4,
RTL_IMR_BCNDOK3,
RTL_IMR_BCNDOK2,
RTL_IMR_BCNDOK1,
RTL_IMR_TIMEOUT2,
RTL_IMR_TIMEOUT1,
RTL_IMR_TXFOVW,
RTL_IMR_PSTIMEOUT,
RTL_IMR_BcnInt,
RTL_IMR_RXFOVW,
RTL_IMR_RDU,
RTL_IMR_ATIMEND,
RTL_IMR_BDOK,
RTL_IMR_HIGHDOK,
RTL_IMR_COMDOK,
RTL_IMR_TBDOK,
RTL_IMR_MGNTDOK,
RTL_IMR_TBDER,
RTL_IMR_BKDOK,
RTL_IMR_BEDOK,
RTL_IMR_VIDOK,
RTL_IMR_VODOK,
RTL_IMR_ROK,
RTL_IBSS_INT_MASKS,
RTL_RC_CCK_RATE1M,
RTL_RC_CCK_RATE2M,
RTL_RC_CCK_RATE5_5M,
RTL_RC_CCK_RATE11M,
RTL_RC_OFDM_RATE6M,
RTL_RC_OFDM_RATE9M,
RTL_RC_OFDM_RATE12M,
RTL_RC_OFDM_RATE18M,
RTL_RC_OFDM_RATE24M,
RTL_RC_OFDM_RATE36M,
RTL_RC_OFDM_RATE48M,
RTL_RC_OFDM_RATE54M,
RTL_RC_HT_RATEMCS7,
RTL_RC_HT_RATEMCS15,
RTL_VAR_MAP_MAX
} |
| |
| enum | _fw_ps_mode {
FW_PS_ACTIVE_MODE = 0,
FW_PS_MIN_MODE = 1,
FW_PS_MAX_MODE = 2,
FW_PS_DTIM_MODE = 3,
FW_PS_VOIP_MODE = 4,
FW_PS_UAPSD_WMM_MODE = 5,
FW_PS_UAPSD_MODE = 6,
FW_PS_IBSS_MODE = 7,
FW_PS_WWLAN_MODE = 8,
FW_PS_PM_Radio_Off = 9,
FW_PS_PM_Card_Disable = 10
} |
| |
| enum | rt_psmode { EACTIVE,
EMAXPS,
EFASTPS,
EAUTOPS
} |
| |
| enum | led_ctl_mode {
LED_CTL_POWER_ON = 1,
LED_CTL_LINK = 2,
LED_CTL_NO_LINK = 3,
LED_CTL_TX = 4,
LED_CTL_RX = 5,
LED_CTL_SITE_SURVEY = 6,
LED_CTL_POWER_OFF = 7,
LED_CTL_START_TO_LINK = 8,
LED_CTL_START_WPS = 9,
LED_CTL_STOP_WPS = 10,
LED_CTL_POWER_ON = 1,
LED_CTL_LINK = 2,
LED_CTL_NO_LINK = 3,
LED_CTL_TX = 4,
LED_CTL_RX = 5,
LED_CTL_SITE_SURVEY = 6,
LED_CTL_POWER_OFF = 7,
LED_CTL_START_TO_LINK = 8,
LED_CTL_START_WPS = 9,
LED_CTL_STOP_WPS = 10,
LED_CTL_START_WPS_BOTTON = 11,
LED_CTL_STOP_WPS_FAIL = 12,
LED_CTL_STOP_WPS_FAIL_OVERLAP = 13
} |
| |
| enum | rtl_led_pin { LED_PIN_GPIO0,
LED_PIN_LED0,
LED_PIN_LED1,
LED_PIN_LED2
} |
| |
| enum | acm_method {
eAcmWay0_SwAndHw = 0,
eAcmWay1_HW = 1,
eAcmWay2_SW = 2,
eAcmWay0_SwAndHw = 0,
eAcmWay1_HW = 1,
eAcmWay2_SW = 2
} |
| |
| enum | macphy_mode { SINGLEMAC_SINGLEPHY = 0,
DUALMAC_DUALPHY,
DUALMAC_SINGLEPHY
} |
| |
| enum | band_type { BAND_ON_2_4G = 0,
BAND_ON_5G,
BAND_ON_BOTH,
BANDMAX
} |
| |
| enum | wireless_mode {
WIRELESS_MODE_UNKNOWN = 0x00,
WIRELESS_MODE_A = 0x01,
WIRELESS_MODE_B = 0x02,
WIRELESS_MODE_G = 0x04,
WIRELESS_MODE_AUTO = 0x08,
WIRELESS_MODE_N_24G = 0x10,
WIRELESS_MODE_N_5G = 0x20,
WIRELESS_MODE_UNKNOWN = 0x00,
WIRELESS_MODE_A = 0x01,
WIRELESS_MODE_B = 0x02,
WIRELESS_MODE_G = 0x04,
WIRELESS_MODE_AUTO = 0x08,
WIRELESS_MODE_N_24G = 0x10,
WIRELESS_MODE_N_5G = 0x20
} |
| |
| enum | ratr_table_mode {
RATR_INX_WIRELESS_NGB = 0,
RATR_INX_WIRELESS_NG = 1,
RATR_INX_WIRELESS_NB = 2,
RATR_INX_WIRELESS_N = 3,
RATR_INX_WIRELESS_GB = 4,
RATR_INX_WIRELESS_G = 5,
RATR_INX_WIRELESS_B = 6,
RATR_INX_WIRELESS_MC = 7,
RATR_INX_WIRELESS_A = 8
} |
| |
| enum | rtl_link_state { MAC80211_NOLINK = 0,
MAC80211_LINKING = 1,
MAC80211_LINKED = 2,
MAC80211_LINKED_SCANNING = 3
} |
| |
| enum | act_category {
ACT_CAT_QOS = 1,
ACT_CAT_DLS = 2,
ACT_CAT_BA = 3,
ACT_CAT_HT = 7,
ACT_CAT_WMM = 17,
ACT_CAT_QOS = 1,
ACT_CAT_DLS = 2,
ACT_CAT_BA = 3,
ACT_CAT_HT = 7,
ACT_CAT_WMM = 17
} |
| |
| enum | ba_action {
ACT_ADDBAREQ = 0,
ACT_ADDBARSP = 1,
ACT_DELBA = 2,
ACT_ADDBAREQ = 0,
ACT_ADDBARSP = 1,
ACT_DELBA = 2
} |
| |
| enum | hw_param_tab_index {
PHY_REG_2T,
PHY_REG_1T,
PHY_REG_PG,
RADIOA_2T,
RADIOB_2T,
RADIOA_1T,
RADIOB_1T,
MAC_REG,
AGCTAB_2T,
AGCTAB_1T,
MAX_TAB
} |
| |
| enum | bt_ant_num { ANT_X2 = 0,
ANT_X1 = 1
} |
| |
| enum | bt_co_type {
BT_2WIRE = 0,
BT_ISSC_3WIRE = 1,
BT_ACCEL = 2,
BT_CSR_BC4 = 3,
BT_CSR_BC8 = 4,
BT_RTL8756 = 5
} |
| |
| enum | bt_cur_state { BT_OFF = 0,
BT_ON = 1
} |
| |
| enum | bt_service_type {
BT_SCO = 0,
BT_A2DP = 1,
BT_HID = 2,
BT_HID_IDLE = 3,
BT_SCAN = 4,
BT_IDLE = 5,
BT_OTHER_ACTION = 6,
BT_BUSY = 7,
BT_OTHERBUSY = 8,
BT_PAN = 9
} |
| |
| enum | bt_radio_shared { BT_RADIO_SHARED = 0,
BT_RADIO_INDIVIDUAL = 1
} |
| |
1.8.2