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trx.h
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1 /******************************************************************************
2  *
3  * Copyright(c) 2009-2012 Realtek Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of version 2 of the GNU General Public License as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17  *
18  * The full GNU General Public License is included in this distribution in the
19  * file called LICENSE.
20  *
21  * Contact Information:
22  * wlanfae <[email protected]>
23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24  * Hsinchu 300, Taiwan.
25  *
26  * Larry Finger <[email protected]>
27  *
28  *****************************************************************************/
29 
30 #ifndef __RTL92DE_TRX_H__
31 #define __RTL92DE_TRX_H__
32 
33 #define TX_DESC_SIZE 64
34 #define TX_DESC_AGGR_SUBFRAME_SIZE 32
35 
36 #define RX_DESC_SIZE 32
37 #define RX_DRV_INFO_SIZE_UNIT 8
38 
39 #define TX_DESC_NEXT_DESC_OFFSET 40
40 #define USB_HWDESC_HEADER_LEN 32
41 #define CRCLENGTH 4
42 
43 /* Define a macro that takes a le32 word, converts it to host ordering,
44  * right shifts by a specified count, creates a mask of the specified
45  * bit count, and extracts that number of bits.
46  */
47 
48 #define SHIFT_AND_MASK_LE(__pdesc, __shift, __mask) \
49  ((le32_to_cpu(*(((__le32 *)(__pdesc)))) >> (__shift)) & \
50  BIT_LEN_MASK_32(__mask))
51 
52 /* Define a macro that clears a bit field in an le32 word and
53  * sets the specified value into that bit field. The resulting
54  * value remains in le32 ordering; however, it is properly converted
55  * to host ordering for the clear and set operations before conversion
56  * back to le32.
57  */
58 
59 #define SET_BITS_OFFSET_LE(__pdesc, __shift, __len, __val) \
60  (*(__le32 *)(__pdesc) = \
61  (cpu_to_le32((le32_to_cpu(*((__le32 *)(__pdesc))) & \
62  (~(BIT_OFFSET_LEN_MASK_32((__shift), __len)))) | \
63  (((u32)(__val) & BIT_LEN_MASK_32(__len)) << (__shift)))));
64 
65 /* macros to read/write various fields in RX or TX descriptors */
66 
67 #define SET_TX_DESC_PKT_SIZE(__pdesc, __val) \
68  SET_BITS_OFFSET_LE(__pdesc, 0, 16, __val)
69 #define SET_TX_DESC_OFFSET(__pdesc, __val) \
70  SET_BITS_OFFSET_LE(__pdesc, 16, 8, __val)
71 #define SET_TX_DESC_BMC(__pdesc, __val) \
72  SET_BITS_OFFSET_LE(__pdesc, 24, 1, __val)
73 #define SET_TX_DESC_HTC(__pdesc, __val) \
74  SET_BITS_OFFSET_LE(__pdesc, 25, 1, __val)
75 #define SET_TX_DESC_LAST_SEG(__pdesc, __val) \
76  SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val)
77 #define SET_TX_DESC_FIRST_SEG(__pdesc, __val) \
78  SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val)
79 #define SET_TX_DESC_LINIP(__pdesc, __val) \
80  SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val)
81 #define SET_TX_DESC_NO_ACM(__pdesc, __val) \
82  SET_BITS_OFFSET_LE(__pdesc, 29, 1, __val)
83 #define SET_TX_DESC_GF(__pdesc, __val) \
84  SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
85 #define SET_TX_DESC_OWN(__pdesc, __val) \
86  SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
87 
88 #define GET_TX_DESC_PKT_SIZE(__pdesc) \
89  SHIFT_AND_MASK_LE(__pdesc, 0, 16)
90 #define GET_TX_DESC_OFFSET(__pdesc) \
91  SHIFT_AND_MASK_LE(__pdesc, 16, 8)
92 #define GET_TX_DESC_BMC(__pdesc) \
93  SHIFT_AND_MASK_LE(__pdesc, 24, 1)
94 #define GET_TX_DESC_HTC(__pdesc) \
95  SHIFT_AND_MASK_LE(__pdesc, 25, 1)
96 #define GET_TX_DESC_LAST_SEG(__pdesc) \
97  SHIFT_AND_MASK_LE(__pdesc, 26, 1)
98 #define GET_TX_DESC_FIRST_SEG(__pdesc) \
99  SHIFT_AND_MASK_LE(__pdesc, 27, 1)
100 #define GET_TX_DESC_LINIP(__pdesc) \
101  SHIFT_AND_MASK_LE(__pdesc, 28, 1)
102 #define GET_TX_DESC_NO_ACM(__pdesc) \
103  SHIFT_AND_MASK_LE(__pdesc, 29, 1)
104 #define GET_TX_DESC_GF(__pdesc) \
105  SHIFT_AND_MASK_LE(__pdesc, 30, 1)
106 #define GET_TX_DESC_OWN(__pdesc) \
107  SHIFT_AND_MASK_LE(__pdesc, 31, 1)
108 
109 #define SET_TX_DESC_MACID(__pdesc, __val) \
110  SET_BITS_OFFSET_LE(__pdesc+4, 0, 5, __val)
111 #define SET_TX_DESC_AGG_ENABLE(__pdesc, __val) \
112  SET_BITS_OFFSET_LE(__pdesc+4, 5, 1, __val)
113 #define SET_TX_DESC_BK(__pdesc, __val) \
114  SET_BITS_OFFSET_LE(__pdesc+4, 6, 1, __val)
115 #define SET_TX_DESC_RDG_ENABLE(__pdesc, __val) \
116  SET_BITS_OFFSET_LE(__pdesc+4, 7, 1, __val)
117 #define SET_TX_DESC_QUEUE_SEL(__pdesc, __val) \
118  SET_BITS_OFFSET_LE(__pdesc+4, 8, 5, __val)
119 #define SET_TX_DESC_RDG_NAV_EXT(__pdesc, __val) \
120  SET_BITS_OFFSET_LE(__pdesc+4, 13, 1, __val)
121 #define SET_TX_DESC_LSIG_TXOP_EN(__pdesc, __val) \
122  SET_BITS_OFFSET_LE(__pdesc+4, 14, 1, __val)
123 #define SET_TX_DESC_PIFS(__pdesc, __val) \
124  SET_BITS_OFFSET_LE(__pdesc+4, 15, 1, __val)
125 #define SET_TX_DESC_RATE_ID(__pdesc, __val) \
126  SET_BITS_OFFSET_LE(__pdesc+4, 16, 4, __val)
127 #define SET_TX_DESC_NAV_USE_HDR(__pdesc, __val) \
128  SET_BITS_OFFSET_LE(__pdesc+4, 20, 1, __val)
129 #define SET_TX_DESC_EN_DESC_ID(__pdesc, __val) \
130  SET_BITS_OFFSET_LE(__pdesc+4, 21, 1, __val)
131 #define SET_TX_DESC_SEC_TYPE(__pdesc, __val) \
132  SET_BITS_OFFSET_LE(__pdesc+4, 22, 2, __val)
133 #define SET_TX_DESC_PKT_OFFSET(__pdesc, __val) \
134  SET_BITS_OFFSET_LE(__pdesc+4, 26, 8, __val)
135 
136 #define GET_TX_DESC_MACID(__pdesc) \
137  SHIFT_AND_MASK_LE(__pdesc+4, 0, 5)
138 #define GET_TX_DESC_AGG_ENABLE(__pdesc) \
139  SHIFT_AND_MASK_LE(__pdesc+4, 5, 1)
140 #define GET_TX_DESC_AGG_BREAK(__pdesc) \
141  SHIFT_AND_MASK_LE(__pdesc+4, 6, 1)
142 #define GET_TX_DESC_RDG_ENABLE(__pdesc) \
143  SHIFT_AND_MASK_LE(__pdesc+4, 7, 1)
144 #define GET_TX_DESC_QUEUE_SEL(__pdesc) \
145  SHIFT_AND_MASK_LE(__pdesc+4, 8, 5)
146 #define GET_TX_DESC_RDG_NAV_EXT(__pdesc) \
147  SHIFT_AND_MASK_LE(__pdesc+4, 13, 1)
148 #define GET_TX_DESC_LSIG_TXOP_EN(__pdesc) \
149  SHIFT_AND_MASK_LE(__pdesc+4, 14, 1)
150 #define GET_TX_DESC_PIFS(__pdesc) \
151  SHIFT_AND_MASK_LE(__pdesc+4, 15, 1)
152 #define GET_TX_DESC_RATE_ID(__pdesc) \
153  SHIFT_AND_MASK_LE(__pdesc+4, 16, 4)
154 #define GET_TX_DESC_NAV_USE_HDR(__pdesc) \
155  SHIFT_AND_MASK_LE(__pdesc+4, 20, 1)
156 #define GET_TX_DESC_EN_DESC_ID(__pdesc) \
157  SHIFT_AND_MASK_LE(__pdesc+4, 21, 1)
158 #define GET_TX_DESC_SEC_TYPE(__pdesc) \
159  SHIFT_AND_MASK_LE(__pdesc+4, 22, 2)
160 #define GET_TX_DESC_PKT_OFFSET(__pdesc) \
161  SHIFT_AND_MASK_LE(__pdesc+4, 24, 8)
162 
163 #define SET_TX_DESC_RTS_RC(__pdesc, __val) \
164  SET_BITS_OFFSET_LE(__pdesc+8, 0, 6, __val)
165 #define SET_TX_DESC_DATA_RC(__pdesc, __val) \
166  SET_BITS_OFFSET_LE(__pdesc+8, 6, 6, __val)
167 #define SET_TX_DESC_BAR_RTY_TH(__pdesc, __val) \
168  SET_BITS_OFFSET_LE(__pdesc+8, 14, 2, __val)
169 #define SET_TX_DESC_MORE_FRAG(__pdesc, __val) \
170  SET_BITS_OFFSET_LE(__pdesc+8, 17, 1, __val)
171 #define SET_TX_DESC_RAW(__pdesc, __val) \
172  SET_BITS_OFFSET_LE(__pdesc+8, 18, 1, __val)
173 #define SET_TX_DESC_CCX(__pdesc, __val) \
174  SET_BITS_OFFSET_LE(__pdesc+8, 19, 1, __val)
175 #define SET_TX_DESC_AMPDU_DENSITY(__pdesc, __val) \
176  SET_BITS_OFFSET_LE(__pdesc+8, 20, 3, __val)
177 #define SET_TX_DESC_ANTSEL_A(__pdesc, __val) \
178  SET_BITS_OFFSET_LE(__pdesc+8, 24, 1, __val)
179 #define SET_TX_DESC_ANTSEL_B(__pdesc, __val) \
180  SET_BITS_OFFSET_LE(__pdesc+8, 25, 1, __val)
181 #define SET_TX_DESC_TX_ANT_CCK(__pdesc, __val) \
182  SET_BITS_OFFSET_LE(__pdesc+8, 26, 2, __val)
183 #define SET_TX_DESC_TX_ANTL(__pdesc, __val) \
184  SET_BITS_OFFSET_LE(__pdesc+8, 28, 2, __val)
185 #define SET_TX_DESC_TX_ANT_HT(__pdesc, __val) \
186  SET_BITS_OFFSET_LE(__pdesc+8, 30, 2, __val)
187 
188 #define GET_TX_DESC_RTS_RC(__pdesc) \
189  SHIFT_AND_MASK_LE(__pdesc+8, 0, 6)
190 #define GET_TX_DESC_DATA_RC(__pdesc) \
191  SHIFT_AND_MASK_LE(__pdesc+8, 6, 6)
192 #define GET_TX_DESC_BAR_RTY_TH(__pdesc) \
193  SHIFT_AND_MASK_LE(__pdesc+8, 14, 2)
194 #define GET_TX_DESC_MORE_FRAG(__pdesc) \
195  SHIFT_AND_MASK_LE(__pdesc+8, 17, 1)
196 #define GET_TX_DESC_RAW(__pdesc) \
197  SHIFT_AND_MASK_LE(__pdesc+8, 18, 1)
198 #define GET_TX_DESC_CCX(__pdesc) \
199  SHIFT_AND_MASK_LE(__pdesc+8, 19, 1)
200 #define GET_TX_DESC_AMPDU_DENSITY(__pdesc) \
201  SHIFT_AND_MASK_LE(__pdesc+8, 20, 3)
202 #define GET_TX_DESC_ANTSEL_A(__pdesc) \
203  SHIFT_AND_MASK_LE(__pdesc+8, 24, 1)
204 #define GET_TX_DESC_ANTSEL_B(__pdesc) \
205  SHIFT_AND_MASK_LE(__pdesc+8, 25, 1)
206 #define GET_TX_DESC_TX_ANT_CCK(__pdesc) \
207  SHIFT_AND_MASK_LE(__pdesc+8, 26, 2)
208 #define GET_TX_DESC_TX_ANTL(__pdesc) \
209  SHIFT_AND_MASK_LE(__pdesc+8, 28, 2)
210 #define GET_TX_DESC_TX_ANT_HT(__pdesc) \
211  SHIFT_AND_MASK_LE(__pdesc+8, 30, 2)
212 
213 #define SET_TX_DESC_NEXT_HEAP_PAGE(__pdesc, __val) \
214  SET_BITS_OFFSET_LE(__pdesc+12, 0, 8, __val)
215 #define SET_TX_DESC_TAIL_PAGE(__pdesc, __val) \
216  SET_BITS_OFFSET_LE(__pdesc+12, 8, 8, __val)
217 #define SET_TX_DESC_SEQ(__pdesc, __val) \
218  SET_BITS_OFFSET_LE(__pdesc+12, 16, 12, __val)
219 #define SET_TX_DESC_PKT_ID(__pdesc, __val) \
220  SET_BITS_OFFSET_LE(__pdesc+12, 28, 4, __val)
221 
222 #define GET_TX_DESC_NEXT_HEAP_PAGE(__pdesc) \
223  SHIFT_AND_MASK_LE(__pdesc+12, 0, 8)
224 #define GET_TX_DESC_TAIL_PAGE(__pdesc) \
225  SHIFT_AND_MASK_LE(__pdesc+12, 8, 8)
226 #define GET_TX_DESC_SEQ(__pdesc) \
227  SHIFT_AND_MASK_LE(__pdesc+12, 16, 12)
228 #define GET_TX_DESC_PKT_ID(__pdesc) \
229  SHIFT_AND_MASK_LE(__pdesc+12, 28, 4)
230 
231 #define SET_TX_DESC_RTS_RATE(__pdesc, __val) \
232  SET_BITS_OFFSET_LE(__pdesc+16, 0, 5, __val)
233 #define SET_TX_DESC_AP_DCFE(__pdesc, __val) \
234  SET_BITS_OFFSET_LE(__pdesc+16, 5, 1, __val)
235 #define SET_TX_DESC_QOS(__pdesc, __val) \
236  SET_BITS_OFFSET_LE(__pdesc+16, 6, 1, __val)
237 #define SET_TX_DESC_HWSEQ_EN(__pdesc, __val) \
238  SET_BITS_OFFSET_LE(__pdesc+16, 7, 1, __val)
239 #define SET_TX_DESC_USE_RATE(__pdesc, __val) \
240  SET_BITS_OFFSET_LE(__pdesc+16, 8, 1, __val)
241 #define SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val) \
242  SET_BITS_OFFSET_LE(__pdesc+16, 9, 1, __val)
243 #define SET_TX_DESC_DISABLE_FB(__pdesc, __val) \
244  SET_BITS_OFFSET_LE(__pdesc+16, 10, 1, __val)
245 #define SET_TX_DESC_CTS2SELF(__pdesc, __val) \
246  SET_BITS_OFFSET_LE(__pdesc+16, 11, 1, __val)
247 #define SET_TX_DESC_RTS_ENABLE(__pdesc, __val) \
248  SET_BITS_OFFSET_LE(__pdesc+16, 12, 1, __val)
249 #define SET_TX_DESC_HW_RTS_ENABLE(__pdesc, __val) \
250  SET_BITS_OFFSET_LE(__pdesc+16, 13, 1, __val)
251 #define SET_TX_DESC_PORT_ID(__pdesc, __val) \
252  SET_BITS_OFFSET_LE(__pdesc+16, 14, 1, __val)
253 #define SET_TX_DESC_WAIT_DCTS(__pdesc, __val) \
254  SET_BITS_OFFSET_LE(__pdesc+16, 18, 1, __val)
255 #define SET_TX_DESC_CTS2AP_EN(__pdesc, __val) \
256  SET_BITS_OFFSET_LE(__pdesc+16, 19, 1, __val)
257 #define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val) \
258  SET_BITS_OFFSET_LE(__pdesc+16, 20, 2, __val)
259 #define SET_TX_DESC_TX_STBC(__pdesc, __val) \
260  SET_BITS_OFFSET_LE(__pdesc+16, 22, 2, __val)
261 #define SET_TX_DESC_DATA_SHORT(__pdesc, __val) \
262  SET_BITS_OFFSET_LE(__pdesc+16, 24, 1, __val)
263 #define SET_TX_DESC_DATA_BW(__pdesc, __val) \
264  SET_BITS_OFFSET_LE(__pdesc+16, 25, 1, __val)
265 #define SET_TX_DESC_RTS_SHORT(__pdesc, __val) \
266  SET_BITS_OFFSET_LE(__pdesc+16, 26, 1, __val)
267 #define SET_TX_DESC_RTS_BW(__pdesc, __val) \
268  SET_BITS_OFFSET_LE(__pdesc+16, 27, 1, __val)
269 #define SET_TX_DESC_RTS_SC(__pdesc, __val) \
270  SET_BITS_OFFSET_LE(__pdesc+16, 28, 2, __val)
271 #define SET_TX_DESC_RTS_STBC(__pdesc, __val) \
272  SET_BITS_OFFSET_LE(__pdesc+16, 30, 2, __val)
273 
274 #define GET_TX_DESC_RTS_RATE(__pdesc) \
275  SHIFT_AND_MASK_LE(__pdesc+16, 0, 5)
276 #define GET_TX_DESC_AP_DCFE(__pdesc) \
277  SHIFT_AND_MASK_LE(__pdesc+16, 5, 1)
278 #define GET_TX_DESC_QOS(__pdesc) \
279  SHIFT_AND_MASK_LE(__pdesc+16, 6, 1)
280 #define GET_TX_DESC_HWSEQ_EN(__pdesc) \
281  SHIFT_AND_MASK_LE(__pdesc+16, 7, 1)
282 #define GET_TX_DESC_USE_RATE(__pdesc) \
283  SHIFT_AND_MASK_LE(__pdesc+16, 8, 1)
284 #define GET_TX_DESC_DISABLE_RTS_FB(__pdesc) \
285  SHIFT_AND_MASK_LE(__pdesc+16, 9, 1)
286 #define GET_TX_DESC_DISABLE_FB(__pdesc) \
287  SHIFT_AND_MASK_LE(__pdesc+16, 10, 1)
288 #define GET_TX_DESC_CTS2SELF(__pdesc) \
289  SHIFT_AND_MASK_LE(__pdesc+16, 11, 1)
290 #define GET_TX_DESC_RTS_ENABLE(__pdesc) \
291  SHIFT_AND_MASK_LE(__pdesc+16, 12, 1)
292 #define GET_TX_DESC_HW_RTS_ENABLE(__pdesc) \
293  SHIFT_AND_MASK_LE(__pdesc+16, 13, 1)
294 #define GET_TX_DESC_PORT_ID(__pdesc) \
295  SHIFT_AND_MASK_LE(__pdesc+16, 14, 1)
296 #define GET_TX_DESC_WAIT_DCTS(__pdesc) \
297  SHIFT_AND_MASK_LE(__pdesc+16, 18, 1)
298 #define GET_TX_DESC_CTS2AP_EN(__pdesc) \
299  SHIFT_AND_MASK_LE(__pdesc+16, 19, 1)
300 #define GET_TX_DESC_TX_SUB_CARRIER(__pdesc) \
301  SHIFT_AND_MASK_LE(__pdesc+16, 20, 2)
302 #define GET_TX_DESC_TX_STBC(__pdesc) \
303  SHIFT_AND_MASK_LE(__pdesc+16, 22, 2)
304 #define GET_TX_DESC_DATA_SHORT(__pdesc) \
305  SHIFT_AND_MASK_LE(__pdesc+16, 24, 1)
306 #define GET_TX_DESC_DATA_BW(__pdesc) \
307  SHIFT_AND_MASK_LE(__pdesc+16, 25, 1)
308 #define GET_TX_DESC_RTS_SHORT(__pdesc) \
309  SHIFT_AND_MASK_LE(__pdesc+16, 26, 1)
310 #define GET_TX_DESC_RTS_BW(__pdesc) \
311  SHIFT_AND_MASK_LE(__pdesc+16, 27, 1)
312 #define GET_TX_DESC_RTS_SC(__pdesc) \
313  SHIFT_AND_MASK_LE(__pdesc+16, 28, 2)
314 #define GET_TX_DESC_RTS_STBC(__pdesc) \
315  SHIFT_AND_MASK_LE(__pdesc+16, 30, 2)
316 
317 #define SET_TX_DESC_TX_RATE(__pdesc, __val) \
318  SET_BITS_OFFSET_LE(__pdesc+20, 0, 6, __val)
319 #define SET_TX_DESC_DATA_SHORTGI(__pdesc, __val) \
320  SET_BITS_OFFSET_LE(__pdesc+20, 6, 1, __val)
321 #define SET_TX_DESC_CCX_TAG(__pdesc, __val) \
322  SET_BITS_OFFSET_LE(__pdesc+20, 7, 1, __val)
323 #define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val) \
324  SET_BITS_OFFSET_LE(__pdesc+20, 8, 5, __val)
325 #define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val) \
326  SET_BITS_OFFSET_LE(__pdesc+20, 13, 4, __val)
327 #define SET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc, __val) \
328  SET_BITS_OFFSET_LE(__pdesc+20, 17, 1, __val)
329 #define SET_TX_DESC_DATA_RETRY_LIMIT(__pdesc, __val) \
330  SET_BITS_OFFSET_LE(__pdesc+20, 18, 6, __val)
331 #define SET_TX_DESC_USB_TXAGG_NUM(__pdesc, __val) \
332  SET_BITS_OFFSET_LE(__pdesc+20, 24, 8, __val)
333 
334 #define GET_TX_DESC_TX_RATE(__pdesc) \
335  SHIFT_AND_MASK_LE(__pdesc+20, 0, 6)
336 #define GET_TX_DESC_DATA_SHORTGI(__pdesc) \
337  SHIFT_AND_MASK_LE(__pdesc+20, 6, 1)
338 #define GET_TX_DESC_CCX_TAG(__pdesc) \
339  SHIFT_AND_MASK_LE(__pdesc+20, 7, 1)
340 #define GET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc) \
341  SHIFT_AND_MASK_LE(__pdesc+20, 8, 5)
342 #define GET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc) \
343  SHIFT_AND_MASK_LE(__pdesc+20, 13, 4)
344 #define GET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc) \
345  SHIFT_AND_MASK_LE(__pdesc+20, 17, 1)
346 #define GET_TX_DESC_DATA_RETRY_LIMIT(__pdesc) \
347  SHIFT_AND_MASK_LE(__pdesc+20, 18, 6)
348 #define GET_TX_DESC_USB_TXAGG_NUM(__pdesc) \
349  SHIFT_AND_MASK_LE(__pdesc+20, 24, 8)
350 
351 #define SET_TX_DESC_TXAGC_A(__pdesc, __val) \
352  SET_BITS_OFFSET_LE(__pdesc+24, 0, 5, __val)
353 #define SET_TX_DESC_TXAGC_B(__pdesc, __val) \
354  SET_BITS_OFFSET_LE(__pdesc+24, 5, 5, __val)
355 #define SET_TX_DESC_USE_MAX_LEN(__pdesc, __val) \
356  SET_BITS_OFFSET_LE(__pdesc+24, 10, 1, __val)
357 #define SET_TX_DESC_MAX_AGG_NUM(__pdesc, __val) \
358  SET_BITS_OFFSET_LE(__pdesc+24, 11, 5, __val)
359 #define SET_TX_DESC_MCSG1_MAX_LEN(__pdesc, __val) \
360  SET_BITS_OFFSET_LE(__pdesc+24, 16, 4, __val)
361 #define SET_TX_DESC_MCSG2_MAX_LEN(__pdesc, __val) \
362  SET_BITS_OFFSET_LE(__pdesc+24, 20, 4, __val)
363 #define SET_TX_DESC_MCSG3_MAX_LEN(__pdesc, __val) \
364  SET_BITS_OFFSET_LE(__pdesc+24, 24, 4, __val)
365 #define SET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc, __val) \
366  SET_BITS_OFFSET_LE(__pdesc+24, 28, 4, __val)
367 
368 #define GET_TX_DESC_TXAGC_A(__pdesc) \
369  SHIFT_AND_MASK_LE(__pdesc+24, 0, 5)
370 #define GET_TX_DESC_TXAGC_B(__pdesc) \
371  SHIFT_AND_MASK_LE(__pdesc+24, 5, 5)
372 #define GET_TX_DESC_USE_MAX_LEN(__pdesc) \
373  SHIFT_AND_MASK_LE(__pdesc+24, 10, 1)
374 #define GET_TX_DESC_MAX_AGG_NUM(__pdesc) \
375  SHIFT_AND_MASK_LE(__pdesc+24, 11, 5)
376 #define GET_TX_DESC_MCSG1_MAX_LEN(__pdesc) \
377  SHIFT_AND_MASK_LE(__pdesc+24, 16, 4)
378 #define GET_TX_DESC_MCSG2_MAX_LEN(__pdesc) \
379  SHIFT_AND_MASK_LE(__pdesc+24, 20, 4)
380 #define GET_TX_DESC_MCSG3_MAX_LEN(__pdesc) \
381  SHIFT_AND_MASK_LE(__pdesc+24, 24, 4)
382 #define GET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc) \
383  SHIFT_AND_MASK_LE(__pdesc+24, 28, 4)
384 
385 #define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val) \
386  SET_BITS_OFFSET_LE(__pdesc+28, 0, 16, __val)
387 #define SET_TX_DESC_MCSG4_MAX_LEN(__pdesc, __val) \
388  SET_BITS_OFFSET_LE(__pdesc+28, 16, 4, __val)
389 #define SET_TX_DESC_MCSG5_MAX_LEN(__pdesc, __val) \
390  SET_BITS_OFFSET_LE(__pdesc+28, 20, 4, __val)
391 #define SET_TX_DESC_MCSG6_MAX_LEN(__pdesc, __val) \
392  SET_BITS_OFFSET_LE(__pdesc+28, 24, 4, __val)
393 #define SET_TX_DESC_MCS15_SGI_MAX_LEN(__pdesc, __val) \
394  SET_BITS_OFFSET_LE(__pdesc+28, 28, 4, __val)
395 
396 #define GET_TX_DESC_TX_BUFFER_SIZE(__pdesc) \
397  SHIFT_AND_MASK_LE(__pdesc+28, 0, 16)
398 #define GET_TX_DESC_MCSG4_MAX_LEN(__pdesc) \
399  SHIFT_AND_MASK_LE(__pdesc+28, 16, 4)
400 #define GET_TX_DESC_MCSG5_MAX_LEN(__pdesc) \
401  SHIFT_AND_MASK_LE(__pdesc+28, 20, 4)
402 #define GET_TX_DESC_MCSG6_MAX_LEN(__pdesc) \
403  SHIFT_AND_MASK_LE(__pdesc+28, 24, 4)
404 #define GET_TX_DESC_MCS15_SGI_MAX_LEN(__pdesc) \
405  SHIFT_AND_MASK_LE(__pdesc+28, 28, 4)
406 
407 #define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val) \
408  SET_BITS_OFFSET_LE(__pdesc+32, 0, 32, __val)
409 #define SET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc, __val) \
410  SET_BITS_OFFSET_LE(__pdesc+36, 0, 32, __val)
411 
412 #define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc) \
413  SHIFT_AND_MASK_LE(__pdesc+32, 0, 32)
414 #define GET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc) \
415  SHIFT_AND_MASK_LE(__pdesc+36, 0, 32)
416 
417 #define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) \
418  SET_BITS_OFFSET_LE(__pdesc+40, 0, 32, __val)
419 #define SET_TX_DESC_NEXT_DESC_ADDRESS64(__pdesc, __val) \
420  SET_BITS_OFFSET_LE(__pdesc+44, 0, 32, __val)
421 
422 #define GET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc) \
423  SHIFT_AND_MASK_LE(__pdesc+40, 0, 32)
424 #define GET_TX_DESC_NEXT_DESC_ADDRESS64(__pdesc) \
425  SHIFT_AND_MASK_LE(__pdesc+44, 0, 32)
426 
427 #define GET_RX_DESC_PKT_LEN(__pdesc) \
428  SHIFT_AND_MASK_LE(__pdesc, 0, 14)
429 #define GET_RX_DESC_CRC32(__pdesc) \
430  SHIFT_AND_MASK_LE(__pdesc, 14, 1)
431 #define GET_RX_DESC_ICV(__pdesc) \
432  SHIFT_AND_MASK_LE(__pdesc, 15, 1)
433 #define GET_RX_DESC_DRV_INFO_SIZE(__pdesc) \
434  SHIFT_AND_MASK_LE(__pdesc, 16, 4)
435 #define GET_RX_DESC_SECURITY(__pdesc) \
436  SHIFT_AND_MASK_LE(__pdesc, 20, 3)
437 #define GET_RX_DESC_QOS(__pdesc) \
438  SHIFT_AND_MASK_LE(__pdesc, 23, 1)
439 #define GET_RX_DESC_SHIFT(__pdesc) \
440  SHIFT_AND_MASK_LE(__pdesc, 24, 2)
441 #define GET_RX_DESC_PHYST(__pdesc) \
442  SHIFT_AND_MASK_LE(__pdesc, 26, 1)
443 #define GET_RX_DESC_SWDEC(__pdesc) \
444  SHIFT_AND_MASK_LE(__pdesc, 27, 1)
445 #define GET_RX_DESC_LS(__pdesc) \
446  SHIFT_AND_MASK_LE(__pdesc, 28, 1)
447 #define GET_RX_DESC_FS(__pdesc) \
448  SHIFT_AND_MASK_LE(__pdesc, 29, 1)
449 #define GET_RX_DESC_EOR(__pdesc) \
450  SHIFT_AND_MASK_LE(__pdesc, 30, 1)
451 #define GET_RX_DESC_OWN(__pdesc) \
452  SHIFT_AND_MASK_LE(__pdesc, 31, 1)
453 
454 #define SET_RX_DESC_PKT_LEN(__pdesc, __val) \
455  SET_BITS_OFFSET_LE(__pdesc, 0, 14, __val)
456 #define SET_RX_DESC_EOR(__pdesc, __val) \
457  SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
458 #define SET_RX_DESC_OWN(__pdesc, __val) \
459  SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
460 
461 #define GET_RX_DESC_MACID(__pdesc) \
462  SHIFT_AND_MASK_LE(__pdesc+4, 0, 5)
463 #define GET_RX_DESC_TID(__pdesc) \
464  SHIFT_AND_MASK_LE(__pdesc+4, 5, 4)
465 #define GET_RX_DESC_HWRSVD(__pdesc) \
466  SHIFT_AND_MASK_LE(__pdesc+4, 9, 5)
467 #define GET_RX_DESC_PAGGR(__pdesc) \
468  SHIFT_AND_MASK_LE(__pdesc+4, 14, 1)
469 #define GET_RX_DESC_FAGGR(__pdesc) \
470  SHIFT_AND_MASK_LE(__pdesc+4, 15, 1)
471 #define GET_RX_DESC_A1_FIT(__pdesc) \
472  SHIFT_AND_MASK_LE(__pdesc+4, 16, 4)
473 #define GET_RX_DESC_A2_FIT(__pdesc) \
474  SHIFT_AND_MASK_LE(__pdesc+4, 20, 4)
475 #define GET_RX_DESC_PAM(__pdesc) \
476  SHIFT_AND_MASK_LE(__pdesc+4, 24, 1)
477 #define GET_RX_DESC_PWR(__pdesc) \
478  SHIFT_AND_MASK_LE(__pdesc+4, 25, 1)
479 #define GET_RX_DESC_MD(__pdesc) \
480  SHIFT_AND_MASK_LE(__pdesc+4, 26, 1)
481 #define GET_RX_DESC_MF(__pdesc) \
482  SHIFT_AND_MASK_LE(__pdesc+4, 27, 1)
483 #define GET_RX_DESC_TYPE(__pdesc) \
484  SHIFT_AND_MASK_LE(__pdesc+4, 28, 2)
485 #define GET_RX_DESC_MC(__pdesc) \
486  SHIFT_AND_MASK_LE(__pdesc+4, 30, 1)
487 #define GET_RX_DESC_BC(__pdesc) \
488  SHIFT_AND_MASK_LE(__pdesc+4, 31, 1)
489 #define GET_RX_DESC_SEQ(__pdesc) \
490  SHIFT_AND_MASK_LE(__pdesc+8, 0, 12)
491 #define GET_RX_DESC_FRAG(__pdesc) \
492  SHIFT_AND_MASK_LE(__pdesc+8, 12, 4)
493 #define GET_RX_DESC_NEXT_PKT_LEN(__pdesc) \
494  SHIFT_AND_MASK_LE(__pdesc+8, 16, 14)
495 #define GET_RX_DESC_NEXT_IND(__pdesc) \
496  SHIFT_AND_MASK_LE(__pdesc+8, 30, 1)
497 #define GET_RX_DESC_RSVD(__pdesc) \
498  SHIFT_AND_MASK_LE(__pdesc+8, 31, 1)
499 
500 #define GET_RX_DESC_RXMCS(__pdesc) \
501  SHIFT_AND_MASK_LE(__pdesc+12, 0, 6)
502 #define GET_RX_DESC_RXHT(__pdesc) \
503  SHIFT_AND_MASK_LE(__pdesc+12, 6, 1)
504 #define GET_RX_DESC_SPLCP(__pdesc) \
505  SHIFT_AND_MASK_LE(__pdesc+12, 8, 1)
506 #define GET_RX_DESC_BW(__pdesc) \
507  SHIFT_AND_MASK_LE(__pdesc+12, 9, 1)
508 #define GET_RX_DESC_HTC(__pdesc) \
509  SHIFT_AND_MASK_LE(__pdesc+12, 10, 1)
510 #define GET_RX_DESC_HWPC_ERR(__pdesc) \
511  SHIFT_AND_MASK_LE(__pdesc+12, 14, 1)
512 #define GET_RX_DESC_HWPC_IND(__pdesc) \
513  SHIFT_AND_MASK_LE(__pdesc+12, 15, 1)
514 #define GET_RX_DESC_IV0(__pdesc) \
515  SHIFT_AND_MASK_LE(__pdesc+12, 16, 16)
516 
517 #define GET_RX_DESC_IV1(__pdesc) \
518  SHIFT_AND_MASK_LE(__pdesc+16, 0, 32)
519 #define GET_RX_DESC_TSFL(__pdesc) \
520  SHIFT_AND_MASK_LE(__pdesc+20, 0, 32)
521 
522 #define GET_RX_DESC_BUFF_ADDR(__pdesc) \
523  SHIFT_AND_MASK_LE(__pdesc+24, 0, 32)
524 #define GET_RX_DESC_BUFF_ADDR64(__pdesc) \
525  SHIFT_AND_MASK_LE(__pdesc+28, 0, 32)
526 
527 #define SET_RX_DESC_BUFF_ADDR(__pdesc, __val) \
528  SET_BITS_OFFSET_LE(__pdesc+24, 0, 32, __val)
529 #define SET_RX_DESC_BUFF_ADDR64(__pdesc, __val) \
530  SET_BITS_OFFSET_LE(__pdesc+28, 0, 32, __val)
531 
532 #define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \
533  memset((void *)__pdesc, 0, \
534  min_t(size_t, _size, TX_DESC_NEXT_DESC_OFFSET))
535 
536 /* For 92D early mode */
537 #define SET_EARLYMODE_PKTNUM(__paddr, __value) \
538  SET_BITS_OFFSET_LE(__paddr, 0, 3, __value)
539 #define SET_EARLYMODE_LEN0(__paddr, __value) \
540  SET_BITS_OFFSET_LE(__paddr, 4, 12, __value)
541 #define SET_EARLYMODE_LEN1(__paddr, __value) \
542  SET_BITS_OFFSET_LE(__paddr, 16, 12, __value)
543 #define SET_EARLYMODE_LEN2_1(__paddr, __value) \
544  SET_BITS_OFFSET_LE(__paddr, 28, 4, __value)
545 #define SET_EARLYMODE_LEN2_2(__paddr, __value) \
546  SET_BITS_OFFSET_LE(__paddr+4, 0, 8, __value)
547 #define SET_EARLYMODE_LEN3(__paddr, __value) \
548  SET_BITS_OFFSET_LE(__paddr+4, 8, 12, __value)
549 #define SET_EARLYMODE_LEN4(__paddr, __value) \
550  SET_BITS_OFFSET_LE(__paddr+4, 20, 12, __value)
551 
552 struct rx_fwinfo_92d {
553  u8 gain_trsw[4];
554  u8 pwdb_all;
555  u8 cfosho[4];
556  u8 cfotail[4];
557  char rxevm[2];
558  char rxsnr[4];
559  u8 pdsnr[2];
560  u8 csi_current[2];
561  u8 csi_target[2];
562  u8 sigevm;
563  u8 max_ex_pwr;
564  u8 ex_intf_flag:1;
565  u8 sgi_en:1;
566  u8 rxsc:2;
567  u8 reserve:4;
568 } __packed;
569 
570 struct tx_desc_92d {
571  u32 pktsize:16;
572  u32 offset:8;
573  u32 bmc:1;
574  u32 htc:1;
575  u32 lastseg:1;
576  u32 firstseg:1;
577  u32 linip:1;
578  u32 noacm:1;
579  u32 gf:1;
580  u32 own:1;
581 
582  u32 macid:5;
583  u32 agg_en:1;
584  u32 bk:1;
585  u32 rdg_en:1;
586  u32 queuesel:5;
587  u32 rd_nav_ext:1;
588  u32 lsig_txop_en:1;
589  u32 pifs:1;
590  u32 rateid:4;
591  u32 nav_usehdr:1;
592  u32 en_descid:1;
593  u32 sectype:2;
594  u32 pktoffset:8;
595 
596  u32 rts_rc:6;
597  u32 data_rc:6;
598  u32 rsvd0:2;
599  u32 bar_retryht:2;
600  u32 rsvd1:1;
601  u32 morefrag:1;
602  u32 raw:1;
603  u32 ccx:1;
604  u32 ampdudensity:3;
605  u32 rsvd2:1;
606  u32 ant_sela:1;
607  u32 ant_selb:1;
608  u32 txant_cck:2;
609  u32 txant_l:2;
610  u32 txant_ht:2;
611 
612  u32 nextheadpage:8;
613  u32 tailpage:8;
614  u32 seq:12;
615  u32 pktid:4;
616 
617  u32 rtsrate:5;
618  u32 apdcfe:1;
619  u32 qos:1;
620  u32 hwseq_enable:1;
621  u32 userrate:1;
622  u32 dis_rtsfb:1;
623  u32 dis_datafb:1;
624  u32 cts2self:1;
625  u32 rts_en:1;
626  u32 hwrts_en:1;
627  u32 portid:1;
628  u32 rsvd3:3;
629  u32 waitdcts:1;
630  u32 cts2ap_en:1;
631  u32 txsc:2;
632  u32 stbc:2;
633  u32 txshort:1;
634  u32 txbw:1;
635  u32 rtsshort:1;
636  u32 rtsbw:1;
637  u32 rtssc:2;
638  u32 rtsstbc:2;
639 
640  u32 txrate:6;
641  u32 shortgi:1;
642  u32 ccxt:1;
643  u32 txrate_fb_lmt:5;
644  u32 rtsrate_fb_lmt:4;
645  u32 retrylmt_en:1;
646  u32 txretrylmt:6;
647  u32 usb_txaggnum:8;
648 
649  u32 txagca:5;
650  u32 txagcb:5;
651  u32 usemaxlen:1;
652  u32 maxaggnum:5;
653  u32 mcsg1maxlen:4;
654  u32 mcsg2maxlen:4;
655  u32 mcsg3maxlen:4;
656  u32 mcs7sgimaxlen:4;
657 
658  u32 txbuffersize:16;
659  u32 mcsg4maxlen:4;
660  u32 mcsg5maxlen:4;
661  u32 mcsg6maxlen:4;
662  u32 mcsg15sgimaxlen:4;
663 
664  u32 txbuffaddr;
665  u32 txbufferaddr64;
666  u32 nextdescaddress;
667  u32 nextdescaddress64;
668 
669  u32 reserve_pass_pcie_mm_limit[4];
670 } __packed;
671 
672 struct rx_desc_92d {
673  u32 length:14;
674  u32 crc32:1;
675  u32 icverror:1;
676  u32 drv_infosize:4;
677  u32 security:3;
678  u32 qos:1;
679  u32 shift:2;
680  u32 phystatus:1;
681  u32 swdec:1;
682  u32 lastseg:1;
683  u32 firstseg:1;
684  u32 eor:1;
685  u32 own:1;
686 
687  u32 macid:5;
688  u32 tid:4;
689  u32 hwrsvd:5;
690  u32 paggr:1;
691  u32 faggr:1;
692  u32 a1_fit:4;
693  u32 a2_fit:4;
694  u32 pam:1;
695  u32 pwr:1;
696  u32 moredata:1;
697  u32 morefrag:1;
698  u32 type:2;
699  u32 mc:1;
700  u32 bc:1;
701 
702  u32 seq:12;
703  u32 frag:4;
704  u32 nextpktlen:14;
705  u32 nextind:1;
706  u32 rsvd:1;
707 
708  u32 rxmcs:6;
709  u32 rxht:1;
710  u32 amsdu:1;
711  u32 splcp:1;
712  u32 bandwidth:1;
713  u32 htc:1;
714  u32 tcpchk_rpt:1;
715  u32 ipcchk_rpt:1;
716  u32 tcpchk_valid:1;
717  u32 hwpcerr:1;
718  u32 hwpcind:1;
719  u32 iv0:16;
720 
721  u32 iv1;
722 
723  u32 tsfl;
724 
725  u32 bufferaddress;
726  u32 bufferaddress64;
727 
728 } __packed;
729 
730 void rtl92de_tx_fill_desc(struct ieee80211_hw *hw,
731  struct ieee80211_hdr *hdr,
732  u8 *pdesc, struct ieee80211_tx_info *info,
733  struct ieee80211_sta *sta,
734  struct sk_buff *skb, u8 hw_queue,
735  struct rtl_tcb_desc *ptcb_desc);
736 bool rtl92de_rx_query_desc(struct ieee80211_hw *hw,
737  struct rtl_stats *stats,
738  struct ieee80211_rx_status *rx_status,
739  u8 *pdesc, struct sk_buff *skb);
740 void rtl92de_set_desc(u8 *pdesc, bool istx, u8 desc_name, u8 *val);
741 u32 rtl92de_get_desc(u8 *pdesc, bool istx, u8 desc_name);
742 void rtl92de_tx_polling(struct ieee80211_hw *hw, u8 hw_queue);
743 void rtl92de_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
744  bool b_firstseg, bool b_lastseg,
745  struct sk_buff *skb);
746 
747 #endif
Generated on Thu Jan 10 2013 14:13:08 for Linux Kernel by   doxygen 1.8.2