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s3c2440-pll-12000000.c
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1 /* arch/arm/mach-s3c2440/s3c2440-pll-12000000.c
2  *
3  * Copyright (c) 2006-2007 Simtec Electronics
4  * http://armlinux.simtec.co.uk/
5  * Ben Dooks <[email protected]>
6  * Vincent Sanders <[email protected]>
7  *
8  * S3C2440/S3C2442 CPU PLL tables (12MHz Crystal)
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License version 2 as
12  * published by the Free Software Foundation.
13 */
14 
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/device.h>
18 #include <linux/clk.h>
19 #include <linux/err.h>
20 
21 #include <plat/cpu.h>
22 #include <plat/cpu-freq-core.h>
23 
24 static struct cpufreq_frequency_table s3c2440_plls_12[] __initdata = {
25  { .frequency = 75000000, .index = PLLVAL(0x75, 3, 3), }, /* FVco 600.000000 */
26  { .frequency = 80000000, .index = PLLVAL(0x98, 4, 3), }, /* FVco 640.000000 */
27  { .frequency = 90000000, .index = PLLVAL(0x70, 2, 3), }, /* FVco 720.000000 */
28  { .frequency = 100000000, .index = PLLVAL(0x5c, 1, 3), }, /* FVco 800.000000 */
29  { .frequency = 110000000, .index = PLLVAL(0x66, 1, 3), }, /* FVco 880.000000 */
30  { .frequency = 120000000, .index = PLLVAL(0x70, 1, 3), }, /* FVco 960.000000 */
31  { .frequency = 150000000, .index = PLLVAL(0x75, 3, 2), }, /* FVco 600.000000 */
32  { .frequency = 160000000, .index = PLLVAL(0x98, 4, 2), }, /* FVco 640.000000 */
33  { .frequency = 170000000, .index = PLLVAL(0x4d, 1, 2), }, /* FVco 680.000000 */
34  { .frequency = 180000000, .index = PLLVAL(0x70, 2, 2), }, /* FVco 720.000000 */
35  { .frequency = 190000000, .index = PLLVAL(0x57, 1, 2), }, /* FVco 760.000000 */
36  { .frequency = 200000000, .index = PLLVAL(0x5c, 1, 2), }, /* FVco 800.000000 */
37  { .frequency = 210000000, .index = PLLVAL(0x84, 2, 2), }, /* FVco 840.000000 */
38  { .frequency = 220000000, .index = PLLVAL(0x66, 1, 2), }, /* FVco 880.000000 */
39  { .frequency = 230000000, .index = PLLVAL(0x6b, 1, 2), }, /* FVco 920.000000 */
40  { .frequency = 240000000, .index = PLLVAL(0x70, 1, 2), }, /* FVco 960.000000 */
41  { .frequency = 300000000, .index = PLLVAL(0x75, 3, 1), }, /* FVco 600.000000 */
42  { .frequency = 310000000, .index = PLLVAL(0x93, 4, 1), }, /* FVco 620.000000 */
43  { .frequency = 320000000, .index = PLLVAL(0x98, 4, 1), }, /* FVco 640.000000 */
44  { .frequency = 330000000, .index = PLLVAL(0x66, 2, 1), }, /* FVco 660.000000 */
45  { .frequency = 340000000, .index = PLLVAL(0x4d, 1, 1), }, /* FVco 680.000000 */
46  { .frequency = 350000000, .index = PLLVAL(0xa7, 4, 1), }, /* FVco 700.000000 */
47  { .frequency = 360000000, .index = PLLVAL(0x70, 2, 1), }, /* FVco 720.000000 */
48  { .frequency = 370000000, .index = PLLVAL(0xb1, 4, 1), }, /* FVco 740.000000 */
49  { .frequency = 380000000, .index = PLLVAL(0x57, 1, 1), }, /* FVco 760.000000 */
50  { .frequency = 390000000, .index = PLLVAL(0x7a, 2, 1), }, /* FVco 780.000000 */
51  { .frequency = 400000000, .index = PLLVAL(0x5c, 1, 1), }, /* FVco 800.000000 */
52 };
53 
54 static int s3c2440_plls12_add(struct device *dev, struct subsys_interface *sif)
55 {
56  struct clk *xtal_clk;
57  unsigned long xtal;
58 
59  xtal_clk = clk_get(NULL, "xtal");
60  if (IS_ERR(xtal_clk))
61  return PTR_ERR(xtal_clk);
62 
63  xtal = clk_get_rate(xtal_clk);
64  clk_put(xtal_clk);
65 
66  if (xtal == 12000000) {
67  printk(KERN_INFO "Using PLL table for 12MHz crystal\n");
68  return s3c_plltab_register(s3c2440_plls_12,
69  ARRAY_SIZE(s3c2440_plls_12));
70  }
71 
72  return 0;
73 }
74 
75 static struct subsys_interface s3c2440_plls12_interface = {
76  .name = "s3c2440_plls12",
77  .subsys = &s3c2440_subsys,
78  .add_dev = s3c2440_plls12_add,
79 };
80 
81 static int __init s3c2440_pll_12mhz(void)
82 {
83  return subsys_interface_register(&s3c2440_plls12_interface);
84 
85 }
86 
87 arch_initcall(s3c2440_pll_12mhz);
88 
89 static struct subsys_interface s3c2442_plls12_interface = {
90  .name = "s3c2442_plls12",
91  .subsys = &s3c2442_subsys,
92  .add_dev = s3c2440_plls12_add,
93 };
94 
95 static int __init s3c2442_pll_12mhz(void)
96 {
97  return subsys_interface_register(&s3c2442_plls12_interface);
98 
99 }
100 
101 arch_initcall(s3c2442_pll_12mhz);