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#define | D_INT (1<<0) |
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#define | D_GEN (1<<1) |
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#define | D_CMD (1<<2) |
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#define | D_MM (1<<3) |
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#define | D_USR (1<<4) |
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#define | D_DESC (1<<5) |
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#define | dprintk(a, x...) do { } while (0) |
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#define | DBRI_CMD(cmd, intr, value) |
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#define | CS4215_CLB (1<<2) /* Control Latch Bit */ |
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#define | CS4215_OLB (1<<3) /* 1: line: 2.0V, speaker 4V */ |
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#define | CS4215_MLB (1<<4) /* 1: Microphone: 20dB gain disabled */ |
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#define | CS4215_RSRVD_1 (1<<5) |
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#define | CS4215_DFR_LINEAR16 0 |
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#define | CS4215_DFR_ULAW 1 |
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#define | CS4215_DFR_ALAW 2 |
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#define | CS4215_DFR_LINEAR8 3 |
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#define | CS4215_DFR_STEREO (1<<2) |
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#define | CS4215_HPF (1<<7) /* High Pass Filter, 1: Enabled */ |
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#define | CS4215_12_MASK 0xfcbf /* Mask off reserved bits in slot 1 & 2 */ |
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#define | CS4215_XEN (1<<0) /* 0: Enable serial output */ |
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#define | CS4215_XCLK (1<<1) /* 1: Master mode: Generate SCLK */ |
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#define | CS4215_BSEL_64 (0<<2) /* Bitrate: 64 bits per frame */ |
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#define | CS4215_BSEL_128 (1<<2) |
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#define | CS4215_BSEL_256 (2<<2) |
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#define | CS4215_MCK_MAST (0<<4) /* Master clock */ |
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#define | CS4215_MCK_XTL1 (1<<4) /* 24.576 MHz clock source */ |
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#define | CS4215_MCK_XTL2 (2<<4) /* 16.9344 MHz clock source */ |
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#define | CS4215_MCK_CLK1 (3<<4) /* Clockin, 256 x Fs */ |
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#define | CS4215_MCK_CLK2 (4<<4) /* Clockin, see DFR */ |
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#define | CS4215_DAD (1<<0) /* 0:Digital-Dig loop, 1:Dig-Analog-Dig loop */ |
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#define | CS4215_ENL (1<<1) /* Enable Loopback Testing */ |
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#define | CS4215_VERSION_MASK 0xf /* Known versions 0/C, 1/D, 2/E */ |
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#define | CS4215_LO(v) v /* Left Output Attenuation 0x3f: -94.5 dB */ |
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#define | CS4215_LE (1<<6) /* Line Out Enable */ |
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#define | CS4215_HE (1<<7) /* Headphone Enable */ |
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#define | CS4215_RO(v) v /* Right Output Attenuation 0x3f: -94.5 dB */ |
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#define | CS4215_SE (1<<6) /* Speaker Enable */ |
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#define | CS4215_ADI (1<<7) /* A/D Data Invalid: Busy in calibration */ |
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#define | CS4215_LG(v) v /* Left Gain Setting 0xf: 22.5 dB */ |
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#define | CS4215_IS (1<<4) /* Input Select: 1=Microphone, 0=Line */ |
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#define | CS4215_OVR (1<<5) /* 1: Over range condition occurred */ |
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#define | CS4215_PIO0 (1<<6) /* Parallel I/O 0 */ |
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#define | CS4215_PIO1 (1<<7) |
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#define | CS4215_RG(v) v /* Right Gain Setting 0xf: 22.5 dB */ |
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#define | CS4215_MA(v) (v<<4) /* Monitor Path Attenuation 0xf: mute */ |
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#define | REG0 0x00 /* Status and Control */ |
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#define | REG1 0x04 /* Mode and Interrupt */ |
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#define | REG2 0x08 /* Parallel IO */ |
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#define | REG3 0x0c /* Test */ |
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#define | REG8 0x20 /* Command Queue Pointer */ |
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#define | REG9 0x24 /* Interrupt Queue Pointer */ |
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#define | DBRI_NO_CMDS 64 |
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#define | DBRI_INT_BLK 64 |
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#define | DBRI_NO_DESCS 64 |
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#define | DBRI_NO_PIPES 32 |
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#define | DBRI_MAX_PIPE (DBRI_NO_PIPES - 1) |
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#define | DBRI_REC 0 |
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#define | DBRI_PLAY 1 |
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#define | DBRI_NO_STREAMS 2 |
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#define | dbri_dma_off(member, elem) |
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#define | DBRI_MAX_VOLUME 63 /* Output volume */ |
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#define | DBRI_MAX_GAIN 15 /* Input gain */ |
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#define | D_P (1<<15) /* Program command & queue pointer valid */ |
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#define | D_G (1<<14) /* Allow 4-Word SBus Burst */ |
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#define | D_S (1<<13) /* Allow 16-Word SBus Burst */ |
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#define | D_E (1<<12) /* Allow 8-Word SBus Burst */ |
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#define | D_X (1<<7) /* Sanity Timer Disable */ |
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#define | D_T (1<<6) /* Permit activation of the TE interface */ |
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#define | D_N (1<<5) /* Permit activation of the NT interface */ |
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#define | D_C (1<<4) /* Permit activation of the CHI interface */ |
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#define | D_F (1<<3) /* Force Sanity Timer Time-Out */ |
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#define | D_D (1<<2) /* Disable Master Mode */ |
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#define | D_H (1<<1) /* Halt for Analysis */ |
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#define | D_R (1<<0) /* Soft Reset */ |
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#define | D_LITTLE_END (1<<8) /* Byte Order */ |
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#define | D_BIG_END (0<<8) /* Byte Order */ |
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#define | D_MRR (1<<4) /* Multiple Error Ack on SBus (read only) */ |
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#define | D_MLE (1<<3) /* Multiple Late Error on SBus (read only) */ |
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#define | D_LBG (1<<2) /* Lost Bus Grant on SBus (read only) */ |
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#define | D_MBE (1<<1) /* Burst Error on SBus (read only) */ |
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#define | D_IR (1<<0) /* Interrupt Indicator (read only) */ |
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#define | D_ENPIO3 (1<<7) /* Enable Pin 3 */ |
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#define | D_ENPIO2 (1<<6) /* Enable Pin 2 */ |
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#define | D_ENPIO1 (1<<5) /* Enable Pin 1 */ |
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#define | D_ENPIO0 (1<<4) /* Enable Pin 0 */ |
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#define | D_ENPIO (0xf0) /* Enable all the pins */ |
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#define | D_PIO3 (1<<3) /* Pin 3: 1: Data mode, 0: Ctrl mode */ |
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#define | D_PIO2 (1<<2) /* Pin 2: 1: Onboard PDN */ |
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#define | D_PIO1 (1<<1) /* Pin 1: 0: Reset */ |
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#define | D_PIO0 (1<<0) /* Pin 0: 1: Speakerbox PDN */ |
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#define | D_WAIT 0x0 /* Stop execution */ |
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#define | D_PAUSE 0x1 /* Flush long pipes */ |
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#define | D_JUMP 0x2 /* New command queue */ |
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#define | D_IIQ 0x3 /* Initialize Interrupt Queue */ |
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#define | D_REX 0x4 /* Report command execution via interrupt */ |
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#define | D_SDP 0x5 /* Setup Data Pipe */ |
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#define | D_CDP 0x6 /* Continue Data Pipe (reread NULL Pointer) */ |
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#define | D_DTS 0x7 /* Define Time Slot */ |
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#define | D_SSP 0x8 /* Set short Data Pipe */ |
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#define | D_CHI 0x9 /* Set CHI Global Mode */ |
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#define | D_NT 0xa /* NT Command */ |
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#define | D_TE 0xb /* TE Command */ |
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#define | D_CDEC 0xc /* Codec setup */ |
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#define | D_TEST 0xd /* No comment */ |
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#define | D_CDM 0xe /* CHI Data mode command */ |
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#define | D_PIPE(v) ((v)<<0) /* Pipe No.: 0-15 long, 16-21 short */ |
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#define | D_SDP_2SAME (1<<18) /* Report 2nd time in a row value received */ |
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#define | D_SDP_CHANGE (2<<18) /* Report any changes */ |
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#define | D_SDP_EVERY (3<<18) /* Report any changes */ |
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#define | D_SDP_EOL (1<<17) /* EOL interrupt enable */ |
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#define | D_SDP_IDLE (1<<16) /* HDLC idle interrupt enable */ |
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#define | D_SDP_MEM (0<<13) /* To/from memory */ |
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#define | D_SDP_HDLC (2<<13) |
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#define | D_SDP_HDLC_D (3<<13) /* D Channel (prio control) */ |
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#define | D_SDP_SER (4<<13) /* Serial to serial */ |
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#define | D_SDP_FIXED (6<<13) /* Short only */ |
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#define | D_SDP_MODE(v) ((v)&(7<<13)) |
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#define | D_SDP_TO_SER (1<<12) /* Direction */ |
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#define | D_SDP_FROM_SER (0<<12) /* Direction */ |
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#define | D_SDP_MSB (1<<11) /* Bit order within Byte */ |
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#define | D_SDP_LSB (0<<11) /* Bit order within Byte */ |
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#define | D_SDP_P (1<<10) /* Pointer Valid */ |
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#define | D_SDP_A (1<<8) /* Abort */ |
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#define | D_SDP_C (1<<7) /* Clear */ |
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#define | D_DTS_VI (1<<17) /* Valid Input Time-Slot Descriptor */ |
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#define | D_DTS_VO (1<<16) /* Valid Output Time-Slot Descriptor */ |
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#define | D_DTS_INS (1<<15) /* Insert Time Slot */ |
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#define | D_DTS_DEL (0<<15) /* Delete Time Slot */ |
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#define | D_DTS_PRVIN(v) ((v)<<10) /* Previous In Pipe */ |
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#define | D_DTS_PRVOUT(v) ((v)<<5) /* Previous Out Pipe */ |
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#define | D_TS_LEN(v) ((v)<<24) /* Number of bits in this time slot */ |
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#define | D_TS_CYCLE(v) ((v)<<14) /* Bit Count at start of TS */ |
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#define | D_TS_DI (1<<13) /* Data Invert */ |
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#define | D_TS_1CHANNEL (0<<10) /* Single Channel / Normal mode */ |
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#define | D_TS_MONITOR (2<<10) /* Monitor pipe */ |
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#define | D_TS_NONCONTIG (3<<10) /* Non contiguous mode */ |
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#define | D_TS_ANCHOR (7<<10) /* Starting short pipes */ |
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#define | D_TS_MON(v) ((v)<<5) /* Monitor Pipe */ |
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#define | D_TS_NEXT(v) ((v)<<0) /* Pipe no.: 0-15 long, 16-21 short */ |
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#define | D_CHI_CHICM(v) ((v)<<16) /* Clock mode */ |
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#define | D_CHI_IR (1<<15) /* Immediate Interrupt Report */ |
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#define | D_CHI_EN (1<<14) /* CHIL Interrupt enabled */ |
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#define | D_CHI_OD (1<<13) /* Open Drain Enable */ |
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#define | D_CHI_FE (1<<12) /* Sample CHIFS on Rising Frame Edge */ |
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#define | D_CHI_FD (1<<11) /* Frame Drive */ |
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#define | D_CHI_BPF(v) ((v)<<0) /* Bits per Frame */ |
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#define | D_NT_FBIT (1<<17) /* Frame Bit */ |
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#define | D_NT_NBF (1<<16) /* Number of bad frames to loose framing */ |
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#define | D_NT_IRM_IMM (1<<15) /* Interrupt Report & Mask: Immediate */ |
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#define | D_NT_IRM_EN (1<<14) /* Interrupt Report & Mask: Enable */ |
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#define | D_NT_ISNT (1<<13) /* Configure interface as NT */ |
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#define | D_NT_FT (1<<12) /* Fixed Timing */ |
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#define | D_NT_EZ (1<<11) /* Echo Channel is Zeros */ |
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#define | D_NT_IFA (1<<10) /* Inhibit Final Activation */ |
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#define | D_NT_ACT (1<<9) /* Activate Interface */ |
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#define | D_NT_MFE (1<<8) /* Multiframe Enable */ |
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#define | D_NT_RLB(v) ((v)<<5) /* Remote Loopback */ |
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#define | D_NT_LLB(v) ((v)<<2) /* Local Loopback */ |
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#define | D_NT_FACT (1<<1) /* Force Activation */ |
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#define | D_NT_ABV (1<<0) /* Activate Bipolar Violation */ |
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#define | D_CDEC_CK(v) ((v)<<24) /* Clock Select */ |
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#define | D_CDEC_FED(v) ((v)<<12) /* FSCOD Falling Edge Delay */ |
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#define | D_CDEC_RED(v) ((v)<<0) /* FSCOD Rising Edge Delay */ |
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#define | D_TEST_RAM(v) ((v)<<16) /* RAM Pointer */ |
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#define | D_TEST_SIZE(v) ((v)<<11) /* */ |
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#define | D_TEST_ROMONOFF 0x5 /* Toggle ROM opcode monitor on/off */ |
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#define | D_TEST_PROC 0x6 /* Microprocessor test */ |
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#define | D_TEST_SER 0x7 /* Serial-Controller test */ |
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#define | D_TEST_RAMREAD 0x8 /* Copy from Ram to system memory */ |
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#define | D_TEST_RAMWRITE 0x9 /* Copy into Ram from system memory */ |
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#define | D_TEST_RAMBIST 0xa /* RAM Built-In Self Test */ |
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#define | D_TEST_MCBIST 0xb /* Microcontroller Built-In Self Test */ |
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#define | D_TEST_DUMP 0xe /* ROM Dump */ |
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#define | D_CDM_THI (1 << 8) /* Transmit Data on CHIDR Pin */ |
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#define | D_CDM_RHI (1 << 7) /* Receive Data on CHIDX Pin */ |
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#define | D_CDM_RCE (1 << 6) /* Receive on Rising Edge of CHICK */ |
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#define | D_CDM_XCE (1 << 2) /* Transmit Data on Rising Edge of CHICK */ |
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#define | D_CDM_XEN (1 << 1) /* Transmit Highway Enable */ |
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#define | D_CDM_REN (1 << 0) /* Receive Highway Enable */ |
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#define | D_INTR_BRDY 1 /* Buffer Ready for processing */ |
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#define | D_INTR_MINT 2 /* Marked Interrupt in RD/TD */ |
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#define | D_INTR_IBEG 3 /* Flag to idle transition detected (HDLC) */ |
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#define | D_INTR_IEND 4 /* Idle to flag transition detected (HDLC) */ |
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#define | D_INTR_EOL 5 /* End of List */ |
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#define | D_INTR_CMDI 6 /* Command has bean read */ |
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#define | D_INTR_XCMP 8 /* Transmission of frame complete */ |
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#define | D_INTR_SBRI 9 /* BRI status change info */ |
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#define | D_INTR_FXDT 10 /* Fixed data change */ |
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#define | D_INTR_CHIL 11 /* CHI lost frame sync (channel 36 only) */ |
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#define | D_INTR_COLL 11 /* Unrecoverable D-Channel collision */ |
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#define | D_INTR_DBYT 12 /* Dropped by frame slip */ |
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#define | D_INTR_RBYT 13 /* Repeated by frame slip */ |
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#define | D_INTR_LINT 14 /* Lost Interrupt */ |
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#define | D_INTR_UNDR 15 /* DMA underrun */ |
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#define | D_INTR_TE 32 |
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#define | D_INTR_NT 34 |
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#define | D_INTR_CHI 36 |
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#define | D_INTR_CMD 38 |
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#define | D_INTR_GETCHAN(v) (((v) >> 24) & 0x3f) |
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#define | D_INTR_GETCODE(v) (((v) >> 20) & 0xf) |
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#define | D_INTR_GETCMD(v) (((v) >> 16) & 0xf) |
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#define | D_INTR_GETVAL(v) ((v) & 0xffff) |
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#define | D_INTR_GETRVAL(v) ((v) & 0xfffff) |
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#define | D_P_0 0 /* TE receive anchor */ |
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#define | D_P_1 1 /* TE transmit anchor */ |
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#define | D_P_2 2 /* NT transmit anchor */ |
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#define | D_P_3 3 /* NT receive anchor */ |
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#define | D_P_4 4 /* CHI send data */ |
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#define | D_P_5 5 /* CHI receive data */ |
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#define | D_P_6 6 /* */ |
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#define | D_P_7 7 /* */ |
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#define | D_P_8 8 /* */ |
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#define | D_P_9 9 /* */ |
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#define | D_P_10 10 /* */ |
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#define | D_P_11 11 /* */ |
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#define | D_P_12 12 /* */ |
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#define | D_P_13 13 /* */ |
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#define | D_P_14 14 /* */ |
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#define | D_P_15 15 /* */ |
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#define | D_P_16 16 /* CHI anchor pipe */ |
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#define | D_P_17 17 /* CHI send */ |
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#define | D_P_18 18 /* CHI receive */ |
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#define | D_P_19 19 /* CHI receive */ |
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#define | D_P_20 20 /* CHI receive */ |
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#define | D_P_21 21 /* */ |
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#define | D_P_22 22 /* */ |
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#define | D_P_23 23 /* */ |
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#define | D_P_24 24 /* */ |
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#define | D_P_25 25 /* */ |
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#define | D_P_26 26 /* */ |
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#define | D_P_27 27 /* */ |
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#define | D_P_28 28 /* */ |
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#define | D_P_29 29 /* */ |
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#define | D_P_30 30 /* */ |
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#define | D_P_31 31 /* */ |
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#define | DBRI_TD_F (1 << 31) /* End of Frame */ |
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#define | DBRI_TD_D (1 << 30) /* Do not append CRC */ |
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#define | DBRI_TD_CNT(v) ((v) << 16) /* Number of valid bytes in the buffer */ |
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#define | DBRI_TD_B (1 << 15) /* Final interrupt */ |
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#define | DBRI_TD_M (1 << 14) /* Marker interrupt */ |
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#define | DBRI_TD_I (1 << 13) /* Transmit Idle Characters */ |
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#define | DBRI_TD_FCNT(v) (v) /* Flag Count */ |
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#define | DBRI_TD_UNR (1 << 3) /* Underrun: transmitter is out of data */ |
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#define | DBRI_TD_ABT (1 << 2) /* Abort: frame aborted */ |
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#define | DBRI_TD_TBC (1 << 0) /* Transmit buffer Complete */ |
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#define | DBRI_TD_STATUS(v) ((v) & 0xff) /* Transmit status */ |
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#define | DBRI_TD_MAXCNT ((1 << 13) - 4) |
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#define | DBRI_RD_F (1 << 31) /* End of Frame */ |
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#define | DBRI_RD_C (1 << 30) /* Completed buffer */ |
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#define | DBRI_RD_B (1 << 15) /* Final interrupt */ |
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#define | DBRI_RD_M (1 << 14) /* Marker interrupt */ |
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#define | DBRI_RD_BCNT(v) (v) /* Buffer size */ |
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#define | DBRI_RD_CRC (1 << 7) /* 0: CRC is correct */ |
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#define | DBRI_RD_BBC (1 << 6) /* 1: Bad Byte received */ |
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#define | DBRI_RD_ABT (1 << 5) /* Abort: frame aborted */ |
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#define | DBRI_RD_OVRN (1 << 3) /* Overrun: data lost */ |
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#define | DBRI_RD_STATUS(v) ((v) & 0xff) /* Receive status */ |
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#define | DBRI_RD_CNT(v) (((v) >> 16) & 0x1fff) /* Valid bytes in the buffer */ |
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#define | DBRI_STREAMNO(substream) |
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#define | DBRI_STREAM(dbri, substream) &dbri->stream_info[DBRI_STREAMNO(substream)] |
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#define | MAXLOOPS 20 |
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#define | CS4215_SINGLE(xname, entry, shift, mask, invert) |
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