#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/dma-mapping.h>
#include <linux/gfp.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/info.h>
#include <sound/control.h>
#include <sound/initval.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/atomic.h>
#include <linux/module.h>

Data Structures
struct	cs4215

struct	dbri_mem

struct	dbri_dma

struct	dbri_pipe

struct	dbri_streaminfo

struct	snd_dbri

Macros
#define	D_INT (1<<0)

#define	D_GEN (1<<1)

#define	D_CMD (1<<2)

#define	D_MM (1<<3)

#define	D_USR (1<<4)

#define	D_DESC (1<<5)

#define	dprintk(a, x...) do { } while (0)

#define	DBRI_CMD(cmd, intr, value)

#define	CS4215_CLB (1<<2) /* Control Latch Bit */

#define	CS4215_OLB (1<<3) /* 1: line: 2.0V, speaker 4V */

#define	CS4215_MLB (1<<4) /* 1: Microphone: 20dB gain disabled */

#define	CS4215_RSRVD_1 (1<<5)

#define	CS4215_DFR_LINEAR16 0

#define	CS4215_DFR_ULAW 1

#define	CS4215_DFR_ALAW 2

#define	CS4215_DFR_LINEAR8 3

#define	CS4215_DFR_STEREO (1<<2)

#define	CS4215_HPF (1<<7) /* High Pass Filter, 1: Enabled */

#define	CS4215_12_MASK 0xfcbf /* Mask off reserved bits in slot 1 & 2 */

#define	CS4215_XEN (1<<0) /* 0: Enable serial output */

#define	CS4215_XCLK (1<<1) /* 1: Master mode: Generate SCLK */

#define	CS4215_BSEL_64 (0<<2) /* Bitrate: 64 bits per frame */

#define	CS4215_BSEL_128 (1<<2)

#define	CS4215_BSEL_256 (2<<2)

#define	CS4215_MCK_MAST (0<<4) /* Master clock */

#define	CS4215_MCK_XTL1 (1<<4) /* 24.576 MHz clock source */

#define	CS4215_MCK_XTL2 (2<<4) /* 16.9344 MHz clock source */

#define	CS4215_MCK_CLK1 (3<<4) /* Clockin, 256 x Fs */

#define	CS4215_MCK_CLK2 (4<<4) /* Clockin, see DFR */

#define	CS4215_DAD (1<<0) /* 0:Digital-Dig loop, 1:Dig-Analog-Dig loop */

#define	CS4215_ENL (1<<1) /* Enable Loopback Testing */

#define	CS4215_VERSION_MASK 0xf /* Known versions 0/C, 1/D, 2/E */

#define	CS4215_LO(v) v /* Left Output Attenuation 0x3f: -94.5 dB */

#define	CS4215_LE (1<<6) /* Line Out Enable */

#define	CS4215_HE (1<<7) /* Headphone Enable */

#define	CS4215_RO(v) v /* Right Output Attenuation 0x3f: -94.5 dB */

#define	CS4215_SE (1<<6) /* Speaker Enable */

#define	CS4215_ADI (1<<7) /* A/D Data Invalid: Busy in calibration */

#define	CS4215_LG(v) v /* Left Gain Setting 0xf: 22.5 dB */

#define	CS4215_IS (1<<4) /* Input Select: 1=Microphone, 0=Line */

#define	CS4215_OVR (1<<5) /* 1: Over range condition occurred */

#define	CS4215_PIO0 (1<<6) /* Parallel I/O 0 */

#define	CS4215_PIO1 (1<<7)

#define	CS4215_RG(v) v /* Right Gain Setting 0xf: 22.5 dB */

#define	CS4215_MA(v) (v<<4) /* Monitor Path Attenuation 0xf: mute */

#define	REG0 0x00 /* Status and Control */

#define	REG1 0x04 /* Mode and Interrupt */

#define	REG2 0x08 /* Parallel IO */

#define	REG3 0x0c /* Test */

#define	REG8 0x20 /* Command Queue Pointer */

#define	REG9 0x24 /* Interrupt Queue Pointer */

#define	DBRI_NO_CMDS 64

#define	DBRI_INT_BLK 64

#define	DBRI_NO_DESCS 64

#define	DBRI_NO_PIPES 32

#define	DBRI_MAX_PIPE (DBRI_NO_PIPES - 1)

#define	DBRI_REC 0

#define	DBRI_PLAY 1

#define	DBRI_NO_STREAMS 2

#define	dbri_dma_off(member, elem)

#define	DBRI_MAX_VOLUME 63 /* Output volume */

#define	DBRI_MAX_GAIN 15 /* Input gain */

#define	D_P (1<<15) /* Program command & queue pointer valid */

#define	D_G (1<<14) /* Allow 4-Word SBus Burst */

#define	D_S (1<<13) /* Allow 16-Word SBus Burst */

#define	D_E (1<<12) /* Allow 8-Word SBus Burst */

#define	D_X (1<<7) /* Sanity Timer Disable */

#define	D_T (1<<6) /* Permit activation of the TE interface */

#define	D_N (1<<5) /* Permit activation of the NT interface */

#define	D_C (1<<4) /* Permit activation of the CHI interface */

#define	D_F (1<<3) /* Force Sanity Timer Time-Out */

#define	D_D (1<<2) /* Disable Master Mode */

#define	D_H (1<<1) /* Halt for Analysis */

#define	D_R (1<<0) /* Soft Reset */

#define	D_LITTLE_END (1<<8) /* Byte Order */

#define	D_BIG_END (0<<8) /* Byte Order */

#define	D_MRR (1<<4) /* Multiple Error Ack on SBus (read only) */

#define	D_MLE (1<<3) /* Multiple Late Error on SBus (read only) */

#define	D_LBG (1<<2) /* Lost Bus Grant on SBus (read only) */

#define	D_MBE (1<<1) /* Burst Error on SBus (read only) */

#define	D_IR (1<<0) /* Interrupt Indicator (read only) */

#define	D_ENPIO3 (1<<7) /* Enable Pin 3 */

#define	D_ENPIO2 (1<<6) /* Enable Pin 2 */

#define	D_ENPIO1 (1<<5) /* Enable Pin 1 */

#define	D_ENPIO0 (1<<4) /* Enable Pin 0 */

#define	D_ENPIO (0xf0) /* Enable all the pins */

#define	D_PIO3 (1<<3) /* Pin 3: 1: Data mode, 0: Ctrl mode */

#define	D_PIO2 (1<<2) /* Pin 2: 1: Onboard PDN */

#define	D_PIO1 (1<<1) /* Pin 1: 0: Reset */

#define	D_PIO0 (1<<0) /* Pin 0: 1: Speakerbox PDN */

#define	D_WAIT 0x0 /* Stop execution */

#define	D_PAUSE 0x1 /* Flush long pipes */

#define	D_JUMP 0x2 /* New command queue */

#define	D_IIQ 0x3 /* Initialize Interrupt Queue */

#define	D_REX 0x4 /* Report command execution via interrupt */

#define	D_SDP 0x5 /* Setup Data Pipe */

#define	D_CDP 0x6 /* Continue Data Pipe (reread NULL Pointer) */

#define	D_DTS 0x7 /* Define Time Slot */

#define	D_SSP 0x8 /* Set short Data Pipe */

#define	D_CHI 0x9 /* Set CHI Global Mode */

#define	D_NT 0xa /* NT Command */

#define	D_TE 0xb /* TE Command */

#define	D_CDEC 0xc /* Codec setup */

#define	D_TEST 0xd /* No comment */

#define	D_CDM 0xe /* CHI Data mode command */

#define	D_PIPE(v) ((v)<<0) /* Pipe No.: 0-15 long, 16-21 short */

#define	D_SDP_2SAME (1<<18) /* Report 2nd time in a row value received */

#define	D_SDP_CHANGE (2<<18) /* Report any changes */

#define	D_SDP_EVERY (3<<18) /* Report any changes */

#define	D_SDP_EOL (1<<17) /* EOL interrupt enable */

#define	D_SDP_IDLE (1<<16) /* HDLC idle interrupt enable */

#define	D_SDP_MEM (0<<13) /* To/from memory */

#define	D_SDP_HDLC (2<<13)

#define	D_SDP_HDLC_D (3<<13) /* D Channel (prio control) */

#define	D_SDP_SER (4<<13) /* Serial to serial */

#define	D_SDP_FIXED (6<<13) /* Short only */

#define	D_SDP_MODE(v) ((v)&(7<<13))

#define	D_SDP_TO_SER (1<<12) /* Direction */

#define	D_SDP_FROM_SER (0<<12) /* Direction */

#define	D_SDP_MSB (1<<11) /* Bit order within Byte */

#define	D_SDP_LSB (0<<11) /* Bit order within Byte */

#define	D_SDP_P (1<<10) /* Pointer Valid */

#define	D_SDP_A (1<<8) /* Abort */

#define	D_SDP_C (1<<7) /* Clear */

#define	D_DTS_VI (1<<17) /* Valid Input Time-Slot Descriptor */

#define	D_DTS_VO (1<<16) /* Valid Output Time-Slot Descriptor */

#define	D_DTS_INS (1<<15) /* Insert Time Slot */

#define	D_DTS_DEL (0<<15) /* Delete Time Slot */

#define	D_DTS_PRVIN(v) ((v)<<10) /* Previous In Pipe */

#define	D_DTS_PRVOUT(v) ((v)<<5) /* Previous Out Pipe */

#define	D_TS_LEN(v) ((v)<<24) /* Number of bits in this time slot */

#define	D_TS_CYCLE(v) ((v)<<14) /* Bit Count at start of TS */

#define	D_TS_DI (1<<13) /* Data Invert */

#define	D_TS_1CHANNEL (0<<10) /* Single Channel / Normal mode */

#define	D_TS_MONITOR (2<<10) /* Monitor pipe */

#define	D_TS_NONCONTIG (3<<10) /* Non contiguous mode */

#define	D_TS_ANCHOR (7<<10) /* Starting short pipes */

#define	D_TS_MON(v) ((v)<<5) /* Monitor Pipe */

#define	D_TS_NEXT(v) ((v)<<0) /* Pipe no.: 0-15 long, 16-21 short */

#define	D_CHI_CHICM(v) ((v)<<16) /* Clock mode */

#define	D_CHI_IR (1<<15) /* Immediate Interrupt Report */

#define	D_CHI_EN (1<<14) /* CHIL Interrupt enabled */

#define	D_CHI_OD (1<<13) /* Open Drain Enable */

#define	D_CHI_FE (1<<12) /* Sample CHIFS on Rising Frame Edge */

#define	D_CHI_FD (1<<11) /* Frame Drive */

#define	D_CHI_BPF(v) ((v)<<0) /* Bits per Frame */

#define	D_NT_FBIT (1<<17) /* Frame Bit */

#define	D_NT_NBF (1<<16) /* Number of bad frames to loose framing */

#define	D_NT_IRM_IMM (1<<15) /* Interrupt Report & Mask: Immediate */

#define	D_NT_IRM_EN (1<<14) /* Interrupt Report & Mask: Enable */

#define	D_NT_ISNT (1<<13) /* Configure interface as NT */

#define	D_NT_FT (1<<12) /* Fixed Timing */

#define	D_NT_EZ (1<<11) /* Echo Channel is Zeros */

#define	D_NT_IFA (1<<10) /* Inhibit Final Activation */

#define	D_NT_ACT (1<<9) /* Activate Interface */

#define	D_NT_MFE (1<<8) /* Multiframe Enable */

#define	D_NT_RLB(v) ((v)<<5) /* Remote Loopback */

#define	D_NT_LLB(v) ((v)<<2) /* Local Loopback */

#define	D_NT_FACT (1<<1) /* Force Activation */

#define	D_NT_ABV (1<<0) /* Activate Bipolar Violation */

#define	D_CDEC_CK(v) ((v)<<24) /* Clock Select */

#define	D_CDEC_FED(v) ((v)<<12) /* FSCOD Falling Edge Delay */

#define	D_CDEC_RED(v) ((v)<<0) /* FSCOD Rising Edge Delay */

#define	D_TEST_RAM(v) ((v)<<16) /* RAM Pointer */

#define	D_TEST_SIZE(v) ((v)<<11) /* */

#define	D_TEST_ROMONOFF 0x5 /* Toggle ROM opcode monitor on/off */

#define	D_TEST_PROC 0x6 /* Microprocessor test */

#define	D_TEST_SER 0x7 /* Serial-Controller test */

#define	D_TEST_RAMREAD 0x8 /* Copy from Ram to system memory */

#define	D_TEST_RAMWRITE 0x9 /* Copy into Ram from system memory */

#define	D_TEST_RAMBIST 0xa /* RAM Built-In Self Test */

#define	D_TEST_MCBIST 0xb /* Microcontroller Built-In Self Test */

#define	D_TEST_DUMP 0xe /* ROM Dump */

#define	D_CDM_THI (1 << 8) /* Transmit Data on CHIDR Pin */

#define	D_CDM_RHI (1 << 7) /* Receive Data on CHIDX Pin */

#define	D_CDM_RCE (1 << 6) /* Receive on Rising Edge of CHICK */

#define	D_CDM_XCE (1 << 2) /* Transmit Data on Rising Edge of CHICK */

#define	D_CDM_XEN (1 << 1) /* Transmit Highway Enable */

#define	D_CDM_REN (1 << 0) /* Receive Highway Enable */

#define	D_INTR_BRDY 1 /* Buffer Ready for processing */

#define	D_INTR_MINT 2 /* Marked Interrupt in RD/TD */

#define	D_INTR_IBEG 3 /* Flag to idle transition detected (HDLC) */

#define	D_INTR_IEND 4 /* Idle to flag transition detected (HDLC) */

#define	D_INTR_EOL 5 /* End of List */

#define	D_INTR_CMDI 6 /* Command has bean read */

#define	D_INTR_XCMP 8 /* Transmission of frame complete */

#define	D_INTR_SBRI 9 /* BRI status change info */

#define	D_INTR_FXDT 10 /* Fixed data change */

#define	D_INTR_CHIL 11 /* CHI lost frame sync (channel 36 only) */

#define	D_INTR_COLL 11 /* Unrecoverable D-Channel collision */

#define	D_INTR_DBYT 12 /* Dropped by frame slip */

#define	D_INTR_RBYT 13 /* Repeated by frame slip */

#define	D_INTR_LINT 14 /* Lost Interrupt */

#define	D_INTR_UNDR 15 /* DMA underrun */

#define	D_INTR_TE 32

#define	D_INTR_NT 34

#define	D_INTR_CHI 36

#define	D_INTR_CMD 38

#define	D_INTR_GETCHAN(v) (((v) >> 24) & 0x3f)

#define	D_INTR_GETCODE(v) (((v) >> 20) & 0xf)

#define	D_INTR_GETCMD(v) (((v) >> 16) & 0xf)

#define	D_INTR_GETVAL(v) ((v) & 0xffff)

#define	D_INTR_GETRVAL(v) ((v) & 0xfffff)

#define	D_P_0 0 /* TE receive anchor */

#define	D_P_1 1 /* TE transmit anchor */

#define	D_P_2 2 /* NT transmit anchor */

#define	D_P_3 3 /* NT receive anchor */

#define	D_P_4 4 /* CHI send data */

#define	D_P_5 5 /* CHI receive data */

#define	D_P_6 6 /* */

#define	D_P_7 7 /* */

#define	D_P_8 8 /* */

#define	D_P_9 9 /* */

#define	D_P_10 10 /* */

#define	D_P_11 11 /* */

#define	D_P_12 12 /* */

#define	D_P_13 13 /* */

#define	D_P_14 14 /* */

#define	D_P_15 15 /* */

#define	D_P_16 16 /* CHI anchor pipe */

#define	D_P_17 17 /* CHI send */

#define	D_P_18 18 /* CHI receive */

#define	D_P_19 19 /* CHI receive */

#define	D_P_20 20 /* CHI receive */

#define	D_P_21 21 /* */

#define	D_P_22 22 /* */

#define	D_P_23 23 /* */

#define	D_P_24 24 /* */

#define	D_P_25 25 /* */

#define	D_P_26 26 /* */

#define	D_P_27 27 /* */

#define	D_P_28 28 /* */

#define	D_P_29 29 /* */

#define	D_P_30 30 /* */

#define	D_P_31 31 /* */

#define	DBRI_TD_F (1 << 31) /* End of Frame */

#define	DBRI_TD_D (1 << 30) /* Do not append CRC */

#define	DBRI_TD_CNT(v) ((v) << 16) /* Number of valid bytes in the buffer */

#define	DBRI_TD_B (1 << 15) /* Final interrupt */

#define	DBRI_TD_M (1 << 14) /* Marker interrupt */

#define	DBRI_TD_I (1 << 13) /* Transmit Idle Characters */

#define	DBRI_TD_FCNT(v) (v) /* Flag Count */

#define	DBRI_TD_UNR (1 << 3) /* Underrun: transmitter is out of data */

#define	DBRI_TD_ABT (1 << 2) /* Abort: frame aborted */

#define	DBRI_TD_TBC (1 << 0) /* Transmit buffer Complete */

#define	DBRI_TD_STATUS(v) ((v) & 0xff) /* Transmit status */

#define	DBRI_TD_MAXCNT ((1 << 13) - 4)

#define	DBRI_RD_F (1 << 31) /* End of Frame */

#define	DBRI_RD_C (1 << 30) /* Completed buffer */

#define	DBRI_RD_B (1 << 15) /* Final interrupt */

#define	DBRI_RD_M (1 << 14) /* Marker interrupt */

#define	DBRI_RD_BCNT(v) (v) /* Buffer size */

#define	DBRI_RD_CRC (1 << 7) /* 0: CRC is correct */

#define	DBRI_RD_BBC (1 << 6) /* 1: Bad Byte received */

#define	DBRI_RD_ABT (1 << 5) /* Abort: frame aborted */

#define	DBRI_RD_OVRN (1 << 3) /* Overrun: data lost */

#define	DBRI_RD_STATUS(v) ((v) & 0xff) /* Receive status */

#define	DBRI_RD_CNT(v) (((v) >> 16) & 0x1fff) /* Valid bytes in the buffer */

#define	DBRI_STREAMNO(substream)

#define	DBRI_STREAM(dbri, substream) &dbri->stream_info[DBRI_STREAMNO(substream)]

#define	MAXLOOPS 20

#define	CS4215_SINGLE(xname, entry, shift, mask, invert)

Enumerations
enum	in_or_out { PIPEinput, PIPEoutput }

enum	master_or_slave { CHImaster, CHIslave }

Functions
	MODULE_AUTHOR ("Rudolf Koenig, Brent Baccala and Martin Habets")

	MODULE_DESCRIPTION ("Sun DBRI")

	MODULE_LICENSE ("GPL")

	MODULE_SUPPORTED_DEVICE ("{{Sun,DBRI}}")

	module_param_array (index, int, NULL, 0444)

	MODULE_PARM_DESC (index,"Index value for Sun DBRI soundcard.")

	module_param_array (id, charp, NULL, 0444)

	MODULE_PARM_DESC (id,"ID string for Sun DBRI soundcard.")

	module_param_array (enable, bool, NULL, 0444)

	MODULE_PARM_DESC (enable,"Enable Sun DBRI soundcard.")

	module_param (dbri_debug, int, 0644)

	MODULE_PARM_DESC (dbri_debug,"Debug value for Sun DBRI soundcard.")

	MODULE_DEVICE_TABLE (of, dbri_match)

	module_platform_driver (dbri_sbus_driver)

Macro Definition Documentation

#define CS4215_12_MASK 0xfcbf /* Mask off reserved bits in slot 1 & 2 */

Definition at line 180 of file dbri.c.

#define CS4215_ADI (1<<7) /* A/D Data Invalid: Busy in calibration */

Definition at line 221 of file dbri.c.

#define CS4215_BSEL_128 (1<<2)

Definition at line 186 of file dbri.c.

#define CS4215_BSEL_256 (2<<2)

Definition at line 187 of file dbri.c.

#define CS4215_BSEL_64 (0<<2) /* Bitrate: 64 bits per frame */

Definition at line 185 of file dbri.c.

#define CS4215_CLB (1<<2) /* Control Latch Bit */

Definition at line 142 of file dbri.c.

#define CS4215_DAD (1<<0) /* 0:Digital-Dig loop, 1:Dig-Analog-Dig loop */

Definition at line 195 of file dbri.c.

#define CS4215_DFR_ALAW 2

Definition at line 151 of file dbri.c.

#define CS4215_DFR_LINEAR16 0

Definition at line 149 of file dbri.c.

#define CS4215_DFR_LINEAR8 3

Definition at line 152 of file dbri.c.

#define CS4215_DFR_STEREO (1<<2)

Definition at line 153 of file dbri.c.

#define CS4215_DFR_ULAW 1

Definition at line 150 of file dbri.c.

#define CS4215_ENL (1<<1) /* Enable Loopback Testing */

Definition at line 196 of file dbri.c.

#define CS4215_HE (1<<7) /* Headphone Enable */

Definition at line 216 of file dbri.c.

#define CS4215_HPF (1<<7) /* High Pass Filter, 1: Enabled */

Definition at line 178 of file dbri.c.

#define CS4215_IS (1<<4) /* Input Select: 1=Microphone, 0=Line */

Definition at line 225 of file dbri.c.

#define CS4215_LE (1<<6) /* Line Out Enable */

Definition at line 215 of file dbri.c.

#define CS4215_LG ( v ) v /* Left Gain Setting 0xf: 22.5 dB */

Definition at line 224 of file dbri.c.

#define CS4215_LO ( v ) v /* Left Output Attenuation 0x3f: -94.5 dB */

Definition at line 214 of file dbri.c.

#define CS4215_MA ( v ) (v<<4) /* Monitor Path Attenuation 0xf: mute */

Definition at line 232 of file dbri.c.

#define CS4215_MCK_CLK1 (3<<4) /* Clockin, 256 x Fs */

Definition at line 191 of file dbri.c.

#define CS4215_MCK_CLK2 (4<<4) /* Clockin, see DFR */

Definition at line 192 of file dbri.c.

#define CS4215_MCK_MAST (0<<4) /* Master clock */

Definition at line 188 of file dbri.c.

#define CS4215_MCK_XTL1 (1<<4) /* 24.576 MHz clock source */

Definition at line 189 of file dbri.c.

#define CS4215_MCK_XTL2 (2<<4) /* 16.9344 MHz clock source */

Definition at line 190 of file dbri.c.

#define CS4215_MLB (1<<4) /* 1: Microphone: 20dB gain disabled */

Definition at line 145 of file dbri.c.

#define CS4215_OLB (1<<3) /* 1: line: 2.0V, speaker 4V */

Definition at line 143 of file dbri.c.

#define CS4215_OVR (1<<5) /* 1: Over range condition occurred */

Definition at line 226 of file dbri.c.

#define CS4215_PIO0 (1<<6) /* Parallel I/O 0 */

Definition at line 227 of file dbri.c.

#define CS4215_PIO1 (1<<7)

Definition at line 228 of file dbri.c.

#define CS4215_RG ( v ) v /* Right Gain Setting 0xf: 22.5 dB */

Definition at line 231 of file dbri.c.

#define CS4215_RO ( v ) v /* Right Output Attenuation 0x3f: -94.5 dB */

Definition at line 219 of file dbri.c.

#define CS4215_RSRVD_1 (1<<5)

Definition at line 146 of file dbri.c.

#define CS4215_SE (1<<6) /* Speaker Enable */

Definition at line 220 of file dbri.c.

#define CS4215_SINGLE	(	xname,
		entry,
		shift,
		mask,
		invert
	)

Value:

{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),     \
  .info = snd_cs4215_info_single,               \
  .get = snd_cs4215_get_single, .put = snd_cs4215_put_single,   \
  .private_value = (entry) | ((shift) << 8) | ((mask) << 16) |  \
            ((invert) << 24) },

Definition at line 2405 of file dbri.c.

#define CS4215_VERSION_MASK 0xf /* Known versions 0/C, 1/D, 2/E */

Definition at line 204 of file dbri.c.

#define CS4215_XCLK (1<<1) /* 1: Master mode: Generate SCLK */

Definition at line 184 of file dbri.c.

#define CS4215_XEN (1<<0) /* 0: Enable serial output */

Definition at line 183 of file dbri.c.

#define D_BIG_END (0<<8) /* Byte Order */

Definition at line 343 of file dbri.c.

#define D_C (1<<4) /* Permit activation of the CHI interface */

Definition at line 335 of file dbri.c.

#define D_CDEC 0xc /* Codec setup */

Definition at line 374 of file dbri.c.

#define D_CDEC_CK ( v ) ((v)<<24) /* Clock Select */

Definition at line 450 of file dbri.c.

#define D_CDEC_FED ( v ) ((v)<<12) /* FSCOD Falling Edge Delay */

Definition at line 451 of file dbri.c.

#define D_CDEC_RED ( v ) ((v)<<0) /* FSCOD Rising Edge Delay */

Definition at line 452 of file dbri.c.

#define D_CDM 0xe /* CHI Data mode command */

Definition at line 376 of file dbri.c.

#define D_CDM_RCE (1 << 6) /* Receive on Rising Edge of CHICK */

Definition at line 469 of file dbri.c.

#define D_CDM_REN (1 << 0) /* Receive Highway Enable */

Definition at line 472 of file dbri.c.

#define D_CDM_RHI (1 << 7) /* Receive Data on CHIDX Pin */

Definition at line 468 of file dbri.c.

#define D_CDM_THI (1 << 8) /* Transmit Data on CHIDR Pin */

Definition at line 467 of file dbri.c.

#define D_CDM_XCE (1 << 2) /* Transmit Data on Rising Edge of CHICK */

Definition at line 470 of file dbri.c.

#define D_CDM_XEN (1 << 1) /* Transmit Highway Enable */

Definition at line 471 of file dbri.c.

#define D_CDP 0x6 /* Continue Data Pipe (reread NULL Pointer) */

Definition at line 368 of file dbri.c.

#define D_CHI 0x9 /* Set CHI Global Mode */

Definition at line 371 of file dbri.c.

#define D_CHI_BPF ( v ) ((v)<<0) /* Bits per Frame */

Definition at line 431 of file dbri.c.

#define D_CHI_CHICM ( v ) ((v)<<16) /* Clock mode */

Definition at line 425 of file dbri.c.

#define D_CHI_EN (1<<14) /* CHIL Interrupt enabled */

Definition at line 427 of file dbri.c.

#define D_CHI_FD (1<<11) /* Frame Drive */

Definition at line 430 of file dbri.c.

#define D_CHI_FE (1<<12) /* Sample CHIFS on Rising Frame Edge */

Definition at line 429 of file dbri.c.

#define D_CHI_IR (1<<15) /* Immediate Interrupt Report */

Definition at line 426 of file dbri.c.

#define D_CHI_OD (1<<13) /* Open Drain Enable */

Definition at line 428 of file dbri.c.

#define D_CMD (1<<2)

Definition at line 96 of file dbri.c.

#define D_D (1<<2) /* Disable Master Mode */

Definition at line 337 of file dbri.c.

#define D_DESC (1<<5)

Definition at line 99 of file dbri.c.

#define D_DTS 0x7 /* Define Time Slot */

Definition at line 369 of file dbri.c.

#define D_DTS_DEL (0<<15) /* Delete Time Slot */

Definition at line 409 of file dbri.c.

#define D_DTS_INS (1<<15) /* Insert Time Slot */

Definition at line 408 of file dbri.c.

#define D_DTS_PRVIN ( v ) ((v)<<10) /* Previous In Pipe */

Definition at line 410 of file dbri.c.

#define D_DTS_PRVOUT ( v ) ((v)<<5) /* Previous Out Pipe */

Definition at line 411 of file dbri.c.

#define D_DTS_VI (1<<17) /* Valid Input Time-Slot Descriptor */

Definition at line 406 of file dbri.c.

#define D_DTS_VO (1<<16) /* Valid Output Time-Slot Descriptor */

Definition at line 407 of file dbri.c.

#define D_E (1<<12) /* Allow 8-Word SBus Burst */

Definition at line 331 of file dbri.c.

#define D_ENPIO (0xf0) /* Enable all the pins */

Definition at line 355 of file dbri.c.

#define D_ENPIO0 (1<<4) /* Enable Pin 0 */

Definition at line 354 of file dbri.c.

#define D_ENPIO1 (1<<5) /* Enable Pin 1 */

Definition at line 353 of file dbri.c.

#define D_ENPIO2 (1<<6) /* Enable Pin 2 */

Definition at line 352 of file dbri.c.

#define D_ENPIO3 (1<<7) /* Enable Pin 3 */

Definition at line 351 of file dbri.c.

#define D_F (1<<3) /* Force Sanity Timer Time-Out */

Definition at line 336 of file dbri.c.

#define D_G (1<<14) /* Allow 4-Word SBus Burst */

Definition at line 329 of file dbri.c.

#define D_GEN (1<<1)

Definition at line 95 of file dbri.c.

#define D_H (1<<1) /* Halt for Analysis */

Definition at line 338 of file dbri.c.

#define D_IIQ 0x3 /* Initialize Interrupt Queue */

Definition at line 365 of file dbri.c.

#define D_INT (1<<0)

Definition at line 94 of file dbri.c.

#define D_INTR_BRDY 1 /* Buffer Ready for processing */

Definition at line 475 of file dbri.c.

#define D_INTR_CHI 36

Definition at line 493 of file dbri.c.

#define D_INTR_CHIL 11 /* CHI lost frame sync (channel 36 only) */

Definition at line 484 of file dbri.c.

#define D_INTR_CMD 38

Definition at line 494 of file dbri.c.

#define D_INTR_CMDI 6 /* Command has bean read */

Definition at line 480 of file dbri.c.

#define D_INTR_COLL 11 /* Unrecoverable D-Channel collision */

Definition at line 485 of file dbri.c.

#define D_INTR_DBYT 12 /* Dropped by frame slip */

Definition at line 486 of file dbri.c.

#define D_INTR_EOL 5 /* End of List */

Definition at line 479 of file dbri.c.

#define D_INTR_FXDT 10 /* Fixed data change */

Definition at line 483 of file dbri.c.

#define D_INTR_GETCHAN ( v ) (((v) >> 24) & 0x3f)

Definition at line 496 of file dbri.c.

#define D_INTR_GETCMD ( v ) (((v) >> 16) & 0xf)

Definition at line 498 of file dbri.c.

#define D_INTR_GETCODE ( v ) (((v) >> 20) & 0xf)

Definition at line 497 of file dbri.c.

#define D_INTR_GETRVAL ( v ) ((v) & 0xfffff)

Definition at line 500 of file dbri.c.

#define D_INTR_GETVAL ( v ) ((v) & 0xffff)

Definition at line 499 of file dbri.c.

#define D_INTR_IBEG 3 /* Flag to idle transition detected (HDLC) */

Definition at line 477 of file dbri.c.

#define D_INTR_IEND 4 /* Idle to flag transition detected (HDLC) */

Definition at line 478 of file dbri.c.

#define D_INTR_LINT 14 /* Lost Interrupt */

Definition at line 488 of file dbri.c.

#define D_INTR_MINT 2 /* Marked Interrupt in RD/TD */

Definition at line 476 of file dbri.c.

#define D_INTR_NT 34

Definition at line 492 of file dbri.c.

#define D_INTR_RBYT 13 /* Repeated by frame slip */

Definition at line 487 of file dbri.c.

#define D_INTR_SBRI 9 /* BRI status change info */

Definition at line 482 of file dbri.c.

#define D_INTR_TE 32

Definition at line 491 of file dbri.c.

#define D_INTR_UNDR 15 /* DMA underrun */

Definition at line 489 of file dbri.c.

#define D_INTR_XCMP 8 /* Transmission of frame complete */

Definition at line 481 of file dbri.c.

#define D_IR (1<<0) /* Interrupt Indicator (read only) */

Definition at line 348 of file dbri.c.

#define D_JUMP 0x2 /* New command queue */

Definition at line 364 of file dbri.c.

#define D_LBG (1<<2) /* Lost Bus Grant on SBus (read only) */

Definition at line 346 of file dbri.c.

#define D_LITTLE_END (1<<8) /* Byte Order */

Definition at line 342 of file dbri.c.

#define D_MBE (1<<1) /* Burst Error on SBus (read only) */

Definition at line 347 of file dbri.c.

#define D_MLE (1<<3) /* Multiple Late Error on SBus (read only) */

Definition at line 345 of file dbri.c.

#define D_MM (1<<3)

Definition at line 97 of file dbri.c.

#define D_MRR (1<<4) /* Multiple Error Ack on SBus (read only) */

Definition at line 344 of file dbri.c.

#define D_N (1<<5) /* Permit activation of the NT interface */

Definition at line 334 of file dbri.c.

#define D_NT 0xa /* NT Command */

Definition at line 372 of file dbri.c.

#define D_NT_ABV (1<<0) /* Activate Bipolar Violation */

Definition at line 447 of file dbri.c.

#define D_NT_ACT (1<<9) /* Activate Interface */

Definition at line 442 of file dbri.c.

#define D_NT_EZ (1<<11) /* Echo Channel is Zeros */

Definition at line 440 of file dbri.c.

#define D_NT_FACT (1<<1) /* Force Activation */

Definition at line 446 of file dbri.c.

#define D_NT_FBIT (1<<17) /* Frame Bit */

Definition at line 434 of file dbri.c.

#define D_NT_FT (1<<12) /* Fixed Timing */

Definition at line 439 of file dbri.c.

#define D_NT_IFA (1<<10) /* Inhibit Final Activation */

Definition at line 441 of file dbri.c.

#define D_NT_IRM_EN (1<<14) /* Interrupt Report & Mask: Enable */

Definition at line 437 of file dbri.c.

#define D_NT_IRM_IMM (1<<15) /* Interrupt Report & Mask: Immediate */

Definition at line 436 of file dbri.c.

#define D_NT_ISNT (1<<13) /* Configure interface as NT */

Definition at line 438 of file dbri.c.

#define D_NT_LLB ( v ) ((v)<<2) /* Local Loopback */

Definition at line 445 of file dbri.c.

#define D_NT_MFE (1<<8) /* Multiframe Enable */

Definition at line 443 of file dbri.c.

#define D_NT_NBF (1<<16) /* Number of bad frames to loose framing */

Definition at line 435 of file dbri.c.

#define D_NT_RLB ( v ) ((v)<<5) /* Remote Loopback */

Definition at line 444 of file dbri.c.

#define D_P (1<<15) /* Program command & queue pointer valid */

Definition at line 328 of file dbri.c.

#define D_P_0 0 /* TE receive anchor */

Definition at line 502 of file dbri.c.

#define D_P_1 1 /* TE transmit anchor */

Definition at line 503 of file dbri.c.

#define D_P_10 10 /* */

Definition at line 512 of file dbri.c.

#define D_P_11 11 /* */

Definition at line 513 of file dbri.c.

#define D_P_12 12 /* */

Definition at line 514 of file dbri.c.

#define D_P_13 13 /* */

Definition at line 515 of file dbri.c.

#define D_P_14 14 /* */

Definition at line 516 of file dbri.c.

#define D_P_15 15 /* */

Definition at line 517 of file dbri.c.

#define D_P_16 16 /* CHI anchor pipe */

Definition at line 518 of file dbri.c.

#define D_P_17 17 /* CHI send */

Definition at line 519 of file dbri.c.

#define D_P_18 18 /* CHI receive */

Definition at line 520 of file dbri.c.

#define D_P_19 19 /* CHI receive */

Definition at line 521 of file dbri.c.

#define D_P_2 2 /* NT transmit anchor */

Definition at line 504 of file dbri.c.

#define D_P_20 20 /* CHI receive */

Definition at line 522 of file dbri.c.

#define D_P_21 21 /* */

Definition at line 523 of file dbri.c.

#define D_P_22 22 /* */

Definition at line 524 of file dbri.c.

#define D_P_23 23 /* */

Definition at line 525 of file dbri.c.

#define D_P_24 24 /* */

Definition at line 526 of file dbri.c.

#define D_P_25 25 /* */

Definition at line 527 of file dbri.c.

#define D_P_26 26 /* */

Definition at line 528 of file dbri.c.

#define D_P_27 27 /* */

Definition at line 529 of file dbri.c.

#define D_P_28 28 /* */

Definition at line 530 of file dbri.c.

#define D_P_29 29 /* */

Definition at line 531 of file dbri.c.

#define D_P_3 3 /* NT receive anchor */

Definition at line 505 of file dbri.c.

#define D_P_30 30 /* */

Definition at line 532 of file dbri.c.

#define D_P_31 31 /* */

Definition at line 533 of file dbri.c.

#define D_P_4 4 /* CHI send data */

Definition at line 506 of file dbri.c.

#define D_P_5 5 /* CHI receive data */

Definition at line 507 of file dbri.c.

#define D_P_6 6 /* */

Definition at line 508 of file dbri.c.

#define D_P_7 7 /* */

Definition at line 509 of file dbri.c.

#define D_P_8 8 /* */

Definition at line 510 of file dbri.c.

#define D_P_9 9 /* */

Definition at line 511 of file dbri.c.

#define D_PAUSE 0x1 /* Flush long pipes */

Definition at line 363 of file dbri.c.

#define D_PIO0 (1<<0) /* Pin 0: 1: Speakerbox PDN */

Definition at line 359 of file dbri.c.

#define D_PIO1 (1<<1) /* Pin 1: 0: Reset */

Definition at line 358 of file dbri.c.

#define D_PIO2 (1<<2) /* Pin 2: 1: Onboard PDN */

Definition at line 357 of file dbri.c.

#define D_PIO3 (1<<3) /* Pin 3: 1: Data mode, 0: Ctrl mode */

Definition at line 356 of file dbri.c.

#define D_PIPE ( v ) ((v)<<0) /* Pipe No.: 0-15 long, 16-21 short */

Definition at line 379 of file dbri.c.

#define D_R (1<<0) /* Soft Reset */

Definition at line 339 of file dbri.c.

#define D_REX 0x4 /* Report command execution via interrupt */

Definition at line 366 of file dbri.c.

#define D_S (1<<13) /* Allow 16-Word SBus Burst */

Definition at line 330 of file dbri.c.

#define D_SDP 0x5 /* Setup Data Pipe */

Definition at line 367 of file dbri.c.

#define D_SDP_2SAME (1<<18) /* Report 2nd time in a row value received */

Definition at line 383 of file dbri.c.

#define D_SDP_A (1<<8) /* Abort */

Definition at line 402 of file dbri.c.

#define D_SDP_C (1<<7) /* Clear */

Definition at line 403 of file dbri.c.

#define D_SDP_CHANGE (2<<18) /* Report any changes */

Definition at line 384 of file dbri.c.

#define D_SDP_EOL (1<<17) /* EOL interrupt enable */

Definition at line 386 of file dbri.c.

#define D_SDP_EVERY (3<<18) /* Report any changes */

Definition at line 385 of file dbri.c.

#define D_SDP_FIXED (6<<13) /* Short only */

Definition at line 394 of file dbri.c.

#define D_SDP_FROM_SER (0<<12) /* Direction */

Definition at line 398 of file dbri.c.

#define D_SDP_HDLC (2<<13)

Definition at line 391 of file dbri.c.

#define D_SDP_HDLC_D (3<<13) /* D Channel (prio control) */

Definition at line 392 of file dbri.c.

#define D_SDP_IDLE (1<<16) /* HDLC idle interrupt enable */

Definition at line 387 of file dbri.c.

#define D_SDP_LSB (0<<11) /* Bit order within Byte */

Definition at line 400 of file dbri.c.

#define D_SDP_MEM (0<<13) /* To/from memory */

Definition at line 390 of file dbri.c.

#define D_SDP_MODE ( v ) ((v)&(7<<13))

Definition at line 395 of file dbri.c.

#define D_SDP_MSB (1<<11) /* Bit order within Byte */

Definition at line 399 of file dbri.c.

#define D_SDP_P (1<<10) /* Pointer Valid */

Definition at line 401 of file dbri.c.

#define D_SDP_SER (4<<13) /* Serial to serial */

Definition at line 393 of file dbri.c.

#define D_SDP_TO_SER (1<<12) /* Direction */

Definition at line 397 of file dbri.c.

#define D_SSP 0x8 /* Set short Data Pipe */

Definition at line 370 of file dbri.c.

#define D_T (1<<6) /* Permit activation of the TE interface */

Definition at line 333 of file dbri.c.

#define D_TE 0xb /* TE Command */

Definition at line 373 of file dbri.c.

#define D_TEST 0xd /* No comment */

Definition at line 375 of file dbri.c.

#define D_TEST_DUMP 0xe /* ROM Dump */

Definition at line 464 of file dbri.c.

#define D_TEST_MCBIST 0xb /* Microcontroller Built-In Self Test */

Definition at line 463 of file dbri.c.

#define D_TEST_PROC 0x6 /* Microprocessor test */

Definition at line 458 of file dbri.c.

#define D_TEST_RAM ( v ) ((v)<<16) /* RAM Pointer */

Definition at line 455 of file dbri.c.

#define D_TEST_RAMBIST 0xa /* RAM Built-In Self Test */

Definition at line 462 of file dbri.c.

#define D_TEST_RAMREAD 0x8 /* Copy from Ram to system memory */

Definition at line 460 of file dbri.c.

#define D_TEST_RAMWRITE 0x9 /* Copy into Ram from system memory */

Definition at line 461 of file dbri.c.

#define D_TEST_ROMONOFF 0x5 /* Toggle ROM opcode monitor on/off */

Definition at line 457 of file dbri.c.

#define D_TEST_SER 0x7 /* Serial-Controller test */

Definition at line 459 of file dbri.c.

#define D_TEST_SIZE ( v ) ((v)<<11) /* */

Definition at line 456 of file dbri.c.

#define D_TS_1CHANNEL (0<<10) /* Single Channel / Normal mode */

Definition at line 417 of file dbri.c.

#define D_TS_ANCHOR (7<<10) /* Starting short pipes */

Definition at line 420 of file dbri.c.

#define D_TS_CYCLE ( v ) ((v)<<14) /* Bit Count at start of TS */

Definition at line 415 of file dbri.c.

#define D_TS_DI (1<<13) /* Data Invert */

Definition at line 416 of file dbri.c.

#define D_TS_LEN ( v ) ((v)<<24) /* Number of bits in this time slot */

Definition at line 414 of file dbri.c.

#define D_TS_MON ( v ) ((v)<<5) /* Monitor Pipe */

Definition at line 421 of file dbri.c.

#define D_TS_MONITOR (2<<10) /* Monitor pipe */

Definition at line 418 of file dbri.c.

#define D_TS_NEXT ( v ) ((v)<<0) /* Pipe no.: 0-15 long, 16-21 short */

Definition at line 422 of file dbri.c.

#define D_TS_NONCONTIG (3<<10) /* Non contiguous mode */

Definition at line 419 of file dbri.c.

#define D_USR (1<<4)

Definition at line 98 of file dbri.c.

#define D_WAIT 0x0 /* Stop execution */

Definition at line 362 of file dbri.c.

#define D_X (1<<7) /* Sanity Timer Disable */

Definition at line 332 of file dbri.c.

#define DBRI_CMD	(	cmd,
		intr,
		value
	)

Value:

((cmd << 28) |  \
                    (intr << 27) |  \
                    value)

Definition at line 118 of file dbri.c.

#define dbri_dma_off	(	member,
		elem
	)

Value:

((u32)(unsigned long) \

(&(((struct dbri_dma *)0)->member[elem])))

Definition at line 274 of file dbri.c.

#define DBRI_INT_BLK 64

Definition at line 247 of file dbri.c.

#define DBRI_MAX_GAIN 15 /* Input gain */

Definition at line 325 of file dbri.c.

#define DBRI_MAX_PIPE (DBRI_NO_PIPES - 1)

Definition at line 250 of file dbri.c.

#define DBRI_MAX_VOLUME 63 /* Output volume */

Definition at line 324 of file dbri.c.

#define DBRI_NO_CMDS 64

Definition at line 246 of file dbri.c.

#define DBRI_NO_DESCS 64

Definition at line 248 of file dbri.c.

#define DBRI_NO_PIPES 32

Definition at line 249 of file dbri.c.

#define DBRI_NO_STREAMS 2

Definition at line 254 of file dbri.c.

#define DBRI_PLAY 1

Definition at line 253 of file dbri.c.

#define DBRI_RD_ABT (1 << 5) /* Abort: frame aborted */

Definition at line 558 of file dbri.c.

#define DBRI_RD_B (1 << 15) /* Final interrupt */

Definition at line 553 of file dbri.c.

#define DBRI_RD_BBC (1 << 6) /* 1: Bad Byte received */

Definition at line 557 of file dbri.c.

#define DBRI_RD_BCNT ( v ) (v) /* Buffer size */

Definition at line 555 of file dbri.c.

#define DBRI_RD_C (1 << 30) /* Completed buffer */

Definition at line 552 of file dbri.c.

#define DBRI_RD_CNT ( v ) (((v) >> 16) & 0x1fff) /* Valid bytes in the buffer */

Definition at line 561 of file dbri.c.

#define DBRI_RD_CRC (1 << 7) /* 0: CRC is correct */

Definition at line 556 of file dbri.c.

#define DBRI_RD_F (1 << 31) /* End of Frame */

Definition at line 551 of file dbri.c.

#define DBRI_RD_M (1 << 14) /* Marker interrupt */

Definition at line 554 of file dbri.c.

#define DBRI_RD_OVRN (1 << 3) /* Overrun: data lost */

Definition at line 559 of file dbri.c.

#define DBRI_RD_STATUS ( v ) ((v) & 0xff) /* Receive status */

Definition at line 560 of file dbri.c.

#define DBRI_REC 0

Definition at line 252 of file dbri.c.

#define DBRI_STREAM	(	dbri,
		substream
	)	&dbri->stream_info[DBRI_STREAMNO(substream)]

Definition at line 570 of file dbri.c.

#define DBRI_STREAMNO ( substream )

Value:

(substream->stream == \

SNDRV_PCM_STREAM_PLAYBACK ? DBRI_PLAY: DBRI_REC)

Definition at line 565 of file dbri.c.

#define DBRI_TD_ABT (1 << 2) /* Abort: frame aborted */

Definition at line 544 of file dbri.c.

#define DBRI_TD_B (1 << 15) /* Final interrupt */

Definition at line 539 of file dbri.c.

#define DBRI_TD_CNT ( v ) ((v) << 16) /* Number of valid bytes in the buffer */

Definition at line 538 of file dbri.c.

#define DBRI_TD_D (1 << 30) /* Do not append CRC */

Definition at line 537 of file dbri.c.

#define DBRI_TD_F (1 << 31) /* End of Frame */

Definition at line 536 of file dbri.c.

#define DBRI_TD_FCNT ( v ) (v) /* Flag Count */

Definition at line 542 of file dbri.c.

#define DBRI_TD_I (1 << 13) /* Transmit Idle Characters */

Definition at line 541 of file dbri.c.

#define DBRI_TD_M (1 << 14) /* Marker interrupt */

Definition at line 540 of file dbri.c.

#define DBRI_TD_MAXCNT ((1 << 13) - 4)

Definition at line 548 of file dbri.c.

#define DBRI_TD_STATUS ( v ) ((v) & 0xff) /* Transmit status */

Definition at line 546 of file dbri.c.

#define DBRI_TD_TBC (1 << 0) /* Transmit buffer Complete */

Definition at line 545 of file dbri.c.

#define DBRI_TD_UNR (1 << 3) /* Underrun: transmitter is out of data */

Definition at line 543 of file dbri.c.

#define dprintk	(	a,
		x...
	)	do { } while (0)

Definition at line 114 of file dbri.c.

#define MAXLOOPS 20

Definition at line 630 of file dbri.c.

#define REG0 0x00 /* Status and Control */

Definition at line 239 of file dbri.c.

#define REG1 0x04 /* Mode and Interrupt */

Definition at line 240 of file dbri.c.

#define REG2 0x08 /* Parallel IO */

Definition at line 241 of file dbri.c.

#define REG3 0x0c /* Test */

Definition at line 242 of file dbri.c.

#define REG8 0x20 /* Command Queue Pointer */

Definition at line 243 of file dbri.c.

#define REG9 0x24 /* Interrupt Queue Pointer */

Definition at line 244 of file dbri.c.

Enumeration Type Documentation

enum in_or_out

Enumerator:

PIPEinput
PIPEoutput

Definition at line 278 of file dbri.c.

enum master_or_slave

Enumerator:

CHImaster
CHIslave

Definition at line 1226 of file dbri.c.

Function Documentation

MODULE_AUTHOR	(	"Rudolf	Koenig,
		Brent Baccala and Martin Habets"
	)

MODULE_DESCRIPTION ( "Sun DBRI" )

MODULE_DEVICE_TABLE	(	of	,
		dbri_match
	)

MODULE_LICENSE ( "GPL" )

module_param	(	dbri_debug	,
		int	,
		0644
	)

module_param_array	(	index	,
		int	,
		NULL	,
		0444
	)

module_param_array	(	id	,
		charp	,
		NULL	,
		0444
	)

module_param_array	(	enable	,
		bool	,
		NULL	,
		0444
	)

MODULE_PARM_DESC	(	index	,
		"Index value for Sun DBRI soundcard."
	)

MODULE_PARM_DESC	(	id	,
		"ID string for Sun DBRI soundcard."
	)

MODULE_PARM_DESC	(	enable	,
		"Enable Sun DBRI soundcard."
	)

MODULE_PARM_DESC	(	dbri_debug	,
		"Debug value for Sun DBRI soundcard."
	)

module_platform_driver ( dbri_sbus_driver )

MODULE_SUPPORTED_DEVICE ( "{{Sun,DBRI}}" )

Variable Documentation

unsigned char csval

Definition at line 157 of file dbri.c.

unsigned short freq

Definition at line 155 of file dbri.c.

unsigned char xtal

Definition at line 156 of file dbri.c.

Data Structures

Macros

Enumerations

Functions

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation

Variable Documentation