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| #define | DRIVER_NAME "S5K6AA" |
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| #define | S5K6AA_TERM 0xffff |
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| #define | S5K6AA_OUT_WIDTH_DEF 640 |
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| #define | S5K6AA_OUT_HEIGHT_DEF 480 |
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| #define | S5K6AA_WIN_WIDTH_MAX 1280 |
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| #define | S5K6AA_WIN_HEIGHT_MAX 1024 |
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| #define | S5K6AA_WIN_WIDTH_MIN 8 |
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| #define | S5K6AA_WIN_HEIGHT_MIN 8 |
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| #define | AHB_MSB_ADDR_PTR 0xfcfc |
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| #define | GEN_REG_OFFSH 0xd000 |
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| #define | REG_CMDWR_ADDRH 0x0028 |
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| #define | REG_CMDWR_ADDRL 0x002a |
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| #define | REG_CMDRD_ADDRH 0x002c |
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| #define | REG_CMDRD_ADDRL 0x002e |
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| #define | REG_CMDBUF0_ADDR 0x0f12 |
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| #define | REG_CMDBUF1_ADDR 0x0f10 |
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| #define | HOST_SWIF_OFFSH 0x7000 |
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| #define | REG_I_INCLK_FREQ_L 0x01b8 |
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| #define | REG_I_INCLK_FREQ_H 0x01ba |
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| #define | MIN_MCLK_FREQ_KHZ 6000U |
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| #define | MAX_MCLK_FREQ_KHZ 27000U |
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| #define | REG_I_USE_NPVI_CLOCKS 0x01c6 |
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| #define | REG_I_USE_NMIPI_CLOCKS 0x01c8 |
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| #define | REG_I_OPCLK_4KHZ(n) ((n) * 6 + 0x01cc) |
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| #define | REG_I_MIN_OUTRATE_4KHZ(n) ((n) * 6 + 0x01ce) |
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| #define | REG_I_MAX_OUTRATE_4KHZ(n) ((n) * 6 + 0x01d0) |
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| #define | SYS_PLL_OUT_FREQ (48000000 / 4000) |
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| #define | PCLK_FREQ_MIN (24000000 / 4000) |
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| #define | PCLK_FREQ_MAX (48000000 / 4000) |
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| #define | REG_I_INIT_PARAMS_UPDATED 0x01e0 |
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| #define | REG_I_ERROR_INFO 0x01e2 |
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| #define | REG_USER_BRIGHTNESS 0x01e4 |
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| #define | REG_USER_CONTRAST 0x01e6 |
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| #define | REG_USER_SATURATION 0x01e8 |
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| #define | REG_USER_SHARPBLUR 0x01ea |
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| #define | REG_G_SPEC_EFFECTS 0x01ee |
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| #define | REG_G_ENABLE_PREV 0x01f0 |
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| #define | REG_G_ENABLE_PREV_CHG 0x01f2 |
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| #define | REG_G_NEW_CFG_SYNC 0x01f8 |
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| #define | REG_G_PREVZOOM_IN_WIDTH 0x020a |
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| #define | REG_G_PREVZOOM_IN_HEIGHT 0x020c |
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| #define | REG_G_PREVZOOM_IN_XOFFS 0x020e |
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| #define | REG_G_PREVZOOM_IN_YOFFS 0x0210 |
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| #define | REG_G_INPUTS_CHANGE_REQ 0x021a |
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| #define | REG_G_ACTIVE_PREV_CFG 0x021c |
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| #define | REG_G_PREV_CFG_CHG 0x021e |
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| #define | REG_G_PREV_OPEN_AFTER_CH 0x0220 |
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| #define | REG_G_PREV_CFG_ERROR 0x0222 |
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| #define | PREG(n, x) ((n) * 0x26 + x) |
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| #define | REG_P_OUT_WIDTH(n) PREG(n, 0x0242) |
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| #define | REG_P_OUT_HEIGHT(n) PREG(n, 0x0244) |
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| #define | REG_P_FMT(n) PREG(n, 0x0246) |
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| #define | REG_P_MAX_OUT_RATE(n) PREG(n, 0x0248) |
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| #define | REG_P_MIN_OUT_RATE(n) PREG(n, 0x024a) |
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| #define | REG_P_PVI_MASK(n) PREG(n, 0x024c) |
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| #define | REG_P_CLK_INDEX(n) PREG(n, 0x024e) |
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| #define | REG_P_FR_RATE_TYPE(n) PREG(n, 0x0250) |
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| #define | FR_RATE_DYNAMIC 0 |
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| #define | FR_RATE_FIXED 1 |
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| #define | FR_RATE_FIXED_ACCURATE 2 |
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| #define | REG_P_FR_RATE_Q_TYPE(n) PREG(n, 0x0252) |
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| #define | FR_RATE_Q_BEST_FRRATE 1 /* Binning enabled */ |
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| #define | FR_RATE_Q_BEST_QUALITY 2 /* Binning disabled */ |
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| #define | REG_P_MAX_FR_TIME(n) PREG(n, 0x0254) |
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| #define | REG_P_MIN_FR_TIME(n) PREG(n, 0x0256) |
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| #define | US_TO_FR_TIME(__t) ((__t) / 100) |
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| #define | S5K6AA_MIN_FR_TIME 33300 /* us */ |
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| #define | S5K6AA_MAX_FR_TIME 650000 /* us */ |
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| #define | S5K6AA_MAX_HIGHRES_FR_TIME 666 /* x100 us */ |
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| #define | REG_P_COLORTEMP(n) PREG(n, 0x025e) |
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| #define | REG_P_PREV_MIRROR(n) PREG(n, 0x0262) |
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| #define | REG_SF_USR_EXPOSURE_L 0x03c6 |
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| #define | REG_SF_USR_EXPOSURE_H 0x03c8 |
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| #define | REG_SF_USR_EXPOSURE_CHG 0x03ca |
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| #define | REG_SF_USR_TOT_GAIN 0x03cc |
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| #define | REG_SF_USR_TOT_GAIN_CHG 0x03ce |
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| #define | REG_SF_RGAIN 0x03d0 |
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| #define | REG_SF_RGAIN_CHG 0x03d2 |
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| #define | REG_SF_GGAIN 0x03d4 |
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| #define | REG_SF_GGAIN_CHG 0x03d6 |
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| #define | REG_SF_BGAIN 0x03d8 |
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| #define | REG_SF_BGAIN_CHG 0x03da |
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| #define | REG_SF_FLICKER_QUANT 0x03dc |
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| #define | REG_SF_FLICKER_QUANT_CHG 0x03de |
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| #define | REG_OIF_EN_MIPI_LANES 0x03fa |
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| #define | REG_OIF_EN_PACKETS 0x03fc |
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| #define | REG_OIF_CFG_CHG 0x03fe |
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| #define | REG_DBG_AUTOALG_EN 0x0400 |
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| #define | AALG_ALL_EN_MASK (1 << 0) |
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| #define | AALG_AE_EN_MASK (1 << 1) |
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| #define | AALG_DIVLEI_EN_MASK (1 << 2) |
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| #define | AALG_WB_EN_MASK (1 << 3) |
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| #define | AALG_FLICKER_EN_MASK (1 << 5) |
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| #define | AALG_FIT_EN_MASK (1 << 6) |
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| #define | AALG_WRHW_EN_MASK (1 << 7) |
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| #define | REG_FW_APIVER 0x012e |
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| #define | S5K6AAFX_FW_APIVER 0x0001 |
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| #define | REG_FW_REVISION 0x0130 |
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| #define | S5K6AA_MAX_PRESETS 1 |
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| #define | S5K6AA_NUM_SUPPLIES ARRAY_SIZE(s5k6aa_supply_names) |
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| #define | S5K6AA_INTERVAL_DEF_INDEX 1 /* 15 fps */ |
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| #define | V4L2_CID_RED_GAIN (V4L2_CTRL_CLASS_CAMERA | 0x1001) |
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| #define | V4L2_CID_GREEN_GAIN (V4L2_CTRL_CLASS_CAMERA | 0x1002) |
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| #define | V4L2_CID_BLUE_GAIN (V4L2_CTRL_CLASS_CAMERA | 0x1003) |
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1.8.2