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setup-sh7722.c
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1 /*
2  * SH7722 Setup
3  *
4  * Copyright (C) 2006 - 2008 Paul Mundt
5  *
6  * This file is subject to the terms and conditions of the GNU General Public
7  * License. See the file "COPYING" in the main directory of this archive
8  * for more details.
9  */
10 #include <linux/init.h>
11 #include <linux/mm.h>
12 #include <linux/platform_device.h>
13 #include <linux/serial.h>
14 #include <linux/serial_sci.h>
15 #include <linux/sh_dma.h>
16 #include <linux/sh_timer.h>
17 #include <linux/sh_intc.h>
18 #include <linux/uio_driver.h>
19 #include <linux/usb/m66592.h>
20 
21 #include <asm/clock.h>
22 #include <asm/mmzone.h>
23 #include <asm/siu.h>
24 
25 #include <cpu/dma-register.h>
26 #include <cpu/sh7722.h>
27 #include <cpu/serial.h>
28 
29 static const struct sh_dmae_slave_config sh7722_dmae_slaves[] = {
30  {
31  .slave_id = SHDMA_SLAVE_SCIF0_TX,
32  .addr = 0xffe0000c,
33  .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
34  .mid_rid = 0x21,
35  }, {
36  .slave_id = SHDMA_SLAVE_SCIF0_RX,
37  .addr = 0xffe00014,
38  .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
39  .mid_rid = 0x22,
40  }, {
41  .slave_id = SHDMA_SLAVE_SCIF1_TX,
42  .addr = 0xffe1000c,
43  .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
44  .mid_rid = 0x25,
45  }, {
46  .slave_id = SHDMA_SLAVE_SCIF1_RX,
47  .addr = 0xffe10014,
48  .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
49  .mid_rid = 0x26,
50  }, {
51  .slave_id = SHDMA_SLAVE_SCIF2_TX,
52  .addr = 0xffe2000c,
53  .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
54  .mid_rid = 0x29,
55  }, {
56  .slave_id = SHDMA_SLAVE_SCIF2_RX,
57  .addr = 0xffe20014,
58  .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
59  .mid_rid = 0x2a,
60  }, {
61  .slave_id = SHDMA_SLAVE_SIUA_TX,
62  .addr = 0xa454c098,
63  .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
64  .mid_rid = 0xb1,
65  }, {
66  .slave_id = SHDMA_SLAVE_SIUA_RX,
67  .addr = 0xa454c090,
68  .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
69  .mid_rid = 0xb2,
70  }, {
71  .slave_id = SHDMA_SLAVE_SIUB_TX,
72  .addr = 0xa454c09c,
73  .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
74  .mid_rid = 0xb5,
75  }, {
76  .slave_id = SHDMA_SLAVE_SIUB_RX,
77  .addr = 0xa454c094,
78  .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
79  .mid_rid = 0xb6,
80  }, {
81  .slave_id = SHDMA_SLAVE_SDHI0_TX,
82  .addr = 0x04ce0030,
83  .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
84  .mid_rid = 0xc1,
85  }, {
86  .slave_id = SHDMA_SLAVE_SDHI0_RX,
87  .addr = 0x04ce0030,
88  .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
89  .mid_rid = 0xc2,
90  },
91 };
92 
93 static const struct sh_dmae_channel sh7722_dmae_channels[] = {
94  {
95  .offset = 0,
96  .dmars = 0,
97  .dmars_bit = 0,
98  }, {
99  .offset = 0x10,
100  .dmars = 0,
101  .dmars_bit = 8,
102  }, {
103  .offset = 0x20,
104  .dmars = 4,
105  .dmars_bit = 0,
106  }, {
107  .offset = 0x30,
108  .dmars = 4,
109  .dmars_bit = 8,
110  }, {
111  .offset = 0x50,
112  .dmars = 8,
113  .dmars_bit = 0,
114  }, {
115  .offset = 0x60,
116  .dmars = 8,
117  .dmars_bit = 8,
118  }
119 };
120 
121 static const unsigned int ts_shift[] = TS_SHIFT;
122 
123 static struct sh_dmae_pdata dma_platform_data = {
124  .slave = sh7722_dmae_slaves,
125  .slave_num = ARRAY_SIZE(sh7722_dmae_slaves),
126  .channel = sh7722_dmae_channels,
127  .channel_num = ARRAY_SIZE(sh7722_dmae_channels),
128  .ts_low_shift = CHCR_TS_LOW_SHIFT,
129  .ts_low_mask = CHCR_TS_LOW_MASK,
130  .ts_high_shift = CHCR_TS_HIGH_SHIFT,
131  .ts_high_mask = CHCR_TS_HIGH_MASK,
132  .ts_shift = ts_shift,
133  .ts_shift_num = ARRAY_SIZE(ts_shift),
134  .dmaor_init = DMAOR_INIT,
135 };
136 
137 static struct resource sh7722_dmae_resources[] = {
138  [0] = {
139  /* Channel registers and DMAOR */
140  .start = 0xfe008020,
141  .end = 0xfe00808f,
142  .flags = IORESOURCE_MEM,
143  },
144  [1] = {
145  /* DMARSx */
146  .start = 0xfe009000,
147  .end = 0xfe00900b,
148  .flags = IORESOURCE_MEM,
149  },
150  {
151  .name = "error_irq",
152  .start = evt2irq(0xbc0),
153  .end = evt2irq(0xbc0),
154  .flags = IORESOURCE_IRQ,
155  },
156  {
157  /* IRQ for channels 0-3 */
158  .start = evt2irq(0x800),
159  .end = evt2irq(0x860),
160  .flags = IORESOURCE_IRQ,
161  },
162  {
163  /* IRQ for channels 4-5 */
164  .start = evt2irq(0xb80),
165  .end = evt2irq(0xba0),
166  .flags = IORESOURCE_IRQ,
167  },
168 };
169 
170 struct platform_device dma_device = {
171  .name = "sh-dma-engine",
172  .id = -1,
173  .resource = sh7722_dmae_resources,
174  .num_resources = ARRAY_SIZE(sh7722_dmae_resources),
175  .dev = {
176  .platform_data = &dma_platform_data,
177  },
178 };
179 
180 /* Serial */
181 static struct plat_sci_port scif0_platform_data = {
182  .mapbase = 0xffe00000,
183  .flags = UPF_BOOT_AUTOCONF,
184  .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
185  .scbrr_algo_id = SCBRR_ALGO_2,
186  .type = PORT_SCIF,
187  .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)),
188  .ops = &sh7722_sci_port_ops,
189  .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
190 };
191 
192 static struct platform_device scif0_device = {
193  .name = "sh-sci",
194  .id = 0,
195  .dev = {
196  .platform_data = &scif0_platform_data,
197  },
198 };
199 
200 static struct plat_sci_port scif1_platform_data = {
201  .mapbase = 0xffe10000,
202  .flags = UPF_BOOT_AUTOCONF,
203  .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
204  .scbrr_algo_id = SCBRR_ALGO_2,
205  .type = PORT_SCIF,
206  .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)),
207  .ops = &sh7722_sci_port_ops,
208  .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
209 };
210 
211 static struct platform_device scif1_device = {
212  .name = "sh-sci",
213  .id = 1,
214  .dev = {
215  .platform_data = &scif1_platform_data,
216  },
217 };
218 
219 static struct plat_sci_port scif2_platform_data = {
220  .mapbase = 0xffe20000,
221  .flags = UPF_BOOT_AUTOCONF,
222  .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
223  .scbrr_algo_id = SCBRR_ALGO_2,
224  .type = PORT_SCIF,
225  .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)),
226  .ops = &sh7722_sci_port_ops,
227  .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
228 };
229 
230 static struct platform_device scif2_device = {
231  .name = "sh-sci",
232  .id = 2,
233  .dev = {
234  .platform_data = &scif2_platform_data,
235  },
236 };
237 
238 static struct resource rtc_resources[] = {
239  [0] = {
240  .start = 0xa465fec0,
241  .end = 0xa465fec0 + 0x58 - 1,
242  .flags = IORESOURCE_IO,
243  },
244  [1] = {
245  /* Period IRQ */
246  .start = evt2irq(0x7a0),
247  .flags = IORESOURCE_IRQ,
248  },
249  [2] = {
250  /* Carry IRQ */
251  .start = evt2irq(0x7c0),
252  .flags = IORESOURCE_IRQ,
253  },
254  [3] = {
255  /* Alarm IRQ */
256  .start = evt2irq(0x780),
257  .flags = IORESOURCE_IRQ,
258  },
259 };
260 
261 static struct platform_device rtc_device = {
262  .name = "sh-rtc",
263  .id = -1,
264  .num_resources = ARRAY_SIZE(rtc_resources),
265  .resource = rtc_resources,
266 };
267 
268 static struct m66592_platdata usbf_platdata = {
269  .on_chip = 1,
270 };
271 
272 static struct resource usbf_resources[] = {
273  [0] = {
274  .name = "USBF",
275  .start = 0x04480000,
276  .end = 0x044800FF,
277  .flags = IORESOURCE_MEM,
278  },
279  [1] = {
280  .start = evt2irq(0xa20),
281  .end = evt2irq(0xa20),
282  .flags = IORESOURCE_IRQ,
283  },
284 };
285 
286 static struct platform_device usbf_device = {
287  .name = "m66592_udc",
288  .id = 0, /* "usbf0" clock */
289  .dev = {
290  .dma_mask = NULL,
291  .coherent_dma_mask = 0xffffffff,
292  .platform_data = &usbf_platdata,
293  },
294  .num_resources = ARRAY_SIZE(usbf_resources),
295  .resource = usbf_resources,
296 };
297 
298 static struct resource iic_resources[] = {
299  [0] = {
300  .name = "IIC",
301  .start = 0x04470000,
302  .end = 0x04470017,
303  .flags = IORESOURCE_MEM,
304  },
305  [1] = {
306  .start = evt2irq(0xe00),
307  .end = evt2irq(0xe60),
308  .flags = IORESOURCE_IRQ,
309  },
310 };
311 
312 static struct platform_device iic_device = {
313  .name = "i2c-sh_mobile",
314  .id = 0, /* "i2c0" clock */
315  .num_resources = ARRAY_SIZE(iic_resources),
316  .resource = iic_resources,
317 };
318 
319 static struct uio_info vpu_platform_data = {
320  .name = "VPU4",
321  .version = "0",
322  .irq = evt2irq(0x980),
323 };
324 
325 static struct resource vpu_resources[] = {
326  [0] = {
327  .name = "VPU",
328  .start = 0xfe900000,
329  .end = 0xfe9022eb,
330  .flags = IORESOURCE_MEM,
331  },
332  [1] = {
333  /* place holder for contiguous memory */
334  },
335 };
336 
337 static struct platform_device vpu_device = {
338  .name = "uio_pdrv_genirq",
339  .id = 0,
340  .dev = {
341  .platform_data = &vpu_platform_data,
342  },
343  .resource = vpu_resources,
344  .num_resources = ARRAY_SIZE(vpu_resources),
345 };
346 
347 static struct uio_info veu_platform_data = {
348  .name = "VEU",
349  .version = "0",
350  .irq = evt2irq(0x8c0),
351 };
352 
353 static struct resource veu_resources[] = {
354  [0] = {
355  .name = "VEU",
356  .start = 0xfe920000,
357  .end = 0xfe9200b7,
358  .flags = IORESOURCE_MEM,
359  },
360  [1] = {
361  /* place holder for contiguous memory */
362  },
363 };
364 
365 static struct platform_device veu_device = {
366  .name = "uio_pdrv_genirq",
367  .id = 1,
368  .dev = {
369  .platform_data = &veu_platform_data,
370  },
371  .resource = veu_resources,
372  .num_resources = ARRAY_SIZE(veu_resources),
373 };
374 
375 static struct uio_info jpu_platform_data = {
376  .name = "JPU",
377  .version = "0",
378  .irq = evt2irq(0x560),
379 };
380 
381 static struct resource jpu_resources[] = {
382  [0] = {
383  .name = "JPU",
384  .start = 0xfea00000,
385  .end = 0xfea102d3,
386  .flags = IORESOURCE_MEM,
387  },
388  [1] = {
389  /* place holder for contiguous memory */
390  },
391 };
392 
393 static struct platform_device jpu_device = {
394  .name = "uio_pdrv_genirq",
395  .id = 2,
396  .dev = {
397  .platform_data = &jpu_platform_data,
398  },
399  .resource = jpu_resources,
400  .num_resources = ARRAY_SIZE(jpu_resources),
401 };
402 
403 static struct sh_timer_config cmt_platform_data = {
404  .channel_offset = 0x60,
405  .timer_bit = 5,
406  .clockevent_rating = 125,
407  .clocksource_rating = 125,
408 };
409 
410 static struct resource cmt_resources[] = {
411  [0] = {
412  .start = 0x044a0060,
413  .end = 0x044a006b,
414  .flags = IORESOURCE_MEM,
415  },
416  [1] = {
417  .start = evt2irq(0xf00),
418  .flags = IORESOURCE_IRQ,
419  },
420 };
421 
422 static struct platform_device cmt_device = {
423  .name = "sh_cmt",
424  .id = 0,
425  .dev = {
426  .platform_data = &cmt_platform_data,
427  },
428  .resource = cmt_resources,
429  .num_resources = ARRAY_SIZE(cmt_resources),
430 };
431 
432 static struct sh_timer_config tmu0_platform_data = {
433  .channel_offset = 0x04,
434  .timer_bit = 0,
435  .clockevent_rating = 200,
436 };
437 
438 static struct resource tmu0_resources[] = {
439  [0] = {
440  .start = 0xffd80008,
441  .end = 0xffd80013,
442  .flags = IORESOURCE_MEM,
443  },
444  [1] = {
445  .start = evt2irq(0x400),
446  .flags = IORESOURCE_IRQ,
447  },
448 };
449 
450 static struct platform_device tmu0_device = {
451  .name = "sh_tmu",
452  .id = 0,
453  .dev = {
454  .platform_data = &tmu0_platform_data,
455  },
456  .resource = tmu0_resources,
457  .num_resources = ARRAY_SIZE(tmu0_resources),
458 };
459 
460 static struct sh_timer_config tmu1_platform_data = {
461  .channel_offset = 0x10,
462  .timer_bit = 1,
463  .clocksource_rating = 200,
464 };
465 
466 static struct resource tmu1_resources[] = {
467  [0] = {
468  .start = 0xffd80014,
469  .end = 0xffd8001f,
470  .flags = IORESOURCE_MEM,
471  },
472  [1] = {
473  .start = evt2irq(0x420),
474  .flags = IORESOURCE_IRQ,
475  },
476 };
477 
478 static struct platform_device tmu1_device = {
479  .name = "sh_tmu",
480  .id = 1,
481  .dev = {
482  .platform_data = &tmu1_platform_data,
483  },
484  .resource = tmu1_resources,
485  .num_resources = ARRAY_SIZE(tmu1_resources),
486 };
487 
488 static struct sh_timer_config tmu2_platform_data = {
489  .channel_offset = 0x1c,
490  .timer_bit = 2,
491 };
492 
493 static struct resource tmu2_resources[] = {
494  [0] = {
495  .start = 0xffd80020,
496  .end = 0xffd8002b,
497  .flags = IORESOURCE_MEM,
498  },
499  [1] = {
500  .start = 18,
501  .flags = IORESOURCE_IRQ,
502  },
503 };
504 
505 static struct platform_device tmu2_device = {
506  .name = "sh_tmu",
507  .id = 2,
508  .dev = {
509  .platform_data = &tmu2_platform_data,
510  },
511  .resource = tmu2_resources,
512  .num_resources = ARRAY_SIZE(tmu2_resources),
513 };
514 
515 static struct siu_platform siu_platform_data = {
516  .dma_slave_tx_a = SHDMA_SLAVE_SIUA_TX,
517  .dma_slave_rx_a = SHDMA_SLAVE_SIUA_RX,
518  .dma_slave_tx_b = SHDMA_SLAVE_SIUB_TX,
519  .dma_slave_rx_b = SHDMA_SLAVE_SIUB_RX,
520 };
521 
522 static struct resource siu_resources[] = {
523  [0] = {
524  .start = 0xa4540000,
525  .end = 0xa454c10f,
526  .flags = IORESOURCE_MEM,
527  },
528  [1] = {
529  .start = evt2irq(0xf80),
530  .flags = IORESOURCE_IRQ,
531  },
532 };
533 
534 static struct platform_device siu_device = {
535  .name = "siu-pcm-audio",
536  .id = -1,
537  .dev = {
538  .platform_data = &siu_platform_data,
539  },
540  .resource = siu_resources,
541  .num_resources = ARRAY_SIZE(siu_resources),
542 };
543 
544 static struct platform_device *sh7722_devices[] __initdata = {
545  &scif0_device,
546  &scif1_device,
547  &scif2_device,
548  &cmt_device,
549  &tmu0_device,
550  &tmu1_device,
551  &tmu2_device,
552  &rtc_device,
553  &usbf_device,
554  &iic_device,
555  &vpu_device,
556  &veu_device,
557  &jpu_device,
558  &siu_device,
559  &dma_device,
560 };
561 
562 static int __init sh7722_devices_setup(void)
563 {
564  platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
565  platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
566  platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
567 
568  return platform_add_devices(sh7722_devices,
569  ARRAY_SIZE(sh7722_devices));
570 }
571 arch_initcall(sh7722_devices_setup);
572 
573 static struct platform_device *sh7722_early_devices[] __initdata = {
574  &scif0_device,
575  &scif1_device,
576  &scif2_device,
577  &cmt_device,
578  &tmu0_device,
579  &tmu1_device,
580  &tmu2_device,
581 };
582 
583 void __init plat_early_device_setup(void)
584 {
585  early_platform_add_devices(sh7722_early_devices,
586  ARRAY_SIZE(sh7722_early_devices));
587 }
588 
589 enum {
590  UNUSED=0,
591  ENABLED,
592  DISABLED,
593 
594  /* interrupt sources */
595  IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
596  HUDI,
597  SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
598  RTC_ATI, RTC_PRI, RTC_CUI,
599  DMAC0, DMAC1, DMAC2, DMAC3,
600  VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
601  VPU, TPU,
602  USB_USBI0, USB_USBI1,
603  DMAC4, DMAC5, DMAC_DADERR,
604  KEYSC,
605  SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
606  FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
607  I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
608  CMT, TSIF, SIU, TWODG,
609  TMU0, TMU1, TMU2,
610  IRDA, JPU, LCDC,
611 
612  /* interrupt groups */
613  SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
614 };
615 
616 static struct intc_vect vectors[] __initdata = {
617  INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
618  INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
619  INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
620  INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
621  INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720),
622  INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760),
623  INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0),
624  INTC_VECT(RTC_CUI, 0x7c0),
625  INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
626  INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
627  INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
628  INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
629  INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0),
630  INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40),
631  INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
632  INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
633  INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20),
634  INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80),
635  INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00),
636  INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
637  INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
638  INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
639  INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
640  INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
641  INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
642  INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
643  INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
644  INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
645  INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480),
646  INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
647 };
648 
649 static struct intc_group groups[] __initdata = {
650  INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
651  INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
652  INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
653  INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
654  INTC_GROUP(USB, USB_USBI0, USB_USBI1),
655  INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
656  INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
657  FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
658  INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
659 };
660 
661 static struct intc_mask_reg mask_registers[] __initdata = {
662  { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
663  { } },
664  { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
665  { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
666  { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
667  { 0, 0, 0, VPU, } },
668  { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
669  { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
670  { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
671  { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
672  { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
673  { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } },
674  { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
675  { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } },
676  { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
677  { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
678  FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
679  { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
680  { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } },
681  { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
682  { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
683  { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
684  { } },
685  { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
686  { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } },
687  { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
688  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
689 };
690 
691 static struct intc_prio_reg prio_registers[] __initdata = {
692  { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
693  { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
694  { 0xa4080008, 0, 16, 4, /* IPRC */ { } },
695  { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
696  { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
697  { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
698  { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
699  { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
700  { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
701  { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
702  { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
703  { 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
704  { 0xa4140010, 0, 32, 4, /* INTPRI00 */
705  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
706 };
707 
708 static struct intc_sense_reg sense_registers[] __initdata = {
709  { 0xa414001c, 16, 2, /* ICR1 */
710  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
711 };
712 
713 static struct intc_mask_reg ack_registers[] __initdata = {
714  { 0xa4140024, 0, 8, /* INTREQ00 */
715  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
716 };
717 
718 static struct intc_desc intc_desc __initdata = {
719  .name = "sh7722",
720  .force_enable = ENABLED,
721  .force_disable = DISABLED,
722  .hw = INTC_HW_DESC(vectors, groups, mask_registers,
723  prio_registers, sense_registers, ack_registers),
724 };
725 
726 void __init plat_irq_setup(void)
727 {
728  register_intc_controller(&intc_desc);
729 }
730 
731 void __init plat_mem_setup(void)
732 {
733  /* Register the URAM space as Node 1 */
734  setup_bootmem_node(1, 0x055f0000, 0x05610000);
735 }
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