Linux Kernel
3.7.1
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#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/pm_qos.h>
Go to the source code of this file.
Data Structures | |
struct | sh_flctl |
struct | sh_flctl_platform_data |
Macros | |
#define | FLCMNCR(f) (f->reg + 0x0) |
#define | FLCMDCR(f) (f->reg + 0x4) |
#define | FLCMCDR(f) (f->reg + 0x8) |
#define | FLADR(f) (f->reg + 0xC) |
#define | FLADR2(f) (f->reg + 0x3C) |
#define | FLDATAR(f) (f->reg + 0x10) |
#define | FLDTCNTR(f) (f->reg + 0x14) |
#define | FLINTDMACR(f) (f->reg + 0x18) |
#define | FLBSYTMR(f) (f->reg + 0x1C) |
#define | FLBSYCNT(f) (f->reg + 0x20) |
#define | FLDTFIFO(f) (f->reg + 0x24) |
#define | FLECFIFO(f) (f->reg + 0x28) |
#define | FLTRCR(f) (f->reg + 0x2C) |
#define | FLHOLDCR(f) (f->reg + 0x38) |
#define | FL4ECCRESULT0(f) (f->reg + 0x80) |
#define | FL4ECCRESULT1(f) (f->reg + 0x84) |
#define | FL4ECCRESULT2(f) (f->reg + 0x88) |
#define | FL4ECCRESULT3(f) (f->reg + 0x8C) |
#define | FL4ECCCR(f) (f->reg + 0x90) |
#define | FL4ECCCNT(f) (f->reg + 0x94) |
#define | FLERRADR(f) (f->reg + 0x98) |
#define | _4ECCCNTEN (0x1 << 24) |
#define | _4ECCEN (0x1 << 23) |
#define | _4ECCCORRECT (0x1 << 22) |
#define | SHBUSSEL (0x1 << 20) |
#define | SEL_16BIT (0x1 << 19) |
#define | SNAND_E (0x1 << 18) /* SNAND (0=512 1=2048)*/ |
#define | QTSEL_E (0x1 << 17) |
#define | ENDIAN (0x1 << 16) /* 1 = little endian */ |
#define | FCKSEL_E (0x1 << 15) |
#define | ACM_SACCES_MODE (0x01 << 10) |
#define | NANWF_E (0x1 << 9) |
#define | SE_D (0x1 << 8) /* Spare area disable */ |
#define | CE1_ENABLE (0x1 << 4) /* Chip Enable 1 */ |
#define | CE0_ENABLE (0x1 << 3) /* Chip Enable 0 */ |
#define | TYPESEL_SET (0x1 << 0) |
#define | PULSE3 (0x1 << 27) |
#define | PULSE2 (0x1 << 17) |
#define | PULSE1 (0x1 << 15) |
#define | PULSE0 (0x1 << 9) |
#define | CLK_8B_0_5 PULSE1 |
#define | CLK_8B_1 0x0 |
#define | CLK_8B_1_5 (PULSE1 | PULSE2) |
#define | CLK_8B_2 PULSE0 |
#define | CLK_8B_3 (PULSE0 | PULSE1 | PULSE2) |
#define | CLK_8B_4 (PULSE0 | PULSE2) |
#define | CLK_16B_6L_2H PULSE0 |
#define | CLK_16B_9L_3H (PULSE0 | PULSE1 | PULSE2) |
#define | CLK_16B_12L_4H (PULSE0 | PULSE2) |
#define | ADRCNT2_E (0x1 << 31) /* 5byte address enable */ |
#define | ADRMD_E (0x1 << 26) /* Sector address access */ |
#define | CDSRC_E (0x1 << 25) /* Data buffer selection */ |
#define | DOSR_E (0x1 << 24) /* Status read check */ |
#define | SELRW (0x1 << 21) /* 0:read 1:write */ |
#define | DOADR_E (0x1 << 20) /* Address stage execute */ |
#define | ADRCNT_1 (0x00 << 18) /* Address data bytes: 1byte */ |
#define | ADRCNT_2 (0x01 << 18) /* Address data bytes: 2byte */ |
#define | ADRCNT_3 (0x02 << 18) /* Address data bytes: 3byte */ |
#define | ADRCNT_4 (0x03 << 18) /* Address data bytes: 4byte */ |
#define | DOCMD2_E (0x1 << 17) /* 2nd cmd stage execute */ |
#define | DOCMD1_E (0x1 << 16) /* 1st cmd stage execute */ |
#define | ESTERINTE (0x1 << 24) /* ECC error interrupt enable */ |
#define | AC1CLR (0x1 << 19) /* ECC FIFO clear */ |
#define | AC0CLR (0x1 << 18) /* Data FIFO clear */ |
#define | ECERB (0x1 << 9) /* ECC error */ |
#define | STERB (0x1 << 8) /* Status error */ |
#define | STERINTE (0x1 << 4) /* Status error enable */ |
#define | TRSTRT (0x1 << 0) /* translation start */ |
#define | TREND (0x1 << 1) /* translation end */ |
#define | HOLDEN (0x1 << 0) |
#define | _4ECCFA (0x1 << 2) /* 4 symbols correct fault */ |
#define | _4ECCEND (0x1 << 1) /* 4 symbols end */ |
#define | _4ECCEXST (0x1 << 0) /* 4 symbols exist */ |
#define | LOOP_TIMEOUT_MAX 0x00010000 |
Enumerations | |
enum | flctl_ecc_res_t { FL_SUCCESS, FL_REPAIRABLE, FL_ERROR, FL_TIMEOUT } |
#define _4ECCCNTEN (0x1 << 24) |
Definition at line 52 of file sh_flctl.h.
#define _4ECCCORRECT (0x1 << 22) |
Definition at line 54 of file sh_flctl.h.
#define _4ECCEN (0x1 << 23) |
Definition at line 53 of file sh_flctl.h.
#define _4ECCEND (0x1 << 1) /* 4 symbols end */ |
Definition at line 129 of file sh_flctl.h.
#define _4ECCEXST (0x1 << 0) /* 4 symbols exist */ |
Definition at line 130 of file sh_flctl.h.
#define _4ECCFA (0x1 << 2) /* 4 symbols correct fault */ |
Definition at line 128 of file sh_flctl.h.
#define AC0CLR (0x1 << 18) /* Data FIFO clear */ |
Definition at line 109 of file sh_flctl.h.
#define AC1CLR (0x1 << 19) /* ECC FIFO clear */ |
Definition at line 108 of file sh_flctl.h.
#define ACM_SACCES_MODE (0x01 << 10) |
Definition at line 61 of file sh_flctl.h.
#define ADRCNT2_E (0x1 << 31) /* 5byte address enable */ |
Definition at line 93 of file sh_flctl.h.
#define ADRCNT_1 (0x00 << 18) /* Address data bytes: 1byte */ |
Definition at line 99 of file sh_flctl.h.
#define ADRCNT_2 (0x01 << 18) /* Address data bytes: 2byte */ |
Definition at line 100 of file sh_flctl.h.
#define ADRCNT_3 (0x02 << 18) /* Address data bytes: 3byte */ |
Definition at line 101 of file sh_flctl.h.
#define ADRCNT_4 (0x03 << 18) /* Address data bytes: 4byte */ |
Definition at line 102 of file sh_flctl.h.
#define ADRMD_E (0x1 << 26) /* Sector address access */ |
Definition at line 94 of file sh_flctl.h.
#define CDSRC_E (0x1 << 25) /* Data buffer selection */ |
Definition at line 95 of file sh_flctl.h.
#define CE0_ENABLE (0x1 << 3) /* Chip Enable 0 */ |
Definition at line 65 of file sh_flctl.h.
#define CE1_ENABLE (0x1 << 4) /* Chip Enable 1 */ |
Definition at line 64 of file sh_flctl.h.
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#define CLK_16B_6L_2H PULSE0 |
Definition at line 88 of file sh_flctl.h.
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#define CLK_8B_0_5 PULSE1 |
Definition at line 82 of file sh_flctl.h.
#define CLK_8B_1 0x0 |
Definition at line 83 of file sh_flctl.h.
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#define CLK_8B_2 PULSE0 |
Definition at line 85 of file sh_flctl.h.
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#define DOADR_E (0x1 << 20) /* Address stage execute */ |
Definition at line 98 of file sh_flctl.h.
#define DOCMD1_E (0x1 << 16) /* 1st cmd stage execute */ |
Definition at line 104 of file sh_flctl.h.
#define DOCMD2_E (0x1 << 17) /* 2nd cmd stage execute */ |
Definition at line 103 of file sh_flctl.h.
#define DOSR_E (0x1 << 24) /* Status read check */ |
Definition at line 96 of file sh_flctl.h.
#define ECERB (0x1 << 9) /* ECC error */ |
Definition at line 110 of file sh_flctl.h.
#define ENDIAN (0x1 << 16) /* 1 = little endian */ |
Definition at line 59 of file sh_flctl.h.
#define ESTERINTE (0x1 << 24) /* ECC error interrupt enable */ |
Definition at line 107 of file sh_flctl.h.
#define FCKSEL_E (0x1 << 15) |
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#define HOLDEN (0x1 << 0) |
Definition at line 125 of file sh_flctl.h.
#define LOOP_TIMEOUT_MAX 0x00010000 |
Definition at line 132 of file sh_flctl.h.
#define NANWF_E (0x1 << 9) |
Definition at line 62 of file sh_flctl.h.
#define PULSE0 (0x1 << 9) |
Definition at line 81 of file sh_flctl.h.
#define PULSE1 (0x1 << 15) |
Definition at line 80 of file sh_flctl.h.
#define PULSE2 (0x1 << 17) |
Definition at line 79 of file sh_flctl.h.
#define PULSE3 (0x1 << 27) |
Definition at line 78 of file sh_flctl.h.
#define QTSEL_E (0x1 << 17) |
Definition at line 58 of file sh_flctl.h.
#define SE_D (0x1 << 8) /* Spare area disable */ |
Definition at line 63 of file sh_flctl.h.
#define SEL_16BIT (0x1 << 19) |
Definition at line 56 of file sh_flctl.h.
#define SELRW (0x1 << 21) /* 0:read 1:write */ |
Definition at line 97 of file sh_flctl.h.
#define SHBUSSEL (0x1 << 20) |
Definition at line 55 of file sh_flctl.h.
#define SNAND_E (0x1 << 18) /* SNAND (0=512 1=2048)*/ |
Definition at line 57 of file sh_flctl.h.
#define STERB (0x1 << 8) /* Status error */ |
Definition at line 111 of file sh_flctl.h.
#define STERINTE (0x1 << 4) /* Status error enable */ |
Definition at line 112 of file sh_flctl.h.
#define TREND (0x1 << 1) /* translation end */ |
Definition at line 116 of file sh_flctl.h.
#define TRSTRT (0x1 << 0) /* translation start */ |
Definition at line 115 of file sh_flctl.h.
#define TYPESEL_SET (0x1 << 0) |
Definition at line 66 of file sh_flctl.h.
enum flctl_ecc_res_t |
Definition at line 134 of file sh_flctl.h.