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| #define | MAX_TRANS (0x0fff) |
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| #define | MST_8259 (0x20) |
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| #define | SLV_8259 (0xA0) |
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| #define | TPS (18) /* ticks per second */ |
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| #define | TN (4) /* number of supported timer = TN+1 */ |
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| #define | SNPPND_TIME (5) /* buffer memory access over mem. data reg. */ |
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| #define | MAC_AD 0x405a0000 |
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| #define | MODR1 FM_A(FM_MDREG1) /* mode register 1 */ |
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| #define | MODR2 FM_A(FM_MDREG2) /* mode register 2 */ |
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| #define | CMDR1 FM_A(FM_CMDREG1) /* command register 1 */ |
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| #define | CMDR2 FM_A(FM_CMDREG2) /* command register 2 */ |
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| #define | CLEAR(io, mask) outpw((io),inpw(io)&(~(mask))) |
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| #define | SET(io, mask) outpw((io),inpw(io)|(mask)) |
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| #define | GET(io, mask) (inpw(io)&(mask)) |
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| #define | SETMASK(io, val, mask) outpw((io),(inpw(io) & ~(mask)) | (val)) |
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| #define | PLC(np, reg) (((np) == PA) ? P2_A(reg) : P1_A(reg)) |
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| #define | MARW(ma) outpw(FM_A(FM_MARW),(unsigned int)(ma)) |
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| #define | MARR(ma) outpw(FM_A(FM_MARR),(unsigned int)(ma)) |
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| #define | MDRW(dd) |
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| #define | MDRR() (((long)inpw(FM_A(FM_MDRU))<<16) + inpw(FM_A(FM_MDRL))) |
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| #define | GET_ST1() (((long)inpw(FM_A(FM_ST1U))<<16) + inpw(FM_A(FM_ST1L))) |
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| #define | GET_ST2() (((long)inpw(FM_A(FM_ST2U))<<16) + inpw(FM_A(FM_ST2L))) |
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| #define | OUT_82c54_TIMER(port, val) outpw(TI_A(port),(val)<<8) |
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| #define | IN_82c54_TIMER(port) ((inpw(TI_A(port))>>8) & 0xff) |
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| #define | DB_MAC(mac, st) |
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| #define | DB_PLC(p, iev) |
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| #define | DB_TIMER() |
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| #define | INC_PTR(sp, cp, ep) if (++cp == ep) cp = sp |
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| #define | COUNT(t) ((t)<<6) /* counter */ |
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| #define | RW_OP(o) ((o)<<4) /* read/write operation */ |
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| #define | TMODE(m) ((m)<<1) /* timer mode */ |
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| #define DB_MAC |
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mac, |
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st |
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) |
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| #define DB_PLC |
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p, |
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iev |
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) |
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| #define IN_82c54_TIMER |
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port | ) |
((inpw(TI_A(port))>>8) & 0xff) |
| #define MAC_AD 0x405a0000 |
| #define MAX_TRANS (0x0fff) |
| #define PLC |
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np, |
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reg |
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| (((np) == PA) ? P2_A(reg) : P1_A(reg)) |