supern_2.h File Reference

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Data Structures
union	rx_descr
union	tx_descr
union	tx_pointer
struct	tx_pointer::t
struct	tx_queue

Macros
#define	MB   0xff
#define	MW   0xffff
#define	MD   0xffffffff
#define	FS_EI   (1<<2)
#define	FS_AI   (1<<1)
#define	FS_CI   (1<<0)
#define	FS_MSVALID   (1<<15) /* end of queue */
#define	FS_MSRABT   (1<<14) /* frame was aborted during reception*/
#define	FS_SSRCRTG   (1<<12) /* if SA has set MSB (source-routing)*/
#define	FS_SEAC2   (FS_EI<<9) /* error indicator */
#define	FS_SEAC1   (FS_AI<<9) /* address indicator */
#define	FS_SEAC0   (FS_CI<<9) /* copy indicator */
#define	FS_SFRMERR   (1<<8) /* error detected (CRC or length) */
#define	FS_SADRRG   (1<<7) /* address recognized */
#define	FS_SFRMTY2   (1<<6) /* frame-class bit */
#define	FS_SFRMTY1   (1<<5) /* frame-type bit (impementor) */
#define	FS_SFRMTY0   (1<<4) /* frame-type bit (LLC) */
#define	FS_ERFBB1   (1<<1) /* byte offset (depends on LSB bit) */
#define	FS_ERFBB0   (1<<0) /* - " - */
#define	FRM_SMT   (0) /* asynchr. frames */
#define	FRM_LLCA   (1)
#define	FRM_IMPA   (2)
#define	FRM_MAC   (4) /* synchr. frames */
#define	FRM_LLCS   (5)
#define	FRM_IMPS   (6)
#define	RX_MSVALID   ((long)1<<31) /* memory status valid */
#define	RX_MSRABT   ((long)1<<30) /* memory status receive abort */
#define	RX_FS_E   ((long)FS_SEAC2<<16) /* error indicator */
#define	RX_FS_A   ((long)FS_SEAC1<<16) /* address indicator */
#define	RX_FS_C   ((long)FS_SEAC0<<16) /* copy indicator */
#define	RX_FS_CRC   ((long)FS_SFRMERR<<16)/* error detected */
#define	RX_FS_ADDRESS   ((long)FS_SADRRG<<16) /* address recognized */
#define	RX_FS_MAC   ((long)FS_SFRMTY2<<16)/* MAC frame */
#define	RX_FS_SMT   ((long)0<<16) /* SMT frame */
#define	RX_FS_IMPL   ((long)FS_SFRMTY1<<16)/* implementer frame */
#define	RX_FS_LLC   ((long)FS_SFRMTY0<<16)/* LLC frame */
#define	RD_S_ERFBB   0x00030000L /* received frame byte boundary */
#define	RD_S_RES2   0x000c0000L /* reserved */
#define	RD_S_SFRMTY   0x00700000L /* frame type bits */
#define	RD_S_SADRRG   0x00800000L /* DA == MA or broad-/multicast */
#define	RD_S_SFRMERR   0x01000000L /* received frame not valid */
#define	RD_S_SEAC   0x0e000000L /* frame status indicators */
#define	RD_S_SEAC0   0x02000000L /* frame-copied case-indicator */
#define	RD_S_SEAC1   0x04000000L /* address-match A-indicator */
#define	RD_S_SEAC2   0x08000000L /* frame-error E-indicator */
#define	RD_S_SSRCRTG   0x10000000L /* == 1 SA has MSB set */
#define	RD_S_RES1   0x20000000L /* reserved */
#define	RD_S_MSRABT   0x40000000L /* memory status receive abort */
#define	RD_S_MSVALID   0x80000000L /* memory status valid */
#define	RD_STATUS   0xffff0000L
#define	RD_LENGTH   0x0000ffffL
#define	RD_FRM_SMT   (unsigned long)(0<<20) /* asynchr. frames */
#define	RD_FRM_LLCA   (unsigned long)(1<<20)
#define	RD_FRM_IMPA   (unsigned long)(2<<20)
#define	RD_FRM_MAC   (unsigned long)(4<<20) /* synchr. frames */
#define	RD_FRM_LLCS   (unsigned long)(5<<20)
#define	RD_FRM_IMPS   (unsigned long)(6<<20)
#define	TX_DESCRIPTOR   0x40000000L
#define	TX_OFFSET_3   0x18000000L
#define	TXP1   2
#define	TD_C_MORE   0x80000000L /* more frame in chain */
#define	TD_C_DESCR   0x60000000L /* must be TXP1 */
#define	TD_C_TXFBB   0x18000000L /* byte offset */
#define	TD_C_XDONE   0x04000000L /* give up token */
#define	TD_C_NFCS   0x02000000L /* no frame check sequence */
#define	TD_C_XMTABT   0x01000000L /* transmit abort */
#define	TD_C_LNCNU   0x0000ff00L
#define	TD_C_LNCNL   0x000000ffL
#define	TD_C_LNCN   0x0000ffffL /* frame length lower/upper byte */
#define	TD_P_CNTRL   0xff000000L
#define	TD_P_RPXU   0x0000ff00L
#define	TD_P_RPXL   0x000000ffL
#define	TD_P_RPX   0x0000ffffL
#define	TX_PATTERN   0xa0
#define	TX_POINTER_END   0xa0000000L
#define	TX_INT_PATTERN   0xa0000000L
#define	FM_CMDREG1   0x00 /* write command reg 1 instruction */
#define	FM_CMDREG2   0x01 /* write command reg 2 instruction */
#define	FM_ST1U   0x00 /* read upper 16-bit of status reg 1 */
#define	FM_ST1L   0x01 /* read lower 16-bit of status reg 1 */
#define	FM_ST2U   0x02 /* read upper 16-bit of status reg 2 */
#define	FM_ST2L   0x03 /* read lower 16-bit of status reg 2 */
#define	FM_IMSK1U   0x04 /* r/w upper 16-bit of IMSK 1 */
#define	FM_IMSK1L   0x05 /* r/w lower 16-bit of IMSK 1 */
#define	FM_IMSK2U   0x06 /* r/w upper 16-bit of IMSK 2 */
#define	FM_IMSK2L   0x07 /* r/w lower 16-bit of IMSK 2 */
#define	FM_SAID   0x08 /* r/w short addr.-individual */
#define	FM_LAIM   0x09 /* r/w long addr.-ind. (MSW of LAID) */
#define	FM_LAIC   0x0a /* r/w long addr.-ind. (middle)*/
#define	FM_LAIL   0x0b /* r/w long addr.-ind. (LSW) */
#define	FM_SAGP   0x0c /* r/w short address-group */
#define	FM_LAGM   0x0d /* r/w long addr.-gr. (MSW of LAGP) */
#define	FM_LAGC   0x0e /* r/w long addr.-gr. (middle) */
#define	FM_LAGL   0x0f /* r/w long addr.-gr. (LSW) */
#define	FM_MDREG1   0x10 /* r/w 16-bit mode reg 1 */
#define	FM_STMCHN   0x11 /* read state-machine reg */
#define	FM_MIR1   0x12 /* read upper 16-bit of MAC Info Reg */
#define	FM_MIR0   0x13 /* read lower 16-bit of MAC Info Reg */
#define	FM_TMAX   0x14 /* r/w 16-bit TMAX reg */
#define	FM_TVX
#define	FM_TRT   0x16 /* r/w upper 16-bit of TRT timer */
#define	FM_THT   0x17 /* r/w upper 16-bit of THT timer */
#define	FM_TNEG   0x18 /* read upper 16-bit of TNEG (TTRT) */
#define	FM_TMRS   0x19 /* read lower 5-bit of TNEG,TRT,THT */
#define	FM_TREQ0   0x1a /* r/w 16-bit TREQ0 reg (LSW of TRT) */
#define	FM_TREQ1   0x1b /* r/w 16-bit TREQ1 reg (MSW of TRT) */
#define	FM_PRI0   0x1c /* r/w priority r. for asyn.-queue 0 */
#define	FM_PRI1   0x1d /* r/w priority r. for asyn.-queue 1 */
#define	FM_PRI2   0x1e /* r/w priority r. for asyn.-queue 2 */
#define	FM_TSYNC   0x1f /* r/w 16-bit of the TSYNC register */
#define	FM_MDREG2   0x20 /* r/w 16-bit mode reg 2 */
#define	FM_FRMTHR   0x21 /* r/w the frame threshold register */
#define	FM_EACB   0x22 /* r/w end addr of claim/beacon area */
#define	FM_EARV   0x23 /* r/w end addr of receive queue */
#define	FM_EARV1   FM_EARV
#define	FM_EAS   0x24 /* r/w end addr of synchr. queue */
#define	FM_EAA0   0x25 /* r/w end addr of asyn. queue 0 */
#define	FM_EAA1   0x26 /* r/w end addr of asyn. queue 1 */
#define	FM_EAA2   0x27 /* r/w end addr of asyn. queue 2 */
#define	FM_SACL   0x28 /* r/w start addr of claim frame */
#define	FM_SABC   0x29 /* r/w start addr of beacon frame */
#define	FM_WPXSF   0x2a /* r/w the write ptr. for special fr.*/
#define	FM_RPXSF   0x2b /* r/w the read ptr. for special fr. */
#define	FM_RPR   0x2d /* r/w the read ptr. for receive qu. */
#define	FM_WPR   0x2e /* r/w the write ptr. for receive qu.*/
#define	FM_SWPR   0x2f /* r/w the shadow wr.-ptr. for rec.q.*/
#define	FM_RPR1   FM_RPR
#define	FM_WPR1   FM_WPR
#define	FM_SWPR1   FM_SWPR
#define	FM_WPXS   0x30 /* r/w the write ptr. for synchr. qu.*/
#define	FM_WPXA0   0x31 /* r/w the write ptr. for asyn. qu.0 */
#define	FM_WPXA1   0x32 /* r/w the write ptr. for asyn. qu.1 */
#define	FM_WPXA2   0x33 /* r/w the write ptr. for asyn. qu.2 */
#define	FM_SWPXS   0x34 /* r/w the shadow wr.-ptr. for syn.q.*/
#define	FM_SWPXA0   0x35 /* r/w the shad. wr.-ptr. for asyn.q0*/
#define	FM_SWPXA1   0x36 /* r/w the shad. wr.-ptr. for asyn.q1*/
#define	FM_SWPXA2   0x37 /* r/w the shad. wr.-ptr. for asyn.q2*/
#define	FM_RPXS   0x38 /* r/w the read ptr. for synchr. qu. */
#define	FM_RPXA0   0x39 /* r/w the read ptr. for asyn. qu. 0 */
#define	FM_RPXA1   0x3a /* r/w the read ptr. for asyn. qu. 1 */
#define	FM_RPXA2   0x3b /* r/w the read ptr. for asyn. qu. 2 */
#define	FM_MARR   0x3c /* r/w the memory read addr register */
#define	FM_MARW   0x3d /* r/w the memory write addr register*/
#define	FM_MDRU   0x3e /* r/w upper 16-bit of mem. data reg */
#define	FM_MDRL   0x3f /* r/w lower 16-bit of mem. data reg */
#define	FM_TMSYNC   0x40 /* r/w upper 16 bits of TMSYNC timer */
#define	FM_FCNTR   0x41 /* r/w the 16-bit frame counter */
#define	FM_LCNTR   0x42 /* r/w the 16-bit lost counter */
#define	FM_ECNTR   0x43 /* r/w the 16-bit error counter */
#define	FM_FSCNTR   0x44 /* r/? Frame Strip Counter */
#define	FM_FRSELREG   0x45 /* r/w Frame Selection Register */
#define	FM_MDREG3   0x60 /* r/w Mode Register 3 */
#define	FM_ST3U   0x61 /* read upper 16-bit of status reg 3 */
#define	FM_ST3L   0x62 /* read lower 16-bit of status reg 3 */
#define	FM_IMSK3U   0x63 /* r/w upper 16-bit of IMSK reg 3 */
#define	FM_IMSK3L   0x64 /* r/w lower 16-bit of IMSK reg 3 */
#define	FM_IVR   0x65 /* read Interrupt Vector register */
#define	FM_IMR   0x66 /* r/w Interrupt mask register */
#define	FM_RPR2   0x68 /* r/w the read ptr. for rec. qu. 2 */
#define	FM_WPR2   0x69 /* r/w the write ptr. for rec. qu. 2 */
#define	FM_SWPR2   0x6a /* r/w the shadow wptr. for rec. q. 2 */
#define	FM_EARV2   0x6b /* r/w end addr of rec. qu. 2 */
#define	FM_UNLCKDLY   0x6c /* r/w Auto Unlock Delay register */
#define	FM_LTDPA1   0x79 /* r/w Last Trans desc ptr for A1 qu. */
#define	FM_AFCMD   0xb0 /* r/w Address Filter Command Reg */
#define	FM_AFSTAT   0xb2 /* r/w Address Filter Status Reg */
#define	FM_AFBIST   0xb4 /* r/w Address Filter BIST signature */
#define	FM_AFCOMP2   0xb6 /* r/w Address Filter Comparand 2 */
#define	FM_AFCOMP1   0xb8 /* r/w Address Filter Comparand 1 */
#define	FM_AFCOMP0   0xba /* r/w Address Filter Comparand 0 */
#define	FM_AFMASK2   0xbc /* r/w Address Filter Mask 2 */
#define	FM_AFMASK1   0xbe /* r/w Address Filter Mask 1 */
#define	FM_AFMASK0   0xc0 /* r/w Address Filter Mask 0 */
#define	FM_AFPERS   0xc2 /* r/w Address Filter Personality Reg */
#define	FM_ORBIST   0xd0 /* r/w Orion BIST signature */
#define	FM_ORSTAT   0xd2 /* r/w Orion Status Register */
#define	FM_RES0   0x0001 /* reserved */
#define	FM_XMTINH_HOLD   0x0002 /* transmit-inhibit/hold bit */
#define	FM_HOFLXI   0x0003 /* SN3: Hold / Flush / Inhibit */
#define	FM_FULL_HALF   0x0004 /* full-duplex/half-duplex bit */
#define	FM_LOCKTX   0x0008 /* lock-transmit-asynchr.-queues bit */
#define	FM_EXGPA0   0x0010 /* extended-group-addressing bit 0 */
#define	FM_EXGPA1   0x0020 /* extended-group-addressing bit 1 */
#define	FM_DISCRY   0x0040 /* disable-carry bit */
#define	FM_SELRA   0x0080 /* select input from PHY (1=RA,0=RB) */
#define	FM_ADDET   0x0700 /* address detection */
#define	FM_MDAMA   (0<<8) /* address detection : DA = MA */
#define	FM_MDASAMA   (1<<8) /* address detection : DA=MA||SA=MA */
#define	FM_MRNNSAFNMA   (2<<8) /* rec. non-NSA frames DA=MA&&SA!=MA */
#define	FM_MRNNSAF   (3<<8) /* rec. non-NSA frames DA = MA */
#define	FM_MDISRCV   (4<<8) /* disable receive function */
#define	FM_MRES0   (5<<8) /* reserve */
#define	FM_MLIMPROM   (6<<8) /* limited-promiscuous mode */
#define	FM_MPROMISCOUS   (7<<8) /* address detection : promiscuous */
#define	FM_SELSA   0x0800 /* select-short-address bit */
#define	FM_MMODE   0x7000 /* mode select */
#define	FM_MINIT   (0<<12) /* initialize */
#define	FM_MMEMACT   (1<<12) /* memory activate */
#define	FM_MONLINESP   (2<<12) /* on-line special */
#define	FM_MONLINE   (3<<12) /* on-line (FDDI operational mode) */
#define	FM_MILOOP   (4<<12) /* internal loopback */
#define	FM_MRES1   (5<<12) /* reserved */
#define	FM_MRES2   (6<<12) /* reserved */
#define	FM_MELOOP   (7<<12) /* external loopback */
#define	FM_SNGLFRM   0x8000 /* single-frame-receive mode */
#define	MDR1INIT   (FM_MINIT | FM_MDAMA)
#define	FM_AFULL   0x000f /* 4-bit value (empty loc.in txqueue)*/
#define	FM_RCVERR   0x0010 /* rec.-errored-frames bit */
#define	FM_SYMCTL   0x0020 /* sysmbol-control bit */
#define	FM_SYNPRQ   0x0040 /* synchron.-NP-DMA-request bit */
#define	FM_ENNPRQ   0x0080 /* enable-NP-DMA-request bit */
#define	FM_ENHSRQ   0x0100 /* enable-host-request bit */
#define	FM_RXFBB01   0x0600 /* rec. frame byte boundary bit0 & 1 */
#define	FM_LSB   0x0800 /* determ. ordering of bytes in buffer*/
#define	FM_PARITY   0x1000 /* 1 = even, 0 = odd */
#define	FM_CHKPAR   0x2000 /* 1 = parity of 32-bit buffer BD-bus*/
#define	FM_STRPFCS   0x4000 /* 1 = strips FCS field of rec.frame */
#define	FM_BMMODE   0x8000 /* Buffer-Memory-Mode (1 = tag mode) */
#define	FM_STEFRMS   0x0001 /* transmit end of frame: synchr. qu.*/
#define	FM_STEFRMA0   0x0002 /* transmit end of frame: asyn. qu.0 */
#define	FM_STEFRMA1   0x0004 /* transmit end of frame: asyn. qu.1 */
#define	FM_STEFRMA2   0x0008 /* transmit end of frame: asyn. qu.2 */
#define	FM_STECFRMS   0x0010 /* transmit end of chain of syn. qu. */
#define	FM_STECFRMA0   0x0020 /* transmit end of chain of asyn. q0 */
#define	FM_STECFRMA1   0x0040 /* transmit end of chain of asyn. q1 */
#define	FM_STECMDA1   0x0040 /* SN3: 'no description' */
#define	FM_STECFRMA2   0x0080 /* transmit end of chain of asyn. q2 */
#define	FM_STEXDONS   0x0100 /* transmit until XDONE in syn. qu. */
#define	FM_STBFLA   0x0200 /* asynchr.-queue trans. buffer full */
#define	FM_STBFLS   0x0400 /* synchr.-queue transm. buffer full */
#define	FM_STXABRS   0x0800 /* synchr. queue transmit-abort */
#define	FM_STXABRA0   0x1000 /* asynchr. queue 0 transmit-abort */
#define	FM_STXABRA1   0x2000 /* asynchr. queue 1 transmit-abort */
#define	FM_STXABRA2   0x4000 /* asynchr. queue 2 transmit-abort */
#define	FM_SXMTABT   0x8000 /* transmit abort */
#define	FM_SQLCKS   0x0001 /* queue lock for synchr. queue */
#define	FM_SQLCKA0   0x0002 /* queue lock for asynchr. queue 0 */
#define	FM_SQLCKA1   0x0004 /* queue lock for asynchr. queue 1 */
#define	FM_SQLCKA2   0x0008 /* queue lock for asynchr. queue 2 */
#define	FM_STXINFLS   0x0010 /* transmit instruction full: syn. */
#define	FM_STXINFLA0   0x0020 /* transmit instruction full: asyn.0 */
#define	FM_STXINFLA1   0x0040 /* transmit instruction full: asyn.1 */
#define	FM_STXINFLA2   0x0080 /* transmit instruction full: asyn.2 */
#define	FM_SPCEPDS   0x0100 /* parity/coding error: syn. queue */
#define	FM_SPCEPDA0   0x0200 /* parity/coding error: asyn. queue0 */
#define	FM_SPCEPDA1   0x0400 /* parity/coding error: asyn. queue1 */
#define	FM_SPCEPDA2   0x0800 /* parity/coding error: asyn. queue2 */
#define	FM_STBURS   0x1000 /* transmit buffer underrun: syn. q. */
#define	FM_STBURA0   0x2000 /* transmit buffer underrun: asyn.0 */
#define	FM_STBURA1   0x4000 /* transmit buffer underrun: asyn.1 */
#define	FM_STBURA2   0x8000 /* transmit buffer underrun: asyn.2 */
#define	FM_SOTRBEC   0x0001 /* other beacon received */
#define	FM_SMYBEC   0x0002 /* my beacon received */
#define	FM_SBEC   0x0004 /* beacon state entered */
#define	FM_SLOCLM   0x0008 /* low claim received */
#define	FM_SHICLM   0x0010 /* high claim received */
#define	FM_SMYCLM   0x0020 /* my claim received */
#define	FM_SCLM   0x0040 /* claim state entered */
#define	FM_SERRSF   0x0080 /* error in special frame */
#define	FM_SNFSLD   0x0100 /* NP and FORMAC+ simultaneous load */
#define	FM_SRFRCTOV   0x0200 /* receive frame counter overflow */
#define	FM_SRCVFRM   0x0400 /* receive frame */
#define	FM_SRCVOVR   0x0800 /* receive FIFO overflow */
#define	FM_SRBFL   0x1000 /* receive buffer full */
#define	FM_SRABT   0x2000 /* receive abort */
#define	FM_SRBMT   0x4000 /* receive buffer empty */
#define	FM_SRCOMP   0x8000 /* receive complete. Nontag mode */
#define	FM_SRES0   0x0001 /* reserved */
#define	FM_SESTRIPTK   0x0001 /* SN3: 'no description' */
#define	FM_STRTEXR   0x0002 /* TRT expired in claim | beacon st. */
#define	FM_SDUPCLM   0x0004 /* duplicate claim received */
#define	FM_SSIFG   0x0008 /* short interframe gap */
#define	FM_SFRMCTR   0x0010 /* frame counter overflow */
#define	FM_SERRCTR   0x0020 /* error counter overflow */
#define	FM_SLSTCTR   0x0040 /* lost counter overflow */
#define	FM_SPHINV   0x0080 /* PHY invalid */
#define	FM_SADET   0x0100 /* address detect */
#define	FM_SMISFRM   0x0200 /* missed frame */
#define	FM_STRTEXP   0x0400 /* TRT expired and late count > 0 */
#define	FM_STVXEXP   0x0800 /* TVX expired */
#define	FM_STKISS   0x1000 /* token issued */
#define	FM_STKERR   0x2000 /* token error */
#define	FM_SMULTDA   0x4000 /* multiple destination address */
#define	FM_SRNGOP   0x8000 /* ring operational */
#define	FM_SRQUNLCK1   0x0001 /* receive queue unlocked queue 1 */
#define	FM_SRQUNLCK2   0x0002 /* receive queue unlocked queue 2 */
#define	FM_SRPERRQ1   0x0004 /* receive parity error rx queue 1 */
#define	FM_SRPERRQ2   0x0008 /* receive parity error rx queue 2 */
#define	FM_SRCVOVR2   0x0800 /* receive FIFO overfull rx queue 2 */
#define	FM_SRBFL2   0x1000 /* receive buffer full rx queue 2 */
#define	FM_SRABT2   0x2000 /* receive abort rx queue 2 */
#define	FM_SRBMT2   0x4000 /* receive buf empty rx queue 2 */
#define	FM_SRCOMP2   0x8000 /* receive comp rx queue 2 */
#define	FM_AF_BIST_DONE   0x0001 /* Address Filter BIST is done */
#define	FM_PLC_BIST_DONE   0x0002 /* internal PLC Bist is done */
#define	FM_PDX_BIST_DONE   0x0004 /* PDX BIST is done */
#define	FM_SICAMDAMAT   0x0010 /* Status internal CAM DA match */
#define	FM_SICAMDAXACT   0x0020 /* Status internal CAM DA exact match */
#define	FM_SICAMSAMAT   0x0040 /* Status internal CAM SA match */
#define	FM_SICAMSAXACT   0x0080 /* Status internal CAM SA exact match */
#define	FM_MDRTAG   0x0004 /* tag bit of long word read */
#define	FM_SNPPND   0x0008 /* r/w from buffer mem. is pending */
#define	FM_TXSTAT   0x0070 /* transmitter state machine state */
#define	FM_RCSTAT   0x0380 /* receiver state machine state */
#define	FM_TM01   0x0c00 /* indicate token mode */
#define	FM_SIM   0x1000 /* indicate send immediate-mode */
#define	FM_REV   0xe000 /* FORMAC Plus revision number */
#define	FM_MENRS   0x0001 /* Ena enhanced rec status encoding */
#define	FM_MENXS   0x0002 /* Ena enhanced xmit status encoding */
#define	FM_MENXCT   0x0004 /* Ena EXACT/INEXACT matching */
#define	FM_MENAFULL   0x0008 /* Ena enh QCTRL encoding for AFULL */
#define	FM_MEIND   0x0030 /* Ena enh A,C indicator settings */
#define	FM_MENQCTRL   0x0040 /* Ena enh QCTRL encoding */
#define	FM_MENRQAUNLCK   0x0080 /* Ena rec q auto unlock */
#define	FM_MENDAS   0x0100 /* Ena DAS connections by cntr MUX */
#define	FM_MENPLCCST   0x0200 /* Ena Counter Segm test in PLC blck */
#define	FM_MENSGLINT   0x0400 /* Ena Vectored Interrupt reading */
#define	FM_MENDRCV   0x0800 /* Ena dual receive queue operation */
#define	FM_MENFCLOC   0x3000 /* Ena FC location within frm data */
#define	FM_MENTRCMD   0x4000 /* Ena ASYNC1 xmit only after command */
#define	FM_MENTDLPBK   0x8000 /* Ena TDAT to RDAT lkoopback */
#define	FM_RECV1   0x000f /* options for receive queue 1 */
#define	FM_RCV1_ALL   (0<<0) /* receive all frames */
#define	FM_RCV1_LLC   (1<<0) /* rec all LLC frames */
#define	FM_RCV1_SMT   (2<<0) /* rec all SMT frames */
#define	FM_RCV1_NSMT   (3<<0) /* rec non-SMT frames */
#define	FM_RCV1_IMP   (4<<0) /* rec Implementor frames */
#define	FM_RCV1_MAC   (5<<0) /* rec all MAC frames */
#define	FM_RCV1_SLLC   (6<<0) /* rec all sync LLC frames */
#define	FM_RCV1_ALLC   (7<<0) /* rec all async LLC frames */
#define	FM_RCV1_VOID   (8<<0) /* rec all void frames */
#define	FM_RCV1_ALSMT   (9<<0) /* rec all async LLC & SMT frames */
#define	FM_RECV2   0x00f0 /* options for receive queue 2 */
#define	FM_RCV2_ALL   (0<<4) /* receive all other frames */
#define	FM_RCV2_LLC   (1<<4) /* rec all LLC frames */
#define	FM_RCV2_SMT   (2<<4) /* rec all SMT frames */
#define	FM_RCV2_NSMT   (3<<4) /* rec non-SMT frames */
#define	FM_RCV2_IMP   (4<<4) /* rec Implementor frames */
#define	FM_RCV2_MAC   (5<<4) /* rec all MAC frames */
#define	FM_RCV2_SLLC   (6<<4) /* rec all sync LLC frames */
#define	FM_RCV2_ALLC   (7<<4) /* rec all async LLC frames */
#define	FM_RCV2_VOID   (8<<4) /* rec all void frames */
#define	FM_RCV2_ALSMT   (9<<4) /* rec all async LLC & SMT frames */
#define	FM_ENXMTADSWAP   0x4000 /* enh rec addr swap (phys -> can) */
#define	FM_ENRCVADSWAP   0x8000 /* enh tx addr swap (can -> phys) */
#define	FM_INST   0x0007 /* Address Filter Operation */
#define	FM_IINV_CAM   (0<<0) /* Invalidate CAM */
#define	FM_IWRITE_CAM   (1<<0) /* Write CAM */
#define	FM_IREAD_CAM   (2<<0) /* Read CAM */
#define	FM_IRUN_BIST   (3<<0) /* Run BIST */
#define	FM_IFIND   (4<<0) /* Find */
#define	FM_IINV   (5<<0) /* Invalidate */
#define	FM_ISKIP   (6<<0) /* Skip */
#define	FM_ICL_SKIP   (7<<0) /* Clear all SKIP bits */
#define	FM_REV_NO   0x00e0 /* Revision Number of Address Filter */
#define	FM_BIST_DONE   0x0100 /* BIST complete */
#define	FM_EMPTY   0x0200 /* CAM empty */
#define	FM_ERROR   0x0400 /* Error (improper operation) */
#define	FM_MULT   0x0800 /* Multiple Match */
#define	FM_EXACT   0x1000 /* Exact Match */
#define	FM_FOUND   0x2000 /* Comparand found in CAM */
#define	FM_FULL   0x4000 /* CAM full */
#define	FM_DONE   0x8000 /* DONE indicator */
#define	AF_BIST_SIGNAT   0x0553 /* Address Filter BIST Signature */
#define	FM_VALID   0x0001 /* CAM Entry Valid */
#define	FM_DA   0x0002 /* Destination Address */
#define	FM_DAX   0x0004 /* Destination Address Exact */
#define	FM_SA   0x0008 /* Source Address */
#define	FM_SAX   0x0010 /* Source Address Exact */
#define	FM_SKIP   0x0020 /* Skip this entry */
#define	FM_IRESET   0x01 /* software reset */
#define	FM_IRMEMWI   0x02 /* load Memory Data Reg., inc MARR */
#define	FM_IRMEMWO   0x03 /* load MDR from buffer memory, n.i. */
#define	FM_IIL   0x04 /* idle/listen */
#define	FM_ICL   0x05 /* claim/listen */
#define	FM_IBL   0x06 /* beacon/listen */
#define	FM_ILTVX   0x07 /* load TVX timer from TVX reg */
#define	FM_INRTM   0x08 /* nonrestricted token mode */
#define	FM_IENTM   0x09 /* enter nonrestricted token mode */
#define	FM_IERTM   0x0a /* enter restricted token mode */
#define	FM_IRTM   0x0b /* restricted token mode */
#define	FM_ISURT   0x0c /* send unrestricted token */
#define	FM_ISRT   0x0d /* send restricted token */
#define	FM_ISIM   0x0e /* enter send-immediate mode */
#define	FM_IESIM   0x0f /* exit send-immediate mode */
#define	FM_ICLLS   0x11 /* clear synchronous queue lock */
#define	FM_ICLLA0   0x12 /* clear asynchronous queue 0 lock */
#define	FM_ICLLA1   0x14 /* clear asynchronous queue 1 lock */
#define	FM_ICLLA2   0x18 /* clear asynchronous queue 2 lock */
#define	FM_ICLLR   0x20 /* clear receive queue (SN3:1) lock */
#define	FM_ICLLR2   0x21 /* SN3: clear receive queue 2 lock */
#define	FM_ITRXBUS   0x22 /* SN3: Tristate X-Bus (SAS only) */
#define	FM_IDRXBUS   0x23 /* SN3: drive X-Bus */
#define	FM_ICLLAL   0x3f /* clear all queue locks */
#define	FM_ITRS   0x01 /* transmit synchronous queue */
#define	FM_ITRA0   0x02 /* transmit asynchronous queue 0 */
#define	FM_ITRA1   0x04 /* transmit asynchronous queue 1 */
#define	FM_ITRA2   0x08 /* transmit asynchronous queue 2 */
#define	FM_IACTR   0x10 /* abort current transmit activity */
#define	FM_IRSTQ   0x20 /* reset transmit queues */
#define	FM_ISTTB   0x30 /* set tag bit */
#define	FM_IERSF   0x40 /* enable receive single frame */
#define	FM_ITR   0x50 /* SN3: Transmit Command */
#define	PL_CNTRL_A   0x00 /* control register A (r/w) */
#define	PL_CNTRL_B   0x01 /* control register B (r/w) */
#define	PL_INTR_MASK   0x02 /* interrupt mask (r/w) */
#define	PL_XMIT_VECTOR   0x03 /* transmit vector register (r/w) */
#define	PL_VECTOR_LEN   0x04 /* transmit vector length (r/w) */
#define	PL_LE_THRESHOLD   0x05 /* link error event threshold (r/w) */
#define	PL_C_MIN   0x06 /* minimum connect state time (r/w) */
#define	PL_TL_MIN   0x07 /* min. line state transmit t. (r/w) */
#define	PL_TB_MIN   0x08 /* minimum break time (r/w) */
#define	PL_T_OUT   0x09 /* signal timeout (r/w) */
#define	PL_CNTRL_C   0x0a /* control register C (r/w) */
#define	PL_LC_LENGTH   0x0b /* link confidence test time (r/w) */
#define	PL_T_SCRUB   0x0c /* scrub time = MAC TVX (r/w) */
#define	PL_NS_MAX   0x0d /* max. noise time before break (r/w)*/
#define	PL_TPC_LOAD_V   0x0e /* TPC timer load value (write only) */
#define	PL_TNE_LOAD_V   0x0f /* TNE timer load value (write only) */
#define	PL_STATUS_A   0x10 /* status register A (read only) */
#define	PL_STATUS_B   0x11 /* status register B (read only) */
#define	PL_TPC   0x12 /* timer for PCM (ro) [20.48 us] */
#define	PL_TNE   0x13 /* time of noise event [0.32 us] */
#define	PL_CLK_DIV   0x14 /* TNE clock divider (read only) */
#define	PL_BIST_SIGNAT   0x15 /* built in self test signature (ro)*/
#define	PL_RCV_VECTOR   0x16 /* receive vector reg. (read only) */
#define	PL_INTR_EVENT   0x17 /* interrupt event reg. (read only) */
#define	PL_VIOL_SYM_CTR   0x18 /* violation symbol count. (read o) */
#define	PL_MIN_IDLE_CTR   0x19 /* minimum idle counter (read only) */
#define	PL_LINK_ERR_CTR   0x1a /* link error event ctr.(read only) */
#define	PL_RUN_BIST   0x0001 /* begin running its Built In Self T.*/
#define	PL_RF_DISABLE   0x0002 /* disable the Repeat Filter state m.*/
#define	PL_SC_REM_LOOP   0x0004 /* remote loopback path */
#define	PL_SC_BYPASS   0x0008 /* by providing a physical bypass */
#define	PL_LM_LOC_LOOP   0x0010 /* loop path just after elastic buff.*/
#define	PL_EB_LOC_LOOP   0x0020 /* loop path just prior to PDT/PDR IF*/
#define	PL_FOT_OFF   0x0040 /* assertion of /FOTOFF pin of PLC */
#define	PL_LOOPBACK   0x0080 /* it cause the /LPBCK pin ass. low */
#define	PL_MINI_CTR_INT   0x0100 /* partially contr. when bit is ass. */
#define	PL_VSYM_CTR_INT   0x0200 /* controls when int bit is asserted */
#define	PL_ENA_PAR_CHK   0x0400 /* enable parity check */
#define	PL_REQ_SCRUB   0x0800 /* limited access to scrub capability*/
#define	PL_TPC_16BIT   0x1000 /* causes the TPC as a 16 bit timer */
#define	PL_TNE_16BIT   0x2000 /* causes the TNE as a 16 bit timer */
#define	PL_NOISE_TIMER   0x4000 /* allows the noise timing function */
#define	PL_PCM_CNTRL   0x0003 /* control PCM state machine */
#define	PL_PCM_NAF   (0) /* state is not affected */
#define	PL_PCM_START   (1) /* goes to the BREAK state */
#define	PL_PCM_TRACE   (2) /* goes to the TRACE state */
#define	PL_PCM_STOP   (3) /* goes to the OFF state */
#define	PL_MAINT   0x0004 /* if OFF state --> MAINT state */
#define	PL_LONG   0x0008 /* perf. a long Link Confid.Test(LCT)*/
#define	PL_PC_JOIN   0x0010 /* if NEXT state --> JOIN state */
#define	PL_PC_LOOP   0x0060 /* loopback used in the LCT */
#define	PL_NOLCT   (0<<5) /* no LCT is performed */
#define	PL_TPDR   (1<<5) /* PCM asserts transmit PDR */
#define	PL_TIDLE   (2<<5) /* PCM asserts transmit idle */
#define	PL_RLBP   (3<<5) /* trans. PDR & remote loopb. path */
#define	PL_CLASS_S   0x0080 /* signif. that single att. station */
#define	PL_MAINT_LS   0x0700 /* line state while in the MAINT st. */
#define	PL_M_QUI0   (0<<8) /* transmit QUIET line state */
#define	PL_M_IDLE   (1<<8) /* transmit IDLE line state */
#define	PL_M_HALT   (2<<8) /* transmit HALT line state */
#define	PL_M_MASTR   (3<<8) /* transmit MASTER line state */
#define	PL_M_QUI1   (4<<8) /* transmit QUIET line state */
#define	PL_M_QUI2   (5<<8) /* transmit QUIET line state */
#define	PL_M_TPDR   (6<<8) /* tr. PHY_DATA requ.-symbol is tr.ed*/
#define	PL_M_QUI3   (7<<8) /* transmit QUIET line state */
#define	PL_MATCH_LS   0x7800 /* line state to be comp. with curr.*/
#define	PL_I_ANY   (0<<11) /* Int. on any change in *_LINE_ST */
#define	PL_I_IDLE   (1<<11) /* Interrupt on IDLE line state */
#define	PL_I_HALT   (2<<11) /* Interrupt on HALT line state */
#define	PL_I_MASTR   (4<<11) /* Interrupt on MASTER line state */
#define	PL_I_QUIET   (8<<11) /* Interrupt on QUIET line state */
#define	PL_CONFIG_CNTRL   0x8000 /* control over scrub, byp. & loopb.*/
#define	PL_C_CIPHER_ENABLE   (1<<0) /* enable scrambler */
#define	PL_C_CIPHER_LPBCK   (1<<1) /* loopback scrambler */
#define	PL_C_SDOFF_ENABLE   (1<<6) /* enable SDOFF timer */
#define	PL_C_SDON_ENABLE   (1<<7) /* enable SDON timer */
#define	PL_C_FOTOFF_CTRL   (3<<8) /* FOTOFF timer control */
#define	PL_C_FOTOFF_0   (0<<8) /* timer off */
#define	PL_C_FOTOFF_30   (1<<8) /* 30uS */
#define	PL_C_FOTOFF_50   (2<<8) /* 50uS */
#define	PL_C_FOTOFF_NEVER   (3<<8) /* never */
#define	PL_C_SDON_TIMER   (3<<10) /* SDON timer control */
#define	PL_C_SDON_084   (0<<10) /* 0.84 uS */
#define	PL_C_SDON_132   (1<<10) /* 1.32 uS */
#define	PL_C_SDON_252   (2<<10) /* 2.52 uS */
#define	PL_C_SDON_512   (3<<10) /* 5.12 uS */
#define	PL_C_SOFF_TIMER   (3<<12) /* SDOFF timer control */
#define	PL_C_SOFF_076   (0<<12) /* 0.76 uS */
#define	PL_C_SOFF_132   (1<<12) /* 1.32 uS */
#define	PL_C_SOFF_252   (2<<12) /* 2.52 uS */
#define	PL_C_SOFF_512   (3<<12) /* 5.12 uS */
#define	PL_C_TSEL   (3<<14) /* scrambler path select */
#define	PLC_REV_MASK   0xf800 /* revision bits in status A */
#define	PLC_REVISION_A   0x0000 /* revision bits for PLC */
#define	PLC_REVISION_S   0xf800 /* revision bits for PLC-S */
#define	PLC_REV_SN3   0x7800 /* revision bits for PLC-S in IFCP */
#define	PL_SYM_PR_CTR   0x0007 /* contains the LSM symbol pair Ctr. */
#define	PL_UNKN_LINE_ST   0x0008 /* unknown line state bit from LSM */
#define	PL_LSM_STATE   0x0010 /* state bit of LSM */
#define	PL_LINE_ST   0x00e0 /* contains recogn. line state of LSM*/
#define	PL_L_NLS   (0<<5) /* noise line state */
#define	PL_L_ALS   (1<<5) /* activ line state */
#define	PL_L_UND   (2<<5) /* undefined */
#define	PL_L_ILS4   (3<<5) /* idle l. s. (after 4 idle symbols) */
#define	PL_L_QLS   (4<<5) /* quiet line state */
#define	PL_L_MLS   (5<<5) /* master line state */
#define	PL_L_HLS   (6<<5) /* halt line state */
#define	PL_L_ILS16   (7<<5) /* idle line state (after 16 idle s.)*/
#define	PL_PREV_LINE_ST   0x0300 /* value of previous line state */
#define	PL_P_QLS   (0<<8) /* quiet line state */
#define	PL_P_MLS   (1<<8) /* master line state */
#define	PL_P_HLS   (2<<8) /* halt line state */
#define	PL_P_ILS16   (3<<8) /* idle line state (after 16 idle s.)*/
#define	PL_SIGNAL_DET   0x0400 /* 1=that signal detect is deasserted*/
#define	PL_BREAK_REASON   0x0007 /* reason for PCM state mach.s to br.*/
#define	PL_B_NOT   (0) /* PCM SM has not gone to BREAK state*/
#define	PL_B_PCS   (1) /* PC_Start issued */
#define	PL_B_TPC   (2) /* TPC timer expired after T_OUT */
#define	PL_B_TNE   (3) /* TNE timer expired after NS_MAX */
#define	PL_B_QLS   (4) /* quit line state detected */
#define	PL_B_ILS   (5) /* idle line state detected */
#define	PL_B_HLS   (6) /* halt line state detected */
#define	PL_TCF   0x0008 /* transmit code flag (start exec.) */
#define	PL_RCF   0x0010 /* receive code flag (start exec.) */
#define	PL_LSF   0x0020 /* line state flag (l.s. has been r.)*/
#define	PL_PCM_SIGNAL   0x0040 /* indic. that XMIT_VECTOR hb.written*/
#define	PL_PCM_STATE   0x0780 /* state bits of PCM state machine */
#define	PL_PC0   (0<<7) /* OFF - when /RST or PCM_CNTRL */
#define	PL_PC1   (1<<7) /* BREAK - entry point in start PCM*/
#define	PL_PC2   (2<<7) /* TRACE - to localize stuck Beacon*/
#define	PL_PC3   (3<<7) /* CONNECT - synchronize ends of conn*/
#define	PL_PC4   (4<<7) /* NEXT - to separate the signalng*/
#define	PL_PC5   (5<<7) /* SIGNAL - PCM trans/rec. bit infos*/
#define	PL_PC6   (6<<7) /* JOIN - 1. state to activ conn. */
#define	PL_PC7   (7<<7) /* VERIFY - 2. - " - (3. ACTIVE) */
#define	PL_PC8   (8<<7) /* ACTIVE - PHY has been incorporated*/
#define	PL_PC9
#define	PL_PCI_SCRUB   0x0800 /* scrubbing function is being exec. */
#define	PL_PCI_STATE   0x3000 /* Physical Connect. Insertion SM */
#define	PL_CI_REMV   (0<<12) /* REMOVED */
#define	PL_CI_ISCR   (1<<12) /* INSERT_SCRUB */
#define	PL_CI_RSCR   (2<<12) /* REMOVE_SCRUB */
#define	PL_CI_INS   (3<<12) /* INSERTED */
#define	PL_RF_STATE   0xc000 /* state bit of repeate filter SM */
#define	PL_RF_REPT   (0<<14) /* REPEAT */
#define	PL_RF_IDLE   (1<<14) /* IDLE */
#define	PL_RF_HALT1   (2<<14) /* HALT1 */
#define	PL_RF_HALT2   (3<<14) /* HALT2 */
#define	PL_PARITY_ERR   0x0001 /* p. error h.b.detected on TX9-0 inp*/
#define	PL_LS_MATCH   0x0002 /* l.s.== l.s. PLC_CNTRL_B's MATCH_LS*/
#define	PL_PCM_CODE   0x0004 /* transmit&receive | LCT complete */
#define	PL_TRACE_PROP   0x0008 /* master l.s. while PCM ACTIV|TRACE */
#define	PL_SELF_TEST   0x0010 /* QUIET|HALT while PCM in TRACE st. */
#define	PL_PCM_BREAK   0x0020 /* PCM has entered the BREAK state */
#define	PL_PCM_ENABLED   0x0040 /* asserted SC_JOIN, scrub. & ACTIV */
#define	PL_TPC_EXPIRED   0x0080 /* TPC timer reached zero */
#define	PL_TNE_EXPIRED   0x0100 /* TNE timer reached zero */
#define	PL_EBUF_ERR   0x0200 /* elastic buff. det. over-|underflow*/
#define	PL_PHYINV   0x0400 /* physical layer invalid signal */
#define	PL_VSYM_CTR   0x0800 /* violation symbol counter has incr.*/
#define	PL_MINI_CTR   0x1000 /* dep. on PLC_CNTRL_A's MINI_CTR_INT*/
#define	PL_LE_CTR   0x2000 /* link error event counter */
#define	PL_LSDO   0x4000 /* SDO input pin changed to a 1 */
#define	PL_NP_ERR   0x8000 /* NP has requested to r/w an inv. r.*/
#define	TP_C_MIN   0xff9c /* 2 ms */
#define	TP_TL_MIN   0xfff0 /* 0.3 ms */
#define	TP_TB_MIN   0xff10 /* 5 ms */
#define	TP_T_OUT   0xd9db /* 200 ms */
#define	TP_LC_LENGTH   0xf676 /* 50 ms */
#define	TP_LC_LONGLN   0xa0a2 /* 500 ms */
#define	TP_T_SCRUB   0xff6d /* 3.5 ms */
#define	TP_NS_MAX   0xf021 /* 1.3 ms */
#define	PLC_BIST   0x6ecd /* BIST signature for PLC */
#define	PLCS_BIST   0x5b6b /* BIST signature for PLC-S */
#define	PLC_ELM_B_BIST   0x6ecd /* BIST signature of ELM Rev. B */
#define	PLC_ELM_D_BIST   0x5b6b /* BIST signature of ELM Rev. D */
#define	PLC_CAM_A_BIST   0x9e75 /* BIST signature of CAMEL Rev. A */
#define	PLC_CAM_B_BIST   0x5b6b /* BIST signature of CAMEL Rev. B */
#define	PLC_IFD_A_BIST   0x9e75 /* BIST signature of IFDDI Rev. A */
#define	PLC_IFD_B_BIST   0x5b6b /* BIST signature of IFDDI Rev. B */
#define	PLC_QELM_A_BIST   0x5b6b /* BIST signature of QELM Rev. A */
#define	RQ_NOT   0 /* not request */
#define	RQ_RES   1 /* reserved */
#define	RQ_SFW   2 /* special frame write */
#define	RQ_RRQ   3 /* read request: receive queue */
#define	RQ_WSQ   4 /* write request: synchronous queue */
#define	RQ_WA0   5 /* write requ.: asynchronous queue 0 */
#define	RQ_WA1   6 /* write requ.: asynchronous queue 1 */
#define	RQ_WA2   7 /* write requ.: asynchronous queue 2 */
#define	SZ_LONG   (sizeof(long))
#define	COMPLREF   ((u_long)32*256*256) /* two's complement 21 bit */
#define	MSTOBCLK(x)   ((u_long)(x)*12500L)
#define	MSTOTVX(x)   (((u_long)(x)*1000L)/80/255)

Macro Definition Documentation

#define AF_BIST_SIGNAT   0x0553 /* Address Filter BIST Signature */

Definition at line 643 of file supern_2.h.

#define COMPLREF   ((u_long)32*256*256) /* two's complement 21 bit */

Definition at line 1053 of file supern_2.h.

#define FM_ADDET   0x0700 /* address detection */

Definition at line 380 of file supern_2.h.

#define FM_AF_BIST_DONE   0x0001 /* Address Filter BIST is done */

Definition at line 542 of file supern_2.h.

#define FM_AFBIST   0xb4 /* r/w Address Filter BIST signature */

Definition at line 350 of file supern_2.h.

#define FM_AFCMD   0xb0 /* r/w Address Filter Command Reg */

Definition at line 348 of file supern_2.h.

#define FM_AFCOMP0   0xba /* r/w Address Filter Comparand 0 */

Definition at line 353 of file supern_2.h.

#define FM_AFCOMP1   0xb8 /* r/w Address Filter Comparand 1 */

Definition at line 352 of file supern_2.h.

#define FM_AFCOMP2   0xb6 /* r/w Address Filter Comparand 2 */

Definition at line 351 of file supern_2.h.

#define FM_AFMASK0   0xc0 /* r/w Address Filter Mask 0 */

Definition at line 356 of file supern_2.h.

#define FM_AFMASK1   0xbe /* r/w Address Filter Mask 1 */

Definition at line 355 of file supern_2.h.

#define FM_AFMASK2   0xbc /* r/w Address Filter Mask 2 */

Definition at line 354 of file supern_2.h.

#define FM_AFPERS   0xc2 /* r/w Address Filter Personality Reg */

Definition at line 357 of file supern_2.h.

#define FM_AFSTAT   0xb2 /* r/w Address Filter Status Reg */

Definition at line 349 of file supern_2.h.

#define FM_AFULL   0x000f /* 4-bit value (empty loc.in txqueue)*/

Definition at line 410 of file supern_2.h.

#define FM_BIST_DONE   0x0100 /* BIST complete */

Definition at line 630 of file supern_2.h.

#define FM_BMMODE   0x8000 /* Buffer-Memory-Mode (1 = tag mode) */

Definition at line 422 of file supern_2.h.

#define FM_CHKPAR   0x2000 /* 1 = parity of 32-bit buffer BD-bus*/

Definition at line 420 of file supern_2.h.

#define FM_CMDREG1   0x00 /* write command reg 1 instruction */

Definition at line 241 of file supern_2.h.

#define FM_CMDREG2   0x01 /* write command reg 2 instruction */

Definition at line 242 of file supern_2.h.

#define FM_DA   0x0002 /* Destination Address */

Definition at line 650 of file supern_2.h.

#define FM_DAX   0x0004 /* Destination Address Exact */

Definition at line 651 of file supern_2.h.

#define FM_DISCRY   0x0040 /* disable-carry bit */

Definition at line 376 of file supern_2.h.

#define FM_DONE   0x8000 /* DONE indicator */

Definition at line 637 of file supern_2.h.

#define FM_EAA0   0x25 /* r/w end addr of asyn. queue 0 */

Definition at line 285 of file supern_2.h.

#define FM_EAA1   0x26 /* r/w end addr of asyn. queue 1 */

Definition at line 286 of file supern_2.h.

#define FM_EAA2   0x27 /* r/w end addr of asyn. queue 2 */

Definition at line 287 of file supern_2.h.

#define FM_EACB   0x22 /* r/w end addr of claim/beacon area */

Definition at line 279 of file supern_2.h.

#define FM_EARV   0x23 /* r/w end addr of receive queue */

Definition at line 280 of file supern_2.h.

#define FM_EARV1   FM_EARV

Definition at line 282 of file supern_2.h.

#define FM_EARV2   0x6b /* r/w end addr of rec. qu. 2 */

Definition at line 339 of file supern_2.h.

#define FM_EAS   0x24 /* r/w end addr of synchr. queue */

Definition at line 284 of file supern_2.h.

#define FM_ECNTR   0x43 /* r/w the 16-bit error counter */

Definition at line 321 of file supern_2.h.

#define FM_EMPTY   0x0200 /* CAM empty */

Definition at line 631 of file supern_2.h.

#define FM_ENHSRQ   0x0100 /* enable-host-request bit */

Definition at line 416 of file supern_2.h.

#define FM_ENNPRQ   0x0080 /* enable-NP-DMA-request bit */

Definition at line 415 of file supern_2.h.

#define FM_ENRCVADSWAP   0x8000 /* enh tx addr swap (can -> phys) */

Definition at line 608 of file supern_2.h.

#define FM_ENXMTADSWAP   0x4000 /* enh rec addr swap (phys -> can) */

Definition at line 607 of file supern_2.h.

#define FM_ERROR   0x0400 /* Error (improper operation) */

Definition at line 632 of file supern_2.h.

#define FM_EXACT   0x1000 /* Exact Match */

Definition at line 634 of file supern_2.h.

#define FM_EXGPA0   0x0010 /* extended-group-addressing bit 0 */

Definition at line 374 of file supern_2.h.

#define FM_EXGPA1   0x0020 /* extended-group-addressing bit 1 */

Definition at line 375 of file supern_2.h.

#define FM_FCNTR   0x41 /* r/w the 16-bit frame counter */

Definition at line 319 of file supern_2.h.

#define FM_FOUND   0x2000 /* Comparand found in CAM */

Definition at line 635 of file supern_2.h.

#define FM_FRMTHR   0x21 /* r/w the frame threshold register */

Definition at line 278 of file supern_2.h.

#define FM_FRSELREG   0x45 /* r/w Frame Selection Register */

Definition at line 325 of file supern_2.h.

#define FM_FSCNTR   0x44 /* r/? Frame Strip Counter */

Definition at line 324 of file supern_2.h.

#define FM_FULL   0x4000 /* CAM full */

Definition at line 636 of file supern_2.h.

#define FM_FULL_HALF   0x0004 /* full-duplex/half-duplex bit */

Definition at line 372 of file supern_2.h.

#define FM_HOFLXI   0x0003 /* SN3: Hold / Flush / Inhibit */

Definition at line 371 of file supern_2.h.

#define FM_IACTR   0x10 /* abort current transmit activity */

Definition at line 696 of file supern_2.h.

#define FM_IBL   0x06 /* beacon/listen */

Definition at line 664 of file supern_2.h.

#define FM_ICL   0x05 /* claim/listen */

Definition at line 663 of file supern_2.h.

#define FM_ICL_SKIP   (7<<0) /* Clear all SKIP bits */

Definition at line 622 of file supern_2.h.

#define FM_ICLLA0   0x12 /* clear asynchronous queue 0 lock */

Definition at line 675 of file supern_2.h.

#define FM_ICLLA1   0x14 /* clear asynchronous queue 1 lock */

Definition at line 676 of file supern_2.h.

#define FM_ICLLA2   0x18 /* clear asynchronous queue 2 lock */

Definition at line 677 of file supern_2.h.

#define FM_ICLLAL   0x3f /* clear all queue locks */

Definition at line 683 of file supern_2.h.

#define FM_ICLLR   0x20 /* clear receive queue (SN3:1) lock */

Definition at line 679 of file supern_2.h.

#define FM_ICLLR2   0x21 /* SN3: clear receive queue 2 lock */

Definition at line 680 of file supern_2.h.

#define FM_ICLLS   0x11 /* clear synchronous queue lock */

Definition at line 674 of file supern_2.h.

#define FM_IDRXBUS   0x23 /* SN3: drive X-Bus */

Definition at line 682 of file supern_2.h.

#define FM_IENTM   0x09 /* enter nonrestricted token mode */

Definition at line 667 of file supern_2.h.

#define FM_IERSF   0x40 /* enable receive single frame */

Definition at line 699 of file supern_2.h.

#define FM_IERTM   0x0a /* enter restricted token mode */

Definition at line 668 of file supern_2.h.

#define FM_IESIM   0x0f /* exit send-immediate mode */

Definition at line 673 of file supern_2.h.

#define FM_IFIND   (4<<0) /* Find */

Definition at line 619 of file supern_2.h.

#define FM_IIL   0x04 /* idle/listen */

Definition at line 662 of file supern_2.h.

#define FM_IINV   (5<<0) /* Invalidate */

Definition at line 620 of file supern_2.h.

#define FM_IINV_CAM   (0<<0) /* Invalidate CAM */

Definition at line 615 of file supern_2.h.

#define FM_ILTVX   0x07 /* load TVX timer from TVX reg */

Definition at line 665 of file supern_2.h.

#define FM_IMR   0x66 /* r/w Interrupt mask register */

Definition at line 334 of file supern_2.h.

#define FM_IMSK1L   0x05 /* r/w lower 16-bit of IMSK 1 */

Definition at line 248 of file supern_2.h.

#define FM_IMSK1U   0x04 /* r/w upper 16-bit of IMSK 1 */

Definition at line 247 of file supern_2.h.

#define FM_IMSK2L   0x07 /* r/w lower 16-bit of IMSK 2 */

Definition at line 250 of file supern_2.h.

#define FM_IMSK2U   0x06 /* r/w upper 16-bit of IMSK 2 */

Definition at line 249 of file supern_2.h.

#define FM_IMSK3L   0x64 /* r/w lower 16-bit of IMSK reg 3 */

Definition at line 332 of file supern_2.h.

#define FM_IMSK3U   0x63 /* r/w upper 16-bit of IMSK reg 3 */

Definition at line 331 of file supern_2.h.

#define FM_INRTM   0x08 /* nonrestricted token mode */

Definition at line 666 of file supern_2.h.

#define FM_INST   0x0007 /* Address Filter Operation */

Definition at line 614 of file supern_2.h.

#define FM_IREAD_CAM   (2<<0) /* Read CAM */

Definition at line 617 of file supern_2.h.

#define FM_IRESET   0x01 /* software reset */

Definition at line 659 of file supern_2.h.

#define FM_IRMEMWI   0x02 /* load Memory Data Reg., inc MARR */

Definition at line 660 of file supern_2.h.

#define FM_IRMEMWO   0x03 /* load MDR from buffer memory, n.i. */

Definition at line 661 of file supern_2.h.

#define FM_IRSTQ   0x20 /* reset transmit queues */

Definition at line 697 of file supern_2.h.

#define FM_IRTM   0x0b /* restricted token mode */

Definition at line 669 of file supern_2.h.

#define FM_IRUN_BIST   (3<<0) /* Run BIST */

Definition at line 618 of file supern_2.h.

#define FM_ISIM   0x0e /* enter send-immediate mode */

Definition at line 672 of file supern_2.h.

#define FM_ISKIP   (6<<0) /* Skip */

Definition at line 621 of file supern_2.h.

#define FM_ISRT   0x0d /* send restricted token */

Definition at line 671 of file supern_2.h.

#define FM_ISTTB   0x30 /* set tag bit */

Definition at line 698 of file supern_2.h.

#define FM_ISURT   0x0c /* send unrestricted token */

Definition at line 670 of file supern_2.h.

#define FM_ITR   0x50 /* SN3: Transmit Command */

Definition at line 701 of file supern_2.h.

#define FM_ITRA0   0x02 /* transmit asynchronous queue 0 */

Definition at line 690 of file supern_2.h.

#define FM_ITRA1   0x04 /* transmit asynchronous queue 1 */

Definition at line 692 of file supern_2.h.

#define FM_ITRA2   0x08 /* transmit asynchronous queue 2 */

Definition at line 694 of file supern_2.h.

#define FM_ITRS   0x01 /* transmit synchronous queue */

Definition at line 688 of file supern_2.h.

#define FM_ITRXBUS   0x22 /* SN3: Tristate X-Bus (SAS only) */

Definition at line 681 of file supern_2.h.

#define FM_IVR   0x65 /* read Interrupt Vector register */

Definition at line 333 of file supern_2.h.

#define FM_IWRITE_CAM   (1<<0) /* Write CAM */

Definition at line 616 of file supern_2.h.

#define FM_LAGC   0x0e /* r/w long addr.-gr. (middle) */

Definition at line 257 of file supern_2.h.

#define FM_LAGL   0x0f /* r/w long addr.-gr. (LSW) */

Definition at line 258 of file supern_2.h.

#define FM_LAGM   0x0d /* r/w long addr.-gr. (MSW of LAGP) */

Definition at line 256 of file supern_2.h.

#define FM_LAIC   0x0a /* r/w long addr.-ind. (middle)*/

Definition at line 253 of file supern_2.h.

#define FM_LAIL   0x0b /* r/w long addr.-ind. (LSW) */

Definition at line 254 of file supern_2.h.

#define FM_LAIM   0x09 /* r/w long addr.-ind. (MSW of LAID) */

Definition at line 252 of file supern_2.h.

#define FM_LCNTR   0x42 /* r/w the 16-bit lost counter */

Definition at line 320 of file supern_2.h.

#define FM_LOCKTX   0x0008 /* lock-transmit-asynchr.-queues bit */

Definition at line 373 of file supern_2.h.

#define FM_LSB   0x0800 /* determ. ordering of bytes in buffer*/

Definition at line 418 of file supern_2.h.

#define FM_LTDPA1   0x79 /* r/w Last Trans desc ptr for A1 qu. */

Definition at line 344 of file supern_2.h.

#define FM_MARR   0x3c /* r/w the memory read addr register */

Definition at line 312 of file supern_2.h.

#define FM_MARW   0x3d /* r/w the memory write addr register*/

Definition at line 313 of file supern_2.h.

#define FM_MDAMA   (0<<8) /* address detection : DA = MA */

Definition at line 381 of file supern_2.h.

#define FM_MDASAMA   (1<<8) /* address detection : DA=MA||SA=MA */

Definition at line 382 of file supern_2.h.

#define FM_MDISRCV   (4<<8) /* disable receive function */

Definition at line 385 of file supern_2.h.

#define FM_MDREG1   0x10 /* r/w 16-bit mode reg 1 */

Definition at line 259 of file supern_2.h.

#define FM_MDREG2   0x20 /* r/w 16-bit mode reg 2 */

Definition at line 277 of file supern_2.h.

#define FM_MDREG3   0x60 /* r/w Mode Register 3 */

Definition at line 328 of file supern_2.h.

#define FM_MDRL   0x3f /* r/w lower 16-bit of mem. data reg */

Definition at line 315 of file supern_2.h.

#define FM_MDRTAG   0x0004 /* tag bit of long word read */

Definition at line 554 of file supern_2.h.

#define FM_MDRU   0x3e /* r/w upper 16-bit of mem. data reg */

Definition at line 314 of file supern_2.h.

#define FM_MEIND   0x0030 /* Ena enh A,C indicator settings */

Definition at line 570 of file supern_2.h.

#define FM_MELOOP   (7<<12) /* external loopback */

Definition at line 400 of file supern_2.h.

#define FM_MENAFULL   0x0008 /* Ena enh QCTRL encoding for AFULL */

Definition at line 569 of file supern_2.h.

#define FM_MENDAS   0x0100 /* Ena DAS connections by cntr MUX */

Definition at line 573 of file supern_2.h.

#define FM_MENDRCV   0x0800 /* Ena dual receive queue operation */

Definition at line 576 of file supern_2.h.

#define FM_MENFCLOC   0x3000 /* Ena FC location within frm data */

Definition at line 577 of file supern_2.h.

#define FM_MENPLCCST   0x0200 /* Ena Counter Segm test in PLC blck */

Definition at line 574 of file supern_2.h.

#define FM_MENQCTRL   0x0040 /* Ena enh QCTRL encoding */

Definition at line 571 of file supern_2.h.

#define FM_MENRQAUNLCK   0x0080 /* Ena rec q auto unlock */

Definition at line 572 of file supern_2.h.

#define FM_MENRS   0x0001 /* Ena enhanced rec status encoding */

Definition at line 566 of file supern_2.h.

#define FM_MENSGLINT   0x0400 /* Ena Vectored Interrupt reading */

Definition at line 575 of file supern_2.h.

#define FM_MENTDLPBK   0x8000 /* Ena TDAT to RDAT lkoopback */

Definition at line 579 of file supern_2.h.

#define FM_MENTRCMD   0x4000 /* Ena ASYNC1 xmit only after command */

Definition at line 578 of file supern_2.h.

#define FM_MENXCT   0x0004 /* Ena EXACT/INEXACT matching */

Definition at line 568 of file supern_2.h.

#define FM_MENXS   0x0002 /* Ena enhanced xmit status encoding */

Definition at line 567 of file supern_2.h.

#define FM_MILOOP   (4<<12) /* internal loopback */

Definition at line 397 of file supern_2.h.

#define FM_MINIT   (0<<12) /* initialize */

Definition at line 393 of file supern_2.h.

#define FM_MIR0   0x13 /* read lower 16-bit of MAC Info Reg */

Definition at line 262 of file supern_2.h.

#define FM_MIR1   0x12 /* read upper 16-bit of MAC Info Reg */

Definition at line 261 of file supern_2.h.

#define FM_MLIMPROM   (6<<8) /* limited-promiscuous mode */

Definition at line 387 of file supern_2.h.

#define FM_MMEMACT   (1<<12) /* memory activate */

Definition at line 394 of file supern_2.h.

#define FM_MMODE   0x7000 /* mode select */

Definition at line 392 of file supern_2.h.

#define FM_MONLINE   (3<<12) /* on-line (FDDI operational mode) */

Definition at line 396 of file supern_2.h.

#define FM_MONLINESP   (2<<12) /* on-line special */

Definition at line 395 of file supern_2.h.

#define FM_MPROMISCOUS   (7<<8) /* address detection : promiscuous */

Definition at line 388 of file supern_2.h.

#define FM_MRES0   (5<<8) /* reserve */

Definition at line 386 of file supern_2.h.

#define FM_MRES1   (5<<12) /* reserved */

Definition at line 398 of file supern_2.h.

#define FM_MRES2   (6<<12) /* reserved */

Definition at line 399 of file supern_2.h.

#define FM_MRNNSAF   (3<<8) /* rec. non-NSA frames DA = MA */

Definition at line 384 of file supern_2.h.

#define FM_MRNNSAFNMA   (2<<8) /* rec. non-NSA frames DA=MA&&SA!=MA */

Definition at line 383 of file supern_2.h.

#define FM_MULT   0x0800 /* Multiple Match */

Definition at line 633 of file supern_2.h.

#define FM_ORBIST   0xd0 /* r/w Orion BIST signature */

Definition at line 360 of file supern_2.h.

#define FM_ORSTAT   0xd2 /* r/w Orion Status Register */

Definition at line 361 of file supern_2.h.

#define FM_PARITY   0x1000 /* 1 = even, 0 = odd */

Definition at line 419 of file supern_2.h.

#define FM_PDX_BIST_DONE   0x0004 /* PDX BIST is done */

Definition at line 544 of file supern_2.h.

#define FM_PLC_BIST_DONE   0x0002 /* internal PLC Bist is done */

Definition at line 543 of file supern_2.h.

#define FM_PRI0   0x1c /* r/w priority r. for asyn.-queue 0 */

Definition at line 273 of file supern_2.h.

#define FM_PRI1   0x1d /* r/w priority r. for asyn.-queue 1 */

Definition at line 274 of file supern_2.h.

#define FM_PRI2   0x1e /* r/w priority r. for asyn.-queue 2 */

Definition at line 275 of file supern_2.h.

#define FM_RCSTAT   0x0380 /* receiver state machine state */

Definition at line 557 of file supern_2.h.

#define FM_RCV1_ALL   (0<<0) /* receive all frames */

Definition at line 586 of file supern_2.h.

#define FM_RCV1_ALLC   (7<<0) /* rec all async LLC frames */

Definition at line 593 of file supern_2.h.

#define FM_RCV1_ALSMT   (9<<0) /* rec all async LLC & SMT frames */

Definition at line 595 of file supern_2.h.

#define FM_RCV1_IMP   (4<<0) /* rec Implementor frames */

Definition at line 590 of file supern_2.h.

#define FM_RCV1_LLC   (1<<0) /* rec all LLC frames */

Definition at line 587 of file supern_2.h.

#define FM_RCV1_MAC   (5<<0) /* rec all MAC frames */

Definition at line 591 of file supern_2.h.

#define FM_RCV1_NSMT   (3<<0) /* rec non-SMT frames */

Definition at line 589 of file supern_2.h.

#define FM_RCV1_SLLC   (6<<0) /* rec all sync LLC frames */

Definition at line 592 of file supern_2.h.

#define FM_RCV1_SMT   (2<<0) /* rec all SMT frames */

Definition at line 588 of file supern_2.h.

#define FM_RCV1_VOID   (8<<0) /* rec all void frames */

Definition at line 594 of file supern_2.h.

#define FM_RCV2_ALL   (0<<4) /* receive all other frames */

Definition at line 597 of file supern_2.h.

#define FM_RCV2_ALLC   (7<<4) /* rec all async LLC frames */

Definition at line 604 of file supern_2.h.

#define FM_RCV2_ALSMT   (9<<4) /* rec all async LLC & SMT frames */

Definition at line 606 of file supern_2.h.

#define FM_RCV2_IMP   (4<<4) /* rec Implementor frames */

Definition at line 601 of file supern_2.h.

#define FM_RCV2_LLC   (1<<4) /* rec all LLC frames */

Definition at line 598 of file supern_2.h.

#define FM_RCV2_MAC   (5<<4) /* rec all MAC frames */

Definition at line 602 of file supern_2.h.

#define FM_RCV2_NSMT   (3<<4) /* rec non-SMT frames */

Definition at line 600 of file supern_2.h.

#define FM_RCV2_SLLC   (6<<4) /* rec all sync LLC frames */

Definition at line 603 of file supern_2.h.

#define FM_RCV2_SMT   (2<<4) /* rec all SMT frames */

Definition at line 599 of file supern_2.h.

#define FM_RCV2_VOID   (8<<4) /* rec all void frames */

Definition at line 605 of file supern_2.h.

#define FM_RCVERR   0x0010 /* rec.-errored-frames bit */

Definition at line 411 of file supern_2.h.

#define FM_RECV1   0x000f /* options for receive queue 1 */

Definition at line 585 of file supern_2.h.

#define FM_RECV2   0x00f0 /* options for receive queue 2 */

Definition at line 596 of file supern_2.h.

#define FM_RES0   0x0001 /* reserved */

Definition at line 367 of file supern_2.h.

#define FM_REV   0xe000 /* FORMAC Plus revision number */

Definition at line 560 of file supern_2.h.

#define FM_REV_NO   0x00e0 /* Revision Number of Address Filter */

Definition at line 629 of file supern_2.h.

#define FM_RPR   0x2d /* r/w the read ptr. for receive qu. */

Definition at line 292 of file supern_2.h.

#define FM_RPR1   FM_RPR

Definition at line 296 of file supern_2.h.

#define FM_RPR2   0x68 /* r/w the read ptr. for rec. qu. 2 */

Definition at line 336 of file supern_2.h.

#define FM_RPXA0   0x39 /* r/w the read ptr. for asyn. qu. 0 */

Definition at line 309 of file supern_2.h.

#define FM_RPXA1   0x3a /* r/w the read ptr. for asyn. qu. 1 */

Definition at line 310 of file supern_2.h.

#define FM_RPXA2   0x3b /* r/w the read ptr. for asyn. qu. 2 */

Definition at line 311 of file supern_2.h.

#define FM_RPXS   0x38 /* r/w the read ptr. for synchr. qu. */

Definition at line 308 of file supern_2.h.

#define FM_RPXSF   0x2b /* r/w the read ptr. for special fr. */

Definition at line 291 of file supern_2.h.

#define FM_RXFBB01   0x0600 /* rec. frame byte boundary bit0 & 1 */

Definition at line 417 of file supern_2.h.

#define FM_SA   0x0008 /* Source Address */

Definition at line 652 of file supern_2.h.

#define FM_SABC   0x29 /* r/w start addr of beacon frame */

Definition at line 289 of file supern_2.h.

#define FM_SACL   0x28 /* r/w start addr of claim frame */

Definition at line 288 of file supern_2.h.

#define FM_SADET   0x0100 /* address detect */

Definition at line 514 of file supern_2.h.

#define FM_SAGP   0x0c /* r/w short address-group */

Definition at line 255 of file supern_2.h.

#define FM_SAID   0x08 /* r/w short addr.-individual */

Definition at line 251 of file supern_2.h.

#define FM_SAX   0x0010 /* Source Address Exact */

Definition at line 653 of file supern_2.h.

#define FM_SBEC   0x0004 /* beacon state entered */

Definition at line 484 of file supern_2.h.

#define FM_SCLM   0x0040 /* claim state entered */

Definition at line 488 of file supern_2.h.

#define FM_SDUPCLM   0x0004 /* duplicate claim received */

Definition at line 508 of file supern_2.h.

#define FM_SELRA   0x0080 /* select input from PHY (1=RA,0=RB) */

Definition at line 378 of file supern_2.h.

#define FM_SELSA   0x0800 /* select-short-address bit */

Definition at line 390 of file supern_2.h.

#define FM_SERRCTR   0x0020 /* error counter overflow */

Definition at line 511 of file supern_2.h.

#define FM_SERRSF   0x0080 /* error in special frame */

Definition at line 489 of file supern_2.h.

#define FM_SESTRIPTK   0x0001 /* SN3: 'no description' */

Definition at line 506 of file supern_2.h.

#define FM_SFRMCTR   0x0010 /* frame counter overflow */

Definition at line 510 of file supern_2.h.

#define FM_SHICLM   0x0010 /* high claim received */

Definition at line 486 of file supern_2.h.

#define FM_SICAMDAMAT   0x0010 /* Status internal CAM DA match */

Definition at line 546 of file supern_2.h.

#define FM_SICAMDAXACT   0x0020 /* Status internal CAM DA exact match */

Definition at line 547 of file supern_2.h.

#define FM_SICAMSAMAT   0x0040 /* Status internal CAM SA match */

Definition at line 548 of file supern_2.h.

#define FM_SICAMSAXACT   0x0080 /* Status internal CAM SA exact match */

Definition at line 549 of file supern_2.h.

#define FM_SIM   0x1000 /* indicate send immediate-mode */

Definition at line 559 of file supern_2.h.

#define FM_SKIP   0x0020 /* Skip this entry */

Definition at line 654 of file supern_2.h.

#define FM_SLOCLM   0x0008 /* low claim received */

Definition at line 485 of file supern_2.h.

#define FM_SLSTCTR   0x0040 /* lost counter overflow */

Definition at line 512 of file supern_2.h.

#define FM_SMISFRM   0x0200 /* missed frame */

Definition at line 515 of file supern_2.h.

#define FM_SMULTDA   0x4000 /* multiple destination address */

Definition at line 520 of file supern_2.h.

#define FM_SMYBEC   0x0002 /* my beacon received */

Definition at line 483 of file supern_2.h.

#define FM_SMYCLM   0x0020 /* my claim received */

Definition at line 487 of file supern_2.h.

#define FM_SNFSLD   0x0100 /* NP and FORMAC+ simultaneous load */

Definition at line 490 of file supern_2.h.

#define FM_SNGLFRM   0x8000 /* single-frame-receive mode */

Definition at line 402 of file supern_2.h.

#define FM_SNPPND   0x0008 /* r/w from buffer mem. is pending */

Definition at line 555 of file supern_2.h.

#define FM_SOTRBEC   0x0001 /* other beacon received */

Definition at line 482 of file supern_2.h.

#define FM_SPCEPDA0   0x0200 /* parity/coding error: asyn. queue0 */

Definition at line 469 of file supern_2.h.

#define FM_SPCEPDA1   0x0400 /* parity/coding error: asyn. queue1 */

Definition at line 470 of file supern_2.h.

#define FM_SPCEPDA2   0x0800 /* parity/coding error: asyn. queue2 */

Definition at line 471 of file supern_2.h.

#define FM_SPCEPDS   0x0100 /* parity/coding error: syn. queue */

Definition at line 468 of file supern_2.h.

#define FM_SPHINV   0x0080 /* PHY invalid */

Definition at line 513 of file supern_2.h.

#define FM_SQLCKA0   0x0002 /* queue lock for asynchr. queue 0 */

Definition at line 456 of file supern_2.h.

#define FM_SQLCKA1   0x0004 /* queue lock for asynchr. queue 1 */

Definition at line 457 of file supern_2.h.

#define FM_SQLCKA2   0x0008 /* queue lock for asynchr. queue 2 */

Definition at line 458 of file supern_2.h.

#define FM_SQLCKS   0x0001 /* queue lock for synchr. queue */

Definition at line 455 of file supern_2.h.

#define FM_SRABT   0x2000 /* receive abort */

Definition at line 497 of file supern_2.h.

#define FM_SRABT2   0x2000 /* receive abort rx queue 2 */

Definition at line 534 of file supern_2.h.

#define FM_SRBFL   0x1000 /* receive buffer full */

Definition at line 496 of file supern_2.h.

#define FM_SRBFL2   0x1000 /* receive buffer full rx queue 2 */

Definition at line 533 of file supern_2.h.

#define FM_SRBMT   0x4000 /* receive buffer empty */

Definition at line 498 of file supern_2.h.

#define FM_SRBMT2   0x4000 /* receive buf empty rx queue 2 */

Definition at line 535 of file supern_2.h.

#define FM_SRCOMP   0x8000 /* receive complete. Nontag mode */

Definition at line 499 of file supern_2.h.

#define FM_SRCOMP2   0x8000 /* receive comp rx queue 2 */

Definition at line 536 of file supern_2.h.

#define FM_SRCVFRM   0x0400 /* receive frame */

Definition at line 493 of file supern_2.h.

#define FM_SRCVOVR   0x0800 /* receive FIFO overflow */

Definition at line 495 of file supern_2.h.

#define FM_SRCVOVR2   0x0800 /* receive FIFO overfull rx queue 2 */

Definition at line 532 of file supern_2.h.

#define FM_SRES0   0x0001 /* reserved */

Definition at line 505 of file supern_2.h.

#define FM_SRFRCTOV   0x0200 /* receive frame counter overflow */

Definition at line 491 of file supern_2.h.

#define FM_SRNGOP   0x8000 /* ring operational */

Definition at line 521 of file supern_2.h.

#define FM_SRPERRQ1   0x0004 /* receive parity error rx queue 1 */

Definition at line 529 of file supern_2.h.

#define FM_SRPERRQ2   0x0008 /* receive parity error rx queue 2 */

Definition at line 530 of file supern_2.h.

#define FM_SRQUNLCK1   0x0001 /* receive queue unlocked queue 1 */

Definition at line 527 of file supern_2.h.

#define FM_SRQUNLCK2   0x0002 /* receive queue unlocked queue 2 */

Definition at line 528 of file supern_2.h.

#define FM_SSIFG   0x0008 /* short interframe gap */

Definition at line 509 of file supern_2.h.

#define FM_ST1L   0x01 /* read lower 16-bit of status reg 1 */

Definition at line 244 of file supern_2.h.

#define FM_ST1U   0x00 /* read upper 16-bit of status reg 1 */

Definition at line 243 of file supern_2.h.

#define FM_ST2L   0x03 /* read lower 16-bit of status reg 2 */

Definition at line 246 of file supern_2.h.

#define FM_ST2U   0x02 /* read upper 16-bit of status reg 2 */

Definition at line 245 of file supern_2.h.

#define FM_ST3L   0x62 /* read lower 16-bit of status reg 3 */

Definition at line 330 of file supern_2.h.

#define FM_ST3U   0x61 /* read upper 16-bit of status reg 3 */

Definition at line 329 of file supern_2.h.

#define FM_STBFLA   0x0200 /* asynchr.-queue trans. buffer full */

Definition at line 443 of file supern_2.h.

#define FM_STBFLS   0x0400 /* synchr.-queue transm. buffer full */

Definition at line 444 of file supern_2.h.

#define FM_STBURA0   0x2000 /* transmit buffer underrun: asyn.0 */

Definition at line 474 of file supern_2.h.

#define FM_STBURA1   0x4000 /* transmit buffer underrun: asyn.1 */

Definition at line 475 of file supern_2.h.

#define FM_STBURA2   0x8000 /* transmit buffer underrun: asyn.2 */

Definition at line 476 of file supern_2.h.

#define FM_STBURS   0x1000 /* transmit buffer underrun: syn. q. */

Definition at line 473 of file supern_2.h.

#define FM_STECFRMA0   0x0020 /* transmit end of chain of asyn. q0 */

Definition at line 435 of file supern_2.h.

#define FM_STECFRMA1   0x0040 /* transmit end of chain of asyn. q1 */

Definition at line 437 of file supern_2.h.

#define FM_STECFRMA2   0x0080 /* transmit end of chain of asyn. q2 */

Definition at line 440 of file supern_2.h.

#define FM_STECFRMS   0x0010 /* transmit end of chain of syn. qu. */

Definition at line 433 of file supern_2.h.

#define FM_STECMDA1   0x0040 /* SN3: 'no description' */

Definition at line 439 of file supern_2.h.

#define FM_STEFRMA0   0x0002 /* transmit end of frame: asyn. qu.0 */

Definition at line 429 of file supern_2.h.

#define FM_STEFRMA1   0x0004 /* transmit end of frame: asyn. qu.1 */

Definition at line 430 of file supern_2.h.

#define FM_STEFRMA2   0x0008 /* transmit end of frame: asyn. qu.2 */

Definition at line 431 of file supern_2.h.

#define FM_STEFRMS   0x0001 /* transmit end of frame: synchr. qu.*/

Definition at line 428 of file supern_2.h.

#define FM_STEXDONS   0x0100 /* transmit until XDONE in syn. qu. */

Definition at line 442 of file supern_2.h.

#define FM_STKERR   0x2000 /* token error */

Definition at line 519 of file supern_2.h.

#define FM_STKISS   0x1000 /* token issued */

Definition at line 518 of file supern_2.h.

#define FM_STMCHN   0x11 /* read state-machine reg */

Definition at line 260 of file supern_2.h.

#define FM_STRPFCS   0x4000 /* 1 = strips FCS field of rec.frame */

Definition at line 421 of file supern_2.h.

#define FM_STRTEXP   0x0400 /* TRT expired and late count > 0 */

Definition at line 516 of file supern_2.h.

#define FM_STRTEXR   0x0002 /* TRT expired in claim | beacon st. */

Definition at line 507 of file supern_2.h.

#define FM_STVXEXP   0x0800 /* TVX expired */

Definition at line 517 of file supern_2.h.

#define FM_STXABRA0   0x1000 /* asynchr. queue 0 transmit-abort */

Definition at line 446 of file supern_2.h.

#define FM_STXABRA1   0x2000 /* asynchr. queue 1 transmit-abort */

Definition at line 447 of file supern_2.h.

#define FM_STXABRA2   0x4000 /* asynchr. queue 2 transmit-abort */

Definition at line 448 of file supern_2.h.

#define FM_STXABRS   0x0800 /* synchr. queue transmit-abort */

Definition at line 445 of file supern_2.h.

#define FM_STXINFLA0   0x0020 /* transmit instruction full: asyn.0 */

Definition at line 462 of file supern_2.h.

#define FM_STXINFLA1   0x0040 /* transmit instruction full: asyn.1 */

Definition at line 464 of file supern_2.h.

#define FM_STXINFLA2   0x0080 /* transmit instruction full: asyn.2 */

Definition at line 466 of file supern_2.h.

#define FM_STXINFLS   0x0010 /* transmit instruction full: syn. */

Definition at line 460 of file supern_2.h.

#define FM_SWPR   0x2f /* r/w the shadow wr.-ptr. for rec.q.*/

Definition at line 294 of file supern_2.h.

#define FM_SWPR1   FM_SWPR

Definition at line 298 of file supern_2.h.

#define FM_SWPR2   0x6a /* r/w the shadow wptr. for rec. q. 2 */

Definition at line 338 of file supern_2.h.

#define FM_SWPXA0   0x35 /* r/w the shad. wr.-ptr. for asyn.q0*/

Definition at line 305 of file supern_2.h.

#define FM_SWPXA1   0x36 /* r/w the shad. wr.-ptr. for asyn.q1*/

Definition at line 306 of file supern_2.h.

#define FM_SWPXA2   0x37 /* r/w the shad. wr.-ptr. for asyn.q2*/

Definition at line 307 of file supern_2.h.

#define FM_SWPXS   0x34 /* r/w the shadow wr.-ptr. for syn.q.*/

Definition at line 304 of file supern_2.h.

#define FM_SXMTABT   0x8000 /* transmit abort */

Definition at line 450 of file supern_2.h.

#define FM_SYMCTL   0x0020 /* sysmbol-control bit */

Definition at line 412 of file supern_2.h.

#define FM_SYNPRQ   0x0040 /* synchron.-NP-DMA-request bit */

Definition at line 414 of file supern_2.h.

#define FM_THT   0x17 /* r/w upper 16-bit of THT timer */

Definition at line 266 of file supern_2.h.

#define FM_TM01   0x0c00 /* indicate token mode */

Definition at line 558 of file supern_2.h.

#define FM_TMAX   0x14 /* r/w 16-bit TMAX reg */

Definition at line 263 of file supern_2.h.

#define FM_TMRS   0x19 /* read lower 5-bit of TNEG,TRT,THT */

Definition at line 268 of file supern_2.h.

#define FM_TMSYNC   0x40 /* r/w upper 16 bits of TMSYNC timer */

Definition at line 318 of file supern_2.h.

#define FM_TNEG   0x18 /* read upper 16-bit of TNEG (TTRT) */

Definition at line 267 of file supern_2.h.

#define FM_TREQ0   0x1a /* r/w 16-bit TREQ0 reg (LSW of TRT) */

Definition at line 271 of file supern_2.h.

#define FM_TREQ1   0x1b /* r/w 16-bit TREQ1 reg (MSW of TRT) */

Definition at line 272 of file supern_2.h.

#define FM_TRT   0x16 /* r/w upper 16-bit of TRT timer */

Definition at line 265 of file supern_2.h.

#define FM_TSYNC   0x1f /* r/w 16-bit of the TSYNC register */

Definition at line 276 of file supern_2.h.

#define FM_TVX

Value:

0x15        /* write 8-bit TVX reg with NP7-0
                       read TVX on NP7-0, timer on NP15-8*/

Definition at line 264 of file supern_2.h.

#define FM_TXSTAT   0x0070 /* transmitter state machine state */

Definition at line 556 of file supern_2.h.

#define FM_UNLCKDLY   0x6c /* r/w Auto Unlock Delay register */

Definition at line 340 of file supern_2.h.

#define FM_VALID   0x0001 /* CAM Entry Valid */

Definition at line 649 of file supern_2.h.

#define FM_WPR   0x2e /* r/w the write ptr. for receive qu.*/

Definition at line 293 of file supern_2.h.

#define FM_WPR1   FM_WPR

Definition at line 297 of file supern_2.h.

#define FM_WPR2   0x69 /* r/w the write ptr. for rec. qu. 2 */

Definition at line 337 of file supern_2.h.

#define FM_WPXA0   0x31 /* r/w the write ptr. for asyn. qu.0 */

Definition at line 301 of file supern_2.h.

#define FM_WPXA1   0x32 /* r/w the write ptr. for asyn. qu.1 */

Definition at line 302 of file supern_2.h.

#define FM_WPXA2   0x33 /* r/w the write ptr. for asyn. qu.2 */

Definition at line 303 of file supern_2.h.

#define FM_WPXS   0x30 /* r/w the write ptr. for synchr. qu.*/

Definition at line 300 of file supern_2.h.

#define FM_WPXSF   0x2a /* r/w the write ptr. for special fr.*/

Definition at line 290 of file supern_2.h.

#define FM_XMTINH_HOLD   0x0002 /* transmit-inhibit/hold bit */

Definition at line 369 of file supern_2.h.

#define FRM_IMPA   (2)

Definition at line 69 of file supern_2.h.

#define FRM_IMPS   (6)

Definition at line 72 of file supern_2.h.

#define FRM_LLCA   (1)

Definition at line 68 of file supern_2.h.

#define FRM_LLCS   (5)

Definition at line 71 of file supern_2.h.

#define FRM_MAC   (4) /* synchr. frames */

Definition at line 70 of file supern_2.h.

#define FRM_SMT   (0) /* asynchr. frames */

Definition at line 67 of file supern_2.h.

#define FS_AI   (1<<1)

Definition at line 47 of file supern_2.h.

#define FS_CI   (1<<0)

Definition at line 48 of file supern_2.h.

#define FS_EI   (1<<2)

Definition at line 46 of file supern_2.h.

#define FS_ERFBB0   (1<<0) /* - " - */

Definition at line 62 of file supern_2.h.

#define FS_ERFBB1   (1<<1) /* byte offset (depends on LSB bit) */

Definition at line 61 of file supern_2.h.

#define FS_MSRABT   (1<<14) /* frame was aborted during reception*/

Definition at line 51 of file supern_2.h.

#define FS_MSVALID   (1<<15) /* end of queue */

Definition at line 50 of file supern_2.h.

#define FS_SADRRG   (1<<7) /* address recognized */

Definition at line 57 of file supern_2.h.

#define FS_SEAC0   (FS_CI<<9) /* copy indicator */

Definition at line 55 of file supern_2.h.

#define FS_SEAC1   (FS_AI<<9) /* address indicator */

Definition at line 54 of file supern_2.h.

#define FS_SEAC2   (FS_EI<<9) /* error indicator */

Definition at line 53 of file supern_2.h.

#define FS_SFRMERR   (1<<8) /* error detected (CRC or length) */

Definition at line 56 of file supern_2.h.

#define FS_SFRMTY0   (1<<4) /* frame-type bit (LLC) */

Definition at line 60 of file supern_2.h.

#define FS_SFRMTY1   (1<<5) /* frame-type bit (impementor) */

Definition at line 59 of file supern_2.h.

#define FS_SFRMTY2   (1<<6) /* frame-class bit */

Definition at line 58 of file supern_2.h.

#define FS_SSRCRTG   (1<<12) /* if SA has set MSB (source-routing)*/

Definition at line 52 of file supern_2.h.

#define MB   0xff

Definition at line 39 of file supern_2.h.

#define MD   0xffffffff

Definition at line 41 of file supern_2.h.

#define MDR1INIT   (FM_MINIT | FM_MDAMA)

Definition at line 405 of file supern_2.h.

#define MSTOBCLK

(

x

)

((u_long)(x)*12500L)

Definition at line 1054 of file supern_2.h.

#define MSTOTVX

(

x

)

(((u_long)(x)*1000L)/80/255)

Definition at line 1055 of file supern_2.h.

#define MW   0xffff

Definition at line 40 of file supern_2.h.

#define PL_B_HLS   (6) /* halt line state detected */

Definition at line 916 of file supern_2.h.

#define PL_B_ILS   (5) /* idle line state detected */

Definition at line 915 of file supern_2.h.

#define PL_B_NOT   (0) /* PCM SM has not gone to BREAK state*/

Definition at line 910 of file supern_2.h.

#define PL_B_PCS   (1) /* PC_Start issued */

Definition at line 911 of file supern_2.h.

#define PL_B_QLS   (4) /* quit line state detected */

Definition at line 914 of file supern_2.h.

#define PL_B_TNE   (3) /* TNE timer expired after NS_MAX */

Definition at line 913 of file supern_2.h.

#define PL_B_TPC   (2) /* TPC timer expired after T_OUT */

Definition at line 912 of file supern_2.h.

#define PL_BIST_SIGNAT   0x15 /* built in self test signature (ro)*/

Definition at line 732 of file supern_2.h.

#define PL_BREAK_REASON   0x0007 /* reason for PCM state mach.s to br.*/

Definition at line 909 of file supern_2.h.

#define PL_C_CIPHER_ENABLE   (1<<0) /* enable scrambler */

Definition at line 832 of file supern_2.h.

#define PL_C_CIPHER_LPBCK   (1<<1) /* loopback scrambler */

Definition at line 833 of file supern_2.h.

#define PL_C_FOTOFF_0   (0<<8) /* timer off */

Definition at line 846 of file supern_2.h.

#define PL_C_FOTOFF_30   (1<<8) /* 30uS */

Definition at line 847 of file supern_2.h.

#define PL_C_FOTOFF_50   (2<<8) /* 50uS */

Definition at line 848 of file supern_2.h.

#define PL_C_FOTOFF_CTRL   (3<<8) /* FOTOFF timer control */

Definition at line 845 of file supern_2.h.

#define PL_C_FOTOFF_NEVER   (3<<8) /* never */

Definition at line 849 of file supern_2.h.

#define PL_C_MIN   0x06 /* minimum connect state time (r/w) */

Definition at line 717 of file supern_2.h.

#define PL_C_SDOFF_ENABLE   (1<<6) /* enable SDOFF timer */

Definition at line 834 of file supern_2.h.

#define PL_C_SDON_084   (0<<10) /* 0.84 uS */

Definition at line 851 of file supern_2.h.

#define PL_C_SDON_132   (1<<10) /* 1.32 uS */

Definition at line 852 of file supern_2.h.

#define PL_C_SDON_252   (2<<10) /* 2.52 uS */

Definition at line 853 of file supern_2.h.

#define PL_C_SDON_512   (3<<10) /* 5.12 uS */

Definition at line 854 of file supern_2.h.

#define PL_C_SDON_ENABLE   (1<<7) /* enable SDON timer */

Definition at line 835 of file supern_2.h.

#define PL_C_SDON_TIMER   (3<<10) /* SDON timer control */

Definition at line 850 of file supern_2.h.

#define PL_C_SOFF_076   (0<<12) /* 0.76 uS */

Definition at line 856 of file supern_2.h.

#define PL_C_SOFF_132   (1<<12) /* 1.32 uS */

Definition at line 857 of file supern_2.h.

#define PL_C_SOFF_252   (2<<12) /* 2.52 uS */

Definition at line 858 of file supern_2.h.

#define PL_C_SOFF_512   (3<<12) /* 5.12 uS */

Definition at line 859 of file supern_2.h.

#define PL_C_SOFF_TIMER   (3<<12) /* SDOFF timer control */

Definition at line 855 of file supern_2.h.

#define PL_C_TSEL   (3<<14) /* scrambler path select */

Definition at line 860 of file supern_2.h.

#define PL_CI_INS   (3<<12) /* INSERTED */

Definition at line 941 of file supern_2.h.

#define PL_CI_ISCR   (1<<12) /* INSERT_SCRUB */

Definition at line 939 of file supern_2.h.

#define PL_CI_REMV   (0<<12) /* REMOVED */

Definition at line 938 of file supern_2.h.

#define PL_CI_RSCR   (2<<12) /* REMOVE_SCRUB */

Definition at line 940 of file supern_2.h.

#define PL_CLASS_S   0x0080 /* signif. that single att. station */

Definition at line 807 of file supern_2.h.

#define PL_CLK_DIV   0x14 /* TNE clock divider (read only) */

Definition at line 731 of file supern_2.h.

#define PL_CNTRL_A   0x00 /* control register A (r/w) */

Definition at line 711 of file supern_2.h.

#define PL_CNTRL_B   0x01 /* control register B (r/w) */

Definition at line 712 of file supern_2.h.

#define PL_CNTRL_C   0x0a /* control register C (r/w) */

Definition at line 721 of file supern_2.h.

#define PL_CONFIG_CNTRL   0x8000 /* control over scrub, byp. & loopb.*/

Definition at line 826 of file supern_2.h.

#define PL_EB_LOC_LOOP   0x0020 /* loop path just prior to PDT/PDR IF*/

Definition at line 775 of file supern_2.h.

#define PL_EBUF_ERR   0x0200 /* elastic buff. det. over-|underflow*/

Definition at line 964 of file supern_2.h.

#define PL_ENA_PAR_CHK   0x0400 /* enable parity check */

Definition at line 780 of file supern_2.h.

#define PL_FOT_OFF   0x0040 /* assertion of /FOTOFF pin of PLC */

Definition at line 776 of file supern_2.h.

#define PL_I_ANY   (0<<11) /* Int. on any change in *_LINE_ST */

Definition at line 820 of file supern_2.h.

#define PL_I_HALT   (2<<11) /* Interrupt on HALT line state */

Definition at line 822 of file supern_2.h.

#define PL_I_IDLE   (1<<11) /* Interrupt on IDLE line state */

Definition at line 821 of file supern_2.h.

#define PL_I_MASTR   (4<<11) /* Interrupt on MASTER line state */

Definition at line 823 of file supern_2.h.

#define PL_I_QUIET   (8<<11) /* Interrupt on QUIET line state */

Definition at line 824 of file supern_2.h.

#define PL_INTR_EVENT   0x17 /* interrupt event reg. (read only) */

Definition at line 734 of file supern_2.h.

#define PL_INTR_MASK   0x02 /* interrupt mask (r/w) */

Definition at line 713 of file supern_2.h.

#define PL_L_ALS   (1<<5) /* activ line state */

Definition at line 888 of file supern_2.h.

#define PL_L_HLS   (6<<5) /* halt line state */

Definition at line 893 of file supern_2.h.

#define PL_L_ILS16   (7<<5) /* idle line state (after 16 idle s.)*/

Definition at line 894 of file supern_2.h.

#define PL_L_ILS4   (3<<5) /* idle l. s. (after 4 idle symbols) */

Definition at line 890 of file supern_2.h.

#define PL_L_MLS   (5<<5) /* master line state */

Definition at line 892 of file supern_2.h.

#define PL_L_NLS   (0<<5) /* noise line state */

Definition at line 887 of file supern_2.h.

#define PL_L_QLS   (4<<5) /* quiet line state */

Definition at line 891 of file supern_2.h.

#define PL_L_UND   (2<<5) /* undefined */

Definition at line 889 of file supern_2.h.

#define PL_LC_LENGTH   0x0b /* link confidence test time (r/w) */

Definition at line 722 of file supern_2.h.

#define PL_LE_CTR   0x2000 /* link error event counter */

Definition at line 968 of file supern_2.h.

#define PL_LE_THRESHOLD   0x05 /* link error event threshold (r/w) */

Definition at line 716 of file supern_2.h.

#define PL_LINE_ST   0x00e0 /* contains recogn. line state of LSM*/

Definition at line 886 of file supern_2.h.

#define PL_LINK_ERR_CTR   0x1a /* link error event ctr.(read only) */

Definition at line 737 of file supern_2.h.

#define PL_LM_LOC_LOOP   0x0010 /* loop path just after elastic buff.*/

Definition at line 774 of file supern_2.h.

#define PL_LONG   0x0008 /* perf. a long Link Confid.Test(LCT)*/

Definition at line 798 of file supern_2.h.

#define PL_LOOPBACK   0x0080 /* it cause the /LPBCK pin ass. low */

Definition at line 777 of file supern_2.h.

#define PL_LS_MATCH   0x0002 /* l.s.== l.s. PLC_CNTRL_B's MATCH_LS*/

Definition at line 956 of file supern_2.h.

#define PL_LSDO   0x4000 /* SDO input pin changed to a 1 */

Definition at line 969 of file supern_2.h.

#define PL_LSF   0x0020 /* line state flag (l.s. has been r.)*/

Definition at line 920 of file supern_2.h.

#define PL_LSM_STATE   0x0010 /* state bit of LSM */

Definition at line 884 of file supern_2.h.

#define PL_M_HALT   (2<<8) /* transmit HALT line state */

Definition at line 812 of file supern_2.h.

#define PL_M_IDLE   (1<<8) /* transmit IDLE line state */

Definition at line 811 of file supern_2.h.

#define PL_M_MASTR   (3<<8) /* transmit MASTER line state */

Definition at line 813 of file supern_2.h.

#define PL_M_QUI0   (0<<8) /* transmit QUIET line state */

Definition at line 810 of file supern_2.h.

#define PL_M_QUI1   (4<<8) /* transmit QUIET line state */

Definition at line 814 of file supern_2.h.

#define PL_M_QUI2   (5<<8) /* transmit QUIET line state */

Definition at line 815 of file supern_2.h.

#define PL_M_QUI3   (7<<8) /* transmit QUIET line state */

Definition at line 817 of file supern_2.h.

#define PL_M_TPDR   (6<<8) /* tr. PHY_DATA requ.-symbol is tr.ed*/

Definition at line 816 of file supern_2.h.

#define PL_MAINT   0x0004 /* if OFF state --> MAINT state */

Definition at line 797 of file supern_2.h.

#define PL_MAINT_LS   0x0700 /* line state while in the MAINT st. */

Definition at line 809 of file supern_2.h.

#define PL_MATCH_LS   0x7800 /* line state to be comp. with curr.*/

Definition at line 819 of file supern_2.h.

#define PL_MIN_IDLE_CTR   0x19 /* minimum idle counter (read only) */

Definition at line 736 of file supern_2.h.

#define PL_MINI_CTR   0x1000 /* dep. on PLC_CNTRL_A's MINI_CTR_INT*/

Definition at line 967 of file supern_2.h.

#define PL_MINI_CTR_INT   0x0100 /* partially contr. when bit is ass. */

Definition at line 778 of file supern_2.h.

#define PL_NOISE_TIMER   0x4000 /* allows the noise timing function */

Definition at line 784 of file supern_2.h.

#define PL_NOLCT   (0<<5) /* no LCT is performed */

Definition at line 802 of file supern_2.h.

#define PL_NP_ERR   0x8000 /* NP has requested to r/w an inv. r.*/

Definition at line 970 of file supern_2.h.

#define PL_NS_MAX   0x0d /* max. noise time before break (r/w)*/

Definition at line 724 of file supern_2.h.

#define PL_P_HLS   (2<<8) /* halt line state */

Definition at line 899 of file supern_2.h.

#define PL_P_ILS16   (3<<8) /* idle line state (after 16 idle s.)*/

Definition at line 900 of file supern_2.h.

#define PL_P_MLS   (1<<8) /* master line state */

Definition at line 898 of file supern_2.h.

#define PL_P_QLS   (0<<8) /* quiet line state */

Definition at line 897 of file supern_2.h.

#define PL_PARITY_ERR   0x0001 /* p. error h.b.detected on TX9-0 inp*/

Definition at line 955 of file supern_2.h.

#define PL_PC0   (0<<7) /* OFF - when /RST or PCM_CNTRL */

Definition at line 924 of file supern_2.h.

#define PL_PC1   (1<<7) /* BREAK - entry point in start PCM*/

Definition at line 925 of file supern_2.h.

#define PL_PC2   (2<<7) /* TRACE - to localize stuck Beacon*/

Definition at line 926 of file supern_2.h.

#define PL_PC3   (3<<7) /* CONNECT - synchronize ends of conn*/

Definition at line 927 of file supern_2.h.

#define PL_PC4   (4<<7) /* NEXT - to separate the signalng*/

Definition at line 928 of file supern_2.h.

#define PL_PC5   (5<<7) /* SIGNAL - PCM trans/rec. bit infos*/

Definition at line 929 of file supern_2.h.

#define PL_PC6   (6<<7) /* JOIN - 1. state to activ conn. */

Definition at line 930 of file supern_2.h.

#define PL_PC7   (7<<7) /* VERIFY - 2. - " - (3. ACTIVE) */

Definition at line 931 of file supern_2.h.

#define PL_PC8   (8<<7) /* ACTIVE - PHY has been incorporated*/

Definition at line 932 of file supern_2.h.

#define PL_PC9

Value:

(9<<7)      /* MAINT   - for test purposes or so 
                       that PCM op. completely in softw. */

Definition at line 933 of file supern_2.h.

#define PL_PC_JOIN   0x0010 /* if NEXT state --> JOIN state */

Definition at line 799 of file supern_2.h.

#define PL_PC_LOOP   0x0060 /* loopback used in the LCT */

Definition at line 801 of file supern_2.h.

#define PL_PCI_SCRUB   0x0800 /* scrubbing function is being exec. */

Definition at line 935 of file supern_2.h.

#define PL_PCI_STATE   0x3000 /* Physical Connect. Insertion SM */

Definition at line 937 of file supern_2.h.

#define PL_PCM_BREAK   0x0020 /* PCM has entered the BREAK state */

Definition at line 960 of file supern_2.h.

#define PL_PCM_CNTRL   0x0003 /* control PCM state machine */

Definition at line 791 of file supern_2.h.

#define PL_PCM_CODE   0x0004 /* transmit&receive | LCT complete */

Definition at line 957 of file supern_2.h.

#define PL_PCM_ENABLED   0x0040 /* asserted SC_JOIN, scrub. & ACTIV */

Definition at line 961 of file supern_2.h.

#define PL_PCM_NAF   (0) /* state is not affected */

Definition at line 792 of file supern_2.h.

#define PL_PCM_SIGNAL   0x0040 /* indic. that XMIT_VECTOR hb.written*/

Definition at line 921 of file supern_2.h.

#define PL_PCM_START   (1) /* goes to the BREAK state */

Definition at line 793 of file supern_2.h.

#define PL_PCM_STATE   0x0780 /* state bits of PCM state machine */

Definition at line 923 of file supern_2.h.

#define PL_PCM_STOP   (3) /* goes to the OFF state */

Definition at line 795 of file supern_2.h.

#define PL_PCM_TRACE   (2) /* goes to the TRACE state */

Definition at line 794 of file supern_2.h.

#define PL_PHYINV   0x0400 /* physical layer invalid signal */

Definition at line 965 of file supern_2.h.

#define PL_PREV_LINE_ST   0x0300 /* value of previous line state */

Definition at line 896 of file supern_2.h.

#define PL_RCF   0x0010 /* receive code flag (start exec.) */

Definition at line 919 of file supern_2.h.

#define PL_RCV_VECTOR   0x16 /* receive vector reg. (read only) */

Definition at line 733 of file supern_2.h.

#define PL_REQ_SCRUB   0x0800 /* limited access to scrub capability*/

Definition at line 781 of file supern_2.h.

#define PL_RF_DISABLE   0x0002 /* disable the Repeat Filter state m.*/

Definition at line 771 of file supern_2.h.

#define PL_RF_HALT1   (2<<14) /* HALT1 */

Definition at line 946 of file supern_2.h.

#define PL_RF_HALT2   (3<<14) /* HALT2 */

Definition at line 947 of file supern_2.h.

#define PL_RF_IDLE   (1<<14) /* IDLE */

Definition at line 945 of file supern_2.h.

#define PL_RF_REPT   (0<<14) /* REPEAT */

Definition at line 944 of file supern_2.h.

#define PL_RF_STATE   0xc000 /* state bit of repeate filter SM */

Definition at line 943 of file supern_2.h.

#define PL_RLBP   (3<<5) /* trans. PDR & remote loopb. path */

Definition at line 805 of file supern_2.h.

#define PL_RUN_BIST   0x0001 /* begin running its Built In Self T.*/

Definition at line 770 of file supern_2.h.

#define PL_SC_BYPASS   0x0008 /* by providing a physical bypass */

Definition at line 773 of file supern_2.h.

#define PL_SC_REM_LOOP   0x0004 /* remote loopback path */

Definition at line 772 of file supern_2.h.

#define PL_SELF_TEST   0x0010 /* QUIET|HALT while PCM in TRACE st. */

Definition at line 959 of file supern_2.h.

#define PL_SIGNAL_DET   0x0400 /* 1=that signal detect is deasserted*/

Definition at line 902 of file supern_2.h.

#define PL_STATUS_A   0x10 /* status register A (read only) */

Definition at line 727 of file supern_2.h.

#define PL_STATUS_B   0x11 /* status register B (read only) */

Definition at line 728 of file supern_2.h.

#define PL_SYM_PR_CTR   0x0007 /* contains the LSM symbol pair Ctr. */

Definition at line 882 of file supern_2.h.

#define PL_T_OUT   0x09 /* signal timeout (r/w) */

Definition at line 720 of file supern_2.h.

#define PL_T_SCRUB   0x0c /* scrub time = MAC TVX (r/w) */

Definition at line 723 of file supern_2.h.

#define PL_TB_MIN   0x08 /* minimum break time (r/w) */

Definition at line 719 of file supern_2.h.

#define PL_TCF   0x0008 /* transmit code flag (start exec.) */

Definition at line 918 of file supern_2.h.

#define PL_TIDLE   (2<<5) /* PCM asserts transmit idle */

Definition at line 804 of file supern_2.h.

#define PL_TL_MIN   0x07 /* min. line state transmit t. (r/w) */

Definition at line 718 of file supern_2.h.

#define PL_TNE   0x13 /* time of noise event [0.32 us] */

Definition at line 730 of file supern_2.h.

#define PL_TNE_16BIT   0x2000 /* causes the TNE as a 16 bit timer */

Definition at line 783 of file supern_2.h.

#define PL_TNE_EXPIRED   0x0100 /* TNE timer reached zero */

Definition at line 963 of file supern_2.h.

#define PL_TNE_LOAD_V   0x0f /* TNE timer load value (write only) */

Definition at line 726 of file supern_2.h.

#define PL_TPC   0x12 /* timer for PCM (ro) [20.48 us] */

Definition at line 729 of file supern_2.h.

#define PL_TPC_16BIT   0x1000 /* causes the TPC as a 16 bit timer */

Definition at line 782 of file supern_2.h.

#define PL_TPC_EXPIRED   0x0080 /* TPC timer reached zero */

Definition at line 962 of file supern_2.h.

#define PL_TPC_LOAD_V   0x0e /* TPC timer load value (write only) */

Definition at line 725 of file supern_2.h.

#define PL_TPDR   (1<<5) /* PCM asserts transmit PDR */

Definition at line 803 of file supern_2.h.

#define PL_TRACE_PROP   0x0008 /* master l.s. while PCM ACTIV|TRACE */

Definition at line 958 of file supern_2.h.

#define PL_UNKN_LINE_ST   0x0008 /* unknown line state bit from LSM */

Definition at line 883 of file supern_2.h.

#define PL_VECTOR_LEN   0x04 /* transmit vector length (r/w) */

Definition at line 715 of file supern_2.h.

#define PL_VIOL_SYM_CTR   0x18 /* violation symbol count. (read o) */

Definition at line 735 of file supern_2.h.

#define PL_VSYM_CTR   0x0800 /* violation symbol counter has incr.*/

Definition at line 966 of file supern_2.h.

#define PL_VSYM_CTR_INT   0x0200 /* controls when int bit is asserted */

Definition at line 779 of file supern_2.h.

#define PL_XMIT_VECTOR   0x03 /* transmit vector register (r/w) */

Definition at line 714 of file supern_2.h.

#define PLC_BIST   0x6ecd /* BIST signature for PLC */

Definition at line 1019 of file supern_2.h.

#define PLC_CAM_A_BIST   0x9e75 /* BIST signature of CAMEL Rev. A */

Definition at line 1023 of file supern_2.h.

#define PLC_CAM_B_BIST   0x5b6b /* BIST signature of CAMEL Rev. B */

Definition at line 1024 of file supern_2.h.

#define PLC_ELM_B_BIST   0x6ecd /* BIST signature of ELM Rev. B */

Definition at line 1021 of file supern_2.h.

#define PLC_ELM_D_BIST   0x5b6b /* BIST signature of ELM Rev. D */

Definition at line 1022 of file supern_2.h.

#define PLC_IFD_A_BIST   0x9e75 /* BIST signature of IFDDI Rev. A */

Definition at line 1025 of file supern_2.h.

#define PLC_IFD_B_BIST   0x5b6b /* BIST signature of IFDDI Rev. B */

Definition at line 1026 of file supern_2.h.

#define PLC_QELM_A_BIST   0x5b6b /* BIST signature of QELM Rev. A */

Definition at line 1027 of file supern_2.h.

#define PLC_REV_MASK   0xf800 /* revision bits in status A */

Definition at line 877 of file supern_2.h.

#define PLC_REV_SN3   0x7800 /* revision bits for PLC-S in IFCP */

Definition at line 880 of file supern_2.h.

#define PLC_REVISION_A   0x0000 /* revision bits for PLC */

Definition at line 878 of file supern_2.h.

#define PLC_REVISION_S   0xf800 /* revision bits for PLC-S */

Definition at line 879 of file supern_2.h.

#define PLCS_BIST   0x5b6b /* BIST signature for PLC-S */

Definition at line 1020 of file supern_2.h.

#define RD_FRM_IMPA   (unsigned long)(2<<20)

Definition at line 149 of file supern_2.h.

#define RD_FRM_IMPS   (unsigned long)(6<<20)

Definition at line 152 of file supern_2.h.

#define RD_FRM_LLCA   (unsigned long)(1<<20)

Definition at line 148 of file supern_2.h.

#define RD_FRM_LLCS   (unsigned long)(5<<20)

Definition at line 151 of file supern_2.h.

#define RD_FRM_MAC   (unsigned long)(4<<20) /* synchr. frames */

Definition at line 150 of file supern_2.h.

#define RD_FRM_SMT   (unsigned long)(0<<20) /* asynchr. frames */

Definition at line 147 of file supern_2.h.

#define RD_LENGTH   0x0000ffffL

Definition at line 143 of file supern_2.h.

#define RD_S_ERFBB   0x00030000L /* received frame byte boundary */

Definition at line 128 of file supern_2.h.

#define RD_S_MSRABT   0x40000000L /* memory status receive abort */

Definition at line 139 of file supern_2.h.

#define RD_S_MSVALID   0x80000000L /* memory status valid */

Definition at line 140 of file supern_2.h.

#define RD_S_RES1   0x20000000L /* reserved */

Definition at line 138 of file supern_2.h.

#define RD_S_RES2   0x000c0000L /* reserved */

Definition at line 129 of file supern_2.h.

#define RD_S_SADRRG   0x00800000L /* DA == MA or broad-/multicast */

Definition at line 131 of file supern_2.h.

#define RD_S_SEAC   0x0e000000L /* frame status indicators */

Definition at line 133 of file supern_2.h.

#define RD_S_SEAC0   0x02000000L /* frame-copied case-indicator */

Definition at line 134 of file supern_2.h.

#define RD_S_SEAC1   0x04000000L /* address-match A-indicator */

Definition at line 135 of file supern_2.h.

#define RD_S_SEAC2   0x08000000L /* frame-error E-indicator */

Definition at line 136 of file supern_2.h.

#define RD_S_SFRMERR   0x01000000L /* received frame not valid */

Definition at line 132 of file supern_2.h.

#define RD_S_SFRMTY   0x00700000L /* frame type bits */

Definition at line 130 of file supern_2.h.

#define RD_S_SSRCRTG   0x10000000L /* == 1 SA has MSB set */

Definition at line 137 of file supern_2.h.

#define RD_STATUS   0xffff0000L

Definition at line 142 of file supern_2.h.

#define RQ_NOT   0 /* not request */

Definition at line 1037 of file supern_2.h.

#define RQ_RES   1 /* reserved */

Definition at line 1038 of file supern_2.h.

#define RQ_RRQ   3 /* read request: receive queue */

Definition at line 1040 of file supern_2.h.

#define RQ_SFW   2 /* special frame write */

Definition at line 1039 of file supern_2.h.

#define RQ_WA0   5 /* write requ.: asynchronous queue 0 */

Definition at line 1042 of file supern_2.h.

#define RQ_WA1   6 /* write requ.: asynchronous queue 1 */

Definition at line 1043 of file supern_2.h.

#define RQ_WA2   7 /* write requ.: asynchronous queue 2 */

Definition at line 1044 of file supern_2.h.

#define RQ_WSQ   4 /* write request: synchronous queue */

Definition at line 1041 of file supern_2.h.

#define RX_FS_A   ((long)FS_SEAC1<<16) /* address indicator */

Definition at line 80 of file supern_2.h.

#define RX_FS_ADDRESS   ((long)FS_SADRRG<<16) /* address recognized */

Definition at line 83 of file supern_2.h.

#define RX_FS_C   ((long)FS_SEAC0<<16) /* copy indicator */

Definition at line 81 of file supern_2.h.

#define RX_FS_CRC   ((long)FS_SFRMERR<<16)/* error detected */

Definition at line 82 of file supern_2.h.

#define RX_FS_E   ((long)FS_SEAC2<<16) /* error indicator */

Definition at line 79 of file supern_2.h.

#define RX_FS_IMPL   ((long)FS_SFRMTY1<<16)/* implementer frame */

Definition at line 86 of file supern_2.h.

#define RX_FS_LLC   ((long)FS_SFRMTY0<<16)/* LLC frame */

Definition at line 87 of file supern_2.h.

#define RX_FS_MAC   ((long)FS_SFRMTY2<<16)/* MAC frame */

Definition at line 84 of file supern_2.h.

#define RX_FS_SMT   ((long)0<<16) /* SMT frame */

Definition at line 85 of file supern_2.h.

#define RX_MSRABT   ((long)1<<30) /* memory status receive abort */

Definition at line 78 of file supern_2.h.

#define RX_MSVALID   ((long)1<<31) /* memory status valid */

Definition at line 77 of file supern_2.h.

#define SZ_LONG   (sizeof(long))

Definition at line 1046 of file supern_2.h.

#define TD_C_DESCR   0x60000000L /* must be TXP1 */

Definition at line 189 of file supern_2.h.

#define TD_C_LNCN   0x0000ffffL /* frame length lower/upper byte */

Definition at line 197 of file supern_2.h.

#define TD_C_LNCNL   0x000000ffL

Definition at line 196 of file supern_2.h.

#define TD_C_LNCNU   0x0000ff00L

Definition at line 195 of file supern_2.h.

#define TD_C_MORE   0x80000000L /* more frame in chain */

Definition at line 188 of file supern_2.h.

#define TD_C_NFCS   0x02000000L /* no frame check sequence */

Definition at line 192 of file supern_2.h.

#define TD_C_TXFBB   0x18000000L /* byte offset */

Definition at line 190 of file supern_2.h.

#define TD_C_XDONE   0x04000000L /* give up token */

Definition at line 191 of file supern_2.h.

#define TD_C_XMTABT   0x01000000L /* transmit abort */

Definition at line 193 of file supern_2.h.

#define TD_P_CNTRL   0xff000000L

Definition at line 218 of file supern_2.h.

#define TD_P_RPX   0x0000ffffL

Definition at line 221 of file supern_2.h.

#define TD_P_RPXL   0x000000ffL

Definition at line 220 of file supern_2.h.

#define TD_P_RPXU   0x0000ff00L

Definition at line 219 of file supern_2.h.

#define TP_C_MIN   0xff9c /* 2 ms */

Definition at line 1007 of file supern_2.h.

#define TP_LC_LENGTH   0xf676 /* 50 ms */

Definition at line 1011 of file supern_2.h.

#define TP_LC_LONGLN   0xa0a2 /* 500 ms */

Definition at line 1012 of file supern_2.h.

#define TP_NS_MAX   0xf021 /* 1.3 ms */

Definition at line 1014 of file supern_2.h.

#define TP_T_OUT   0xd9db /* 200 ms */

Definition at line 1010 of file supern_2.h.

#define TP_T_SCRUB   0xff6d /* 3.5 ms */

Definition at line 1013 of file supern_2.h.

#define TP_TB_MIN   0xff10 /* 5 ms */

Definition at line 1009 of file supern_2.h.

#define TP_TL_MIN   0xfff0 /* 0.3 ms */

Definition at line 1008 of file supern_2.h.

#define TX_DESCRIPTOR   0x40000000L

Definition at line 154 of file supern_2.h.

#define TX_INT_PATTERN   0xa0000000L

Definition at line 226 of file supern_2.h.

#define TX_OFFSET_3   0x18000000L

Definition at line 155 of file supern_2.h.

#define TX_PATTERN   0xa0

Definition at line 224 of file supern_2.h.

#define TX_POINTER_END   0xa0000000L

Definition at line 225 of file supern_2.h.

#define TXP1   2

Definition at line 157 of file supern_2.h.