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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Data Structures | |
| struct | slic_rcvbuf |
| struct | slic_hddr_wds |
| struct | slic_host64sg |
| struct | slic_host64_cmd |
| struct | slic_rspbuf |
| struct | slic_regs |
| struct | inicpm_wakepattern |
| struct | inicpm_state |
| struct | slicpm_packet_pattern |
| struct | slicpm_wakeup_capabilities |
| struct | slic_pnp_capabilities |
| struct | xmt_stats |
| struct | rcv_stats |
| struct | xmt_statsgb |
| struct | rcv_statsgb |
| struct | slic_stats |
| struct | slic_config_mac |
| struct | atk_fru |
| struct | vendor1_fru |
| struct | vendor2_fru |
| struct | vendor3_fru |
| struct | vendor4_fru |
| union | oemfru |
| struct | slic_eeprom |
| struct | oslic_eeprom |
| struct | slic_config |
Macros | |
| #define | PCI_VENDOR_ID_ALACRITECH 0x139A |
| #define | SLIC_1GB_DEVICE_ID 0x0005 |
| #define | SLIC_2GB_DEVICE_ID 0x0007 /* Oasis Device ID */ |
| #define | SLIC_1GB_CICADA_SUBSYS_ID 0x0008 |
| #define | SLIC_NBR_MACS 4 |
| #define | SLIC_RCVBUF_SIZE 2048 |
| #define | SLIC_RCVBUF_HEADSIZE 34 |
| #define | SLIC_RCVBUF_TAILSIZE 0 |
| #define | SLIC_RCVBUF_DATASIZE |
| #define | VGBSTAT_XPERR 0x40000000 |
| #define | VGBSTAT_XERRSHFT 25 |
| #define | VGBSTAT_XCSERR 0x23 |
| #define | VGBSTAT_XUFLOW 0x22 |
| #define | VGBSTAT_XHLEN 0x20 |
| #define | VGBSTAT_NETERR 0x01000000 |
| #define | VGBSTAT_NERRSHFT 16 |
| #define | VGBSTAT_NERRMSK 0x1ff |
| #define | VGBSTAT_NCSERR 0x103 |
| #define | VGBSTAT_NUFLOW 0x102 |
| #define | VGBSTAT_NHLEN 0x100 |
| #define | VGBSTAT_LNKERR 0x00000080 |
| #define | VGBSTAT_LERRMSK 0xff |
| #define | VGBSTAT_LDEARLY 0x86 |
| #define | VGBSTAT_LBOFLO 0x85 |
| #define | VGBSTAT_LCODERR 0x84 |
| #define | VGBSTAT_LDBLNBL 0x83 |
| #define | VGBSTAT_LCRCERR 0x82 |
| #define | VGBSTAT_LOFLO 0x81 |
| #define | VGBSTAT_LUFLO 0x80 |
| #define | IRHDDR_FLEN_MSK 0x0000ffff |
| #define | IRHDDR_SVALID 0x80000000 |
| #define | IRHDDR_ERR 0x10000000 |
| #define | VRHSTAT_802OE 0x80000000 |
| #define | VRHSTAT_TPOFLO 0x10000000 |
| #define | VRHSTATB_802UE 0x80000000 |
| #define | VRHSTATB_RCVE 0x40000000 |
| #define | VRHSTATB_BUFF 0x20000000 |
| #define | VRHSTATB_CARRE 0x08000000 |
| #define | VRHSTATB_LONGE 0x02000000 |
| #define | VRHSTATB_PREA 0x01000000 |
| #define | VRHSTATB_CRC 0x00800000 |
| #define | VRHSTATB_DRBL 0x00400000 |
| #define | VRHSTATB_CODE 0x00200000 |
| #define | VRHSTATB_TPCSUM 0x00100000 |
| #define | VRHSTATB_TPHLEN 0x00080000 |
| #define | VRHSTATB_IPCSUM 0x00040000 |
| #define | VRHSTATB_IPLERR 0x00020000 |
| #define | VRHSTATB_IPHERR 0x00010000 |
| #define | SLIC_MAX64_BCNT 23 |
| #define | SLIC_MAX32_BCNT 26 |
| #define | IHCMD_XMT_REQ 0x01 |
| #define | IHFLG_IFSHFT 2 |
| #define | SLIC_RSPBUF_SIZE 32 |
| #define | SLIC_RESET_MAGIC 0xDEAD |
| #define | ICR_INT_OFF 0 |
| #define | ICR_INT_ON 1 |
| #define | ICR_INT_MASK 2 |
| #define | ISR_ERR 0x80000000 |
| #define | ISR_RCV 0x40000000 |
| #define | ISR_CMD 0x20000000 |
| #define | ISR_IO 0x60000000 |
| #define | ISR_UPC 0x10000000 |
| #define | ISR_LEVENT 0x08000000 |
| #define | ISR_RMISS 0x02000000 |
| #define | ISR_UPCERR 0x01000000 |
| #define | ISR_XDROP 0x00800000 |
| #define | ISR_UPCBSY 0x00020000 |
| #define | ISR_EVMSK 0xffff0000 |
| #define | ISR_PINGMASK 0x00700000 |
| #define | ISR_PINGDSMASK 0x00710000 |
| #define | ISR_UPCMASK 0x11000000 |
| #define | SLIC_WCS_START 0x80000000 |
| #define | SLIC_WCS_COMPARE 0x40000000 |
| #define | SLIC_RCVWCS_BEGIN 0x40000000 |
| #define | SLIC_RCVWCS_FINISH 0x80000000 |
| #define | SLIC_PM_MAXPATTERNS 6 |
| #define | SLIC_PM_PATTERNSIZE 128 |
| #define | SLIC_PMCAPS_WAKEONLAN 0x00000001 |
| #define | MIICR_REG_PCR 0x00000000 |
| #define | MIICR_REG_4 0x00040000 |
| #define | MIICR_REG_9 0x00090000 |
| #define | MIICR_REG_16 0x00100000 |
| #define | PCR_RESET 0x8000 |
| #define | PCR_POWERDOWN 0x0800 |
| #define | PCR_SPEED_100 0x2000 |
| #define | PCR_SPEED_1000 0x0040 |
| #define | PCR_AUTONEG 0x1000 |
| #define | PCR_AUTONEG_RST 0x0200 |
| #define | PCR_DUPLEX_FULL 0x0100 |
| #define | PSR_LINKUP 0x0004 |
| #define | PAR_ADV100FD 0x0100 |
| #define | PAR_ADV100HD 0x0080 |
| #define | PAR_ADV10FD 0x0040 |
| #define | PAR_ADV10HD 0x0020 |
| #define | PAR_ASYMPAUSE 0x0C00 |
| #define | PAR_802_3 0x0001 |
| #define | PAR_ADV1000XFD 0x0020 |
| #define | PAR_ADV1000XHD 0x0040 |
| #define | PAR_ASYMPAUSE_FIBER 0x0180 |
| #define | PGC_ADV1000FD 0x0200 |
| #define | PGC_ADV1000HD 0x0100 |
| #define | SEEQ_LINKFAIL 0x4000 |
| #define | SEEQ_SPEED 0x0080 |
| #define | SEEQ_DUPLEX 0x0040 |
| #define | TDK_DUPLEX 0x0800 |
| #define | TDK_SPEED 0x0400 |
| #define | MRV_REG16_XOVERON 0x0068 |
| #define | MRV_REG16_XOVEROFF 0x0008 |
| #define | MRV_SPEED_1000 0x8000 |
| #define | MRV_SPEED_100 0x4000 |
| #define | MRV_SPEED_10 0x0000 |
| #define | MRV_FULLDUPLEX 0x2000 |
| #define | MRV_LINKUP 0x0400 |
| #define | GIG_LINKUP 0x0001 |
| #define | GIG_FULLDUPLEX 0x0002 |
| #define | GIG_SPEED_MASK 0x000C |
| #define | GIG_SPEED_1000 0x0008 |
| #define | GIG_SPEED_100 0x0004 |
| #define | GIG_SPEED_10 0x0000 |
| #define | MCR_RESET 0x80000000 |
| #define | MCR_CRCEN 0x40000000 |
| #define | MCR_FULLD 0x10000000 |
| #define | MCR_PAD 0x02000000 |
| #define | MCR_RETRYLATE 0x01000000 |
| #define | MCR_BOL_SHIFT 21 |
| #define | MCR_IPG1_SHIFT 14 |
| #define | MCR_IPG2_SHIFT 7 |
| #define | MCR_IPG3_SHIFT 0 |
| #define | GMCR_RESET 0x80000000 |
| #define | GMCR_GBIT 0x20000000 |
| #define | GMCR_FULLD 0x10000000 |
| #define | GMCR_GAPBB_SHIFT 14 |
| #define | GMCR_GAPR1_SHIFT 7 |
| #define | GMCR_GAPR2_SHIFT 0 |
| #define | GMCR_GAPBB_1000 0x60 |
| #define | GMCR_GAPR1_1000 0x2C |
| #define | GMCR_GAPR2_1000 0x40 |
| #define | GMCR_GAPBB_100 0x70 |
| #define | GMCR_GAPR1_100 0x2C |
| #define | GMCR_GAPR2_100 0x40 |
| #define | XCR_RESET 0x80000000 |
| #define | XCR_XMTEN 0x40000000 |
| #define | XCR_PAUSEEN 0x20000000 |
| #define | XCR_LOADRNG 0x10000000 |
| #define | RCR_RESET 0x80000000 |
| #define | RCR_RCVEN 0x40000000 |
| #define | RCR_RCVALL 0x20000000 |
| #define | RCR_RCVBAD 0x10000000 |
| #define | RCR_CTLEN 0x08000000 |
| #define | RCR_ADDRAEN 0x02000000 |
| #define | GXCR_RESET 0x80000000 |
| #define | GXCR_XMTEN 0x40000000 |
| #define | GXCR_PAUSEEN 0x20000000 |
| #define | GRCR_RESET 0x80000000 |
| #define | GRCR_RCVEN 0x40000000 |
| #define | GRCR_RCVALL 0x20000000 |
| #define | GRCR_RCVBAD 0x10000000 |
| #define | GRCR_CTLEN 0x08000000 |
| #define | GRCR_ADDRAEN 0x02000000 |
| #define | GRCR_HASHSIZE_SHIFT 17 |
| #define | GRCR_HASHSIZE 14 |
| #define | SLIC_EEPROM_ID 0xA5A5 |
| #define | SLIC_SRAM_SIZE2GB (64 * 1024) |
| #define | SLIC_SRAM_SIZE1GB (32 * 1024) |
| #define | SLIC_HOSTID_DEFAULT 0xFFFF /* uninitialized hostid */ |
| #define | SLIC_NBR_MACS 4 |
| #define | frame_status14 u0.hdrs_14port.frame_status |
| #define | frame_status_b14 u0.hdrs_14port.frame_status_b |
| #define | frame_statusGB u0.hdrs_gbit.frame_status |
| #define | SLIC_ICR 0x0008 |
| #define | SLIC_ISP 0x0010 |
| #define | SLIC_ISR 0x0018 |
| #define | SLIC_HBAR 0x0020 |
| #define | SLIC_HBAR_CNT_MSK 0x000000FF |
| #define | SLIC_DBAR 0x0028 |
| #define | SLIC_DBAR_SIZE 2048 |
| #define | SLIC_CBAR 0x0030 |
| #define | SLIC_CBAR_LEN_MSK 0x0000001F |
| #define | SLIC_CBAR_ALIGN 0x00000020 |
| #define | SLIC_WCS 0x0034 |
| #define | SLIC_WCS_START 0x80000000 /*Start the SLIC (Jump to WCS)*/ |
| #define | SLIC_WCS_COMPARE 0x40000000 /* Compare with value in WCS*/ |
| #define | SLIC_RBAR 0x0038 |
| #define | SLIC_RBAR_CNT_MSK 0x000000FF |
| #define | SLIC_RBAR_SIZE 32 |
| #define | SLIC_RSTAT 0x0040 |
| #define | SLIC_LSTAT 0x0048 |
| #define | SLIC_WMCFG 0x0050 |
| #define | SLIC_WPHY 0x0058 |
| #define | SLIC_RCBAR 0x0060 |
| #define | SLIC_RCONFIG 0x0068 |
| #define | SLIC_INTAGG 0x0070 |
| #define | SLIC_WXCFG 0x0078 |
| #define | SLIC_WRCFG 0x0080 |
| #define | SLIC_WRADDRAL 0x0088 |
| #define | SLIC_WRADDRAH 0x0090 |
| #define | SLIC_WRADDRBL 0x0098 |
| #define | SLIC_WRADDRBH 0x00a0 |
| #define | SLIC_MCASTLOW 0x00a8 |
| #define | SLIC_MCASTHIGH 0x00b0 |
| #define | SLIC_PING 0x00b8 |
| #define | SLIC_DUMP_CMD 0x00c0 |
| #define | SLIC_DUMP_DATA 0x00c8 |
| #define | SLIC_PCISTATUS 0x00d0 |
| #define | SLIC_WRHOSTID 0x00d8 |
| #define | SLIC_RDHOSTID_1GB 0x1554 |
| #define | SLIC_RDHOSTID_2GB 0x1554 |
| #define | SLIC_LOW_POWER 0x00e0 |
| #define | SLIC_QUIESCE 0x00e8 |
| #define | SLIC_RESET_IFACE 0x00f0 |
| #define | SLIC_ADDR_UPPER 0x00f8 /*Register is only written when it has changed*/ |
| #define | SLIC_HBAR64 0x0100 |
| #define | SLIC_DBAR64 0x0108 |
| #define | SLIC_CBAR64 0x0110 |
| #define | SLIC_RBAR64 0x0118 |
| #define | SLIC_RCBAR64 0x0120 |
| #define | SLIC_RSTAT64 0x0128 |
| #define | SLIC_RCV_WCS 0x0130 |
| #define | SLIC_RCVWCS_BEGIN 0x40000000 |
| #define | SLIC_RCVWCS_FINISH 0x80000000 |
| #define | SLIC_WRVLANID 0x0138 |
| #define | SLIC_READ_XF_INFO 0x0140 |
| #define | SLIC_WRITE_XF_INFO 0x0148 |
| #define | SLIC_TICKS_PER_SEC 0x0170 |
| #define | xmit_tcp_segs100 u.stats_100.xmt100.xmit_tcp_segs |
| #define | xmit_tcp_bytes100 u.stats_100.xmt100.xmit_tcp_bytes |
| #define | xmit_bytes100 u.stats_100.xmt100.xmit_bytes |
| #define | xmit_collisions100 u.stats_100.xmt100.xmit_collisions |
| #define | xmit_unicasts100 u.stats_100.xmt100.xmit_unicasts |
| #define | xmit_other_error100 u.stats_100.xmt100.xmit_other_error |
| #define | xmit_excess_collisions100 u.stats_100.xmt100.xmit_excess_collisions |
| #define | rcv_tcp_segs100 u.stats_100.rcv100.rcv_tcp_segs |
| #define | rcv_tcp_bytes100 u.stats_100.rcv100.rcv_tcp_bytes |
| #define | rcv_bytes100 u.stats_100.rcv100.rcv_bytes |
| #define | rcv_unicasts100 u.stats_100.rcv100.rcv_unicasts |
| #define | rcv_other_error100 u.stats_100.rcv100.rcv_other_error |
| #define | rcv_drops100 u.stats_100.rcv100.rcv_drops |
| #define | xmit_tcp_segs_gb u.stats_GB.xmtGB.xmit_tcp_segs |
| #define | xmit_tcp_bytes_gb u.stats_GB.xmtGB.xmit_tcp_bytes |
| #define | xmit_bytes_gb u.stats_GB.xmtGB.xmit_bytes |
| #define | xmit_collisions_gb u.stats_GB.xmtGB.xmit_collisions |
| #define | xmit_unicasts_gb u.stats_GB.xmtGB.xmit_unicasts |
| #define | xmit_other_error_gb u.stats_GB.xmtGB.xmit_other_error |
| #define | xmit_excess_collisions_gb u.stats_GB.xmtGB.xmit_excess_collisions |
| #define | rcv_tcp_segs_gb u.stats_GB.rcvGB.rcv_tcp_segs |
| #define | rcv_tcp_bytes_gb u.stats_GB.rcvGB.rcv_tcp_bytes |
| #define | rcv_bytes_gb u.stats_GB.rcvGB.rcv_bytes |
| #define | rcv_unicasts_gb u.stats_GB.rcvGB.rcv_unicasts |
| #define | rcv_other_error_gb u.stats_GB.rcvGB.rcv_other_error |
| #define | rcv_drops_gb u.stats_GB.rcvGB.rcv_drops |
| #define | ATK_FRU_FORMAT 0x00 |
| #define | VENDOR1_FRU_FORMAT 0x01 |
| #define | VENDOR2_FRU_FORMAT 0x02 |
| #define | VENDOR3_FRU_FORMAT 0x03 |
| #define | VENDOR4_FRU_FORMAT 0x04 |
| #define | NO_FRU_FORMAT 0xFF |
| #define | MAX_EECODE_SIZE sizeof(struct slic_eeprom) |
| #define | MIN_EECODE_SIZE 0x62 /* code size without optional OEM FRU stuff */ |
| #define frame_status14 u0.hdrs_14port.frame_status |
| #define frame_statusGB u0.hdrs_gbit.frame_status |
| #define MAX_EECODE_SIZE sizeof(struct slic_eeprom) |
| #define MIN_EECODE_SIZE 0x62 /* code size without optional OEM FRU stuff */ |
| #define rcv_other_error100 u.stats_100.rcv100.rcv_other_error |
| #define rcv_other_error_gb u.stats_GB.rcvGB.rcv_other_error |
| #define SLIC_ADDR_UPPER 0x00f8 /*Register is only written when it has changed*/ |
| #define SLIC_HOSTID_DEFAULT 0xFFFF /* uninitialized hostid */ |
| #define SLIC_RCVBUF_DATASIZE |
| #define SLIC_WCS_COMPARE 0x40000000 /* Compare with value in WCS*/ |
| #define SLIC_WCS_START 0x80000000 /*Start the SLIC (Jump to WCS)*/ |
| #define xmit_collisions100 u.stats_100.xmt100.xmit_collisions |
| #define xmit_collisions_gb u.stats_GB.xmtGB.xmit_collisions |
| #define xmit_excess_collisions100 u.stats_100.xmt100.xmit_excess_collisions |
| #define xmit_excess_collisions_gb u.stats_GB.xmtGB.xmit_excess_collisions |
| #define xmit_other_error100 u.stats_100.xmt100.xmit_other_error |
| #define xmit_other_error_gb u.stats_GB.xmtGB.xmit_other_error |
| #define xmit_tcp_bytes100 u.stats_100.xmt100.xmit_tcp_bytes |
| enum slicpm_power_state |
| enum UPR_REQUEST |
1.8.2