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Linux Kernel
3.7.1
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#include <linux/kernel.h>#include <linux/mm.h>#include <linux/init.h>#include <linux/delay.h>#include <asm/hwrpb.h>#include <asm/io.h>#include <asm/segment.h>Go to the source code of this file.
Macros | |
| #define | SMC_DEBUG 0 |
| #define | DBG_DEVS(args) |
| #define | KB 1024 |
| #define | MB (1024*KB) |
| #define | GB (1024*MB) |
| #define | DEVICE_ON 1 |
| #define | DEVICE_OFF 0 |
| #define | CONFIG_ON_KEY 0x55 |
| #define | CONFIG_OFF_KEY 0xaa |
| #define | FDC 0 |
| #define | IDE1 1 |
| #define | IDE2 2 |
| #define | PARP 3 |
| #define | SER1 4 |
| #define | SER2 5 |
| #define | RTCL 6 |
| #define | KYBD 7 |
| #define | AUXIO 8 |
| #define | CONFIG_CONTROL 0x02 |
| #define | INDEX_ADDRESS 0x03 |
| #define | LOGICAL_DEVICE_NUMBER 0x07 |
| #define | DEVICE_ID 0x20 |
| #define | DEVICE_REV 0x21 |
| #define | POWER_CONTROL 0x22 |
| #define | POWER_MGMT 0x23 |
| #define | OSC 0x24 |
| #define | ACTIVATE 0x30 |
| #define | ADDR_HI 0x60 |
| #define | ADDR_LO 0x61 |
| #define | INTERRUPT_SEL 0x70 |
| #define | INTERRUPT_SEL_2 0x72 /* KYBD/MOUS only */ |
| #define | DMA_CHANNEL_SEL 0x74 /* FDC/PARP only */ |
| #define | FDD_MODE_REGISTER 0x90 |
| #define | FDD_OPTION_REGISTER 0x91 |
| #define | VALID_DEVICE_ID 2 |
| #define | KYBD_INTERRUPT 1 |
| #define | MOUS_INTERRUPT 12 |
| #define | COM2_BASE 0x2f8 |
| #define | COM2_INTERRUPT 3 |
| #define | COM1_BASE 0x3f8 |
| #define | COM1_INTERRUPT 4 |
| #define | PARP_BASE 0x3bc |
| #define | PARP_INTERRUPT 7 |
| #define | NUM_RETRIES 5 |
Functions | |
| int __init | SMC93x_Init (void) |
| #define ACTIVATE 0x30 |
Definition at line 56 of file smc37c93x.c.
| #define ADDR_HI 0x60 |
Definition at line 57 of file smc37c93x.c.
| #define ADDR_LO 0x61 |
Definition at line 58 of file smc37c93x.c.
| #define AUXIO 8 |
Definition at line 44 of file smc37c93x.c.
| #define COM1_BASE 0x3f8 |
Definition at line 74 of file smc37c93x.c.
| #define COM1_INTERRUPT 4 |
Definition at line 75 of file smc37c93x.c.
| #define COM2_BASE 0x2f8 |
Definition at line 72 of file smc37c93x.c.
| #define COM2_INTERRUPT 3 |
Definition at line 73 of file smc37c93x.c.
| #define CONFIG_CONTROL 0x02 |
Definition at line 47 of file smc37c93x.c.
| #define CONFIG_OFF_KEY 0xaa |
Definition at line 33 of file smc37c93x.c.
| #define CONFIG_ON_KEY 0x55 |
Definition at line 32 of file smc37c93x.c.
| #define DBG_DEVS | ( | args | ) |
Definition at line 20 of file smc37c93x.c.
| #define DEVICE_ID 0x20 |
Definition at line 50 of file smc37c93x.c.
| #define DEVICE_OFF 0 |
Definition at line 29 of file smc37c93x.c.
| #define DEVICE_ON 1 |
Definition at line 28 of file smc37c93x.c.
| #define DEVICE_REV 0x21 |
Definition at line 51 of file smc37c93x.c.
| #define DMA_CHANNEL_SEL 0x74 /* FDC/PARP only */ |
Definition at line 61 of file smc37c93x.c.
| #define FDC 0 |
Definition at line 36 of file smc37c93x.c.
| #define FDD_MODE_REGISTER 0x90 |
Definition at line 63 of file smc37c93x.c.
| #define FDD_OPTION_REGISTER 0x91 |
Definition at line 64 of file smc37c93x.c.
| #define GB (1024*MB) |
Definition at line 25 of file smc37c93x.c.
| #define IDE1 1 |
Definition at line 37 of file smc37c93x.c.
| #define IDE2 2 |
Definition at line 38 of file smc37c93x.c.
| #define INDEX_ADDRESS 0x03 |
Definition at line 48 of file smc37c93x.c.
| #define INTERRUPT_SEL 0x70 |
Definition at line 59 of file smc37c93x.c.
| #define INTERRUPT_SEL_2 0x72 /* KYBD/MOUS only */ |
Definition at line 60 of file smc37c93x.c.
| #define KB 1024 |
Definition at line 23 of file smc37c93x.c.
| #define KYBD 7 |
Definition at line 43 of file smc37c93x.c.
| #define KYBD_INTERRUPT 1 |
Definition at line 70 of file smc37c93x.c.
| #define LOGICAL_DEVICE_NUMBER 0x07 |
Definition at line 49 of file smc37c93x.c.
| #define MB (1024*KB) |
Definition at line 24 of file smc37c93x.c.
| #define MOUS_INTERRUPT 12 |
Definition at line 71 of file smc37c93x.c.
| #define NUM_RETRIES 5 |
| #define OSC 0x24 |
Definition at line 54 of file smc37c93x.c.
| #define PARP 3 |
Definition at line 39 of file smc37c93x.c.
| #define PARP_BASE 0x3bc |
Definition at line 76 of file smc37c93x.c.
| #define PARP_INTERRUPT 7 |
Definition at line 77 of file smc37c93x.c.
| #define POWER_CONTROL 0x22 |
Definition at line 52 of file smc37c93x.c.
| #define POWER_MGMT 0x23 |
Definition at line 53 of file smc37c93x.c.
| #define RTCL 6 |
Definition at line 42 of file smc37c93x.c.
| #define SER1 4 |
Definition at line 40 of file smc37c93x.c.
| #define SER2 5 |
Definition at line 41 of file smc37c93x.c.
| #define SMC_DEBUG 0 |
Definition at line 15 of file smc37c93x.c.
| #define VALID_DEVICE_ID 2 |
Definition at line 67 of file smc37c93x.c.
Definition at line 238 of file smc37c93x.c.
1.8.2