smc37c93x.h File Reference

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Data Structures
struct	uart_reg

Macros
#define	FDC_PRIMARY_BASE   0x3f0
#define	IDE1_PRIMARY_BASE   0x1f0
#define	IDE1_SECONDARY_BASE   0x170
#define	PARPORT_PRIMARY_BASE   0x378
#define	COM1_PRIMARY_BASE   0x2f8
#define	COM2_PRIMARY_BASE   0x3f8
#define	RTC_PRIMARY_BASE   0x070
#define	KBC_PRIMARY_BASE   0x060
#define	AUXIO_PRIMARY_BASE   0x000 /* XXX */
#define	LDN_FDC   0
#define	LDN_IDE1   1
#define	LDN_IDE2   2
#define	LDN_PARPORT   3
#define	LDN_COM1   4
#define	LDN_COM2   5
#define	LDN_RTC   6
#define	LDN_KBC   7
#define	LDN_AUXIO   8
#define	CONFIG_PORT   0x3f0
#define	INDEX_PORT   CONFIG_PORT
#define	DATA_PORT   0x3f1
#define	CONFIG_ENTER   0x55
#define	CONFIG_EXIT   0xaa
#define	CURRENT_LDN_INDEX   0x07
#define	POWER_CONTROL_INDEX   0x22
#define	ACTIVATE_INDEX   0x30
#define	IO_BASE_HI_INDEX   0x60
#define	IO_BASE_LO_INDEX   0x61
#define	IRQ_SELECT_INDEX   0x70
#define	DMA_SELECT_INDEX   0x74
#define	GPIO46_INDEX   0xc6
#define	GPIO47_INDEX   0xc7
#define	UART_RBR   0x0 /* Receiver Buffer Register (Read Only) */
#define	UART_THR   0x0 /* Transmitter Holding Register (Write Only) */
#define	UART_IER   0x2 /* Interrupt Enable Register */
#define	UART_IIR   0x4 /* Interrupt Ident Register (Read Only) */
#define	UART_FCR   0x4 /* FIFO Control Register (Write Only) */
#define	UART_LCR   0x6 /* Line Control Register */
#define	UART_MCR   0x8 /* MODEM Control Register */
#define	UART_LSR   0xa /* Line Status Register */
#define	UART_MSR   0xc /* MODEM Status Register */
#define	UART_SCR   0xe /* Scratch Register */
#define	UART_DLL   0x0 /* Divisor Latch (LS) */
#define	UART_DLM   0x2 /* Divisor Latch (MS) */
#define	thr   rbr
#define	tcr   iir
#define	dll   rbr
#define	dlm   ier
#define	fcr   iir
#define	IER_ERDAI   0x0100 /* Enable Received Data Available Interrupt */
#define	IER_ETHREI   0x0200 /* Enable Transmitter Holding Register Empty Interrupt */
#define	IER_ELSI   0x0400 /* Enable Receiver Line Status Interrupt */
#define	IER_EMSI   0x0800 /* Enable MODEM Status Interrupt */
#define	IIR_IP   0x0100 /* "0" if Interrupt Pending */
#define	IIR_IIB0   0x0200 /* Interrupt ID Bit 0 */
#define	IIR_IIB1   0x0400 /* Interrupt ID Bit 1 */
#define	IIR_IIB2   0x0800 /* Interrupt ID Bit 2 */
#define	IIR_FIFO   0xc000 /* FIFOs enabled */
#define	FCR_FEN   0x0100 /* FIFO enable */
#define	FCR_RFRES   0x0200 /* Receiver FIFO reset */
#define	FCR_TFRES   0x0400 /* Transmitter FIFO reset */
#define	FCR_DMA   0x0800 /* DMA mode select */
#define	FCR_RTL   0x4000 /* Receiver triger (LSB) */
#define	FCR_RTM   0x8000 /* Receiver triger (MSB) */
#define	LCR_WLS0   0x0100 /* Word Length Select Bit 0 */
#define	LCR_WLS1   0x0200 /* Word Length Select Bit 1 */
#define	LCR_STB   0x0400 /* Number of Stop Bits */
#define	LCR_PEN   0x0800 /* Parity Enable */
#define	LCR_EPS   0x1000 /* Even Parity Select */
#define	LCR_SP   0x2000 /* Stick Parity */
#define	LCR_SB   0x4000 /* Set Break */
#define	LCR_DLAB   0x8000 /* Divisor Latch Access Bit */
#define	MCR_DTR   0x0100 /* Data Terminal Ready */
#define	MCR_RTS   0x0200 /* Request to Send */
#define	MCR_OUT1   0x0400 /* Out 1 */
#define	MCR_IRQEN   0x0800 /* IRQ Enable */
#define	MCR_LOOP   0x1000 /* Loop */
#define	LSR_DR   0x0100 /* Data Ready */
#define	LSR_OE   0x0200 /* Overrun Error */
#define	LSR_PE   0x0400 /* Parity Error */
#define	LSR_FE   0x0800 /* Framing Error */
#define	LSR_BI   0x1000 /* Break Interrupt */
#define	LSR_THRE   0x2000 /* Transmitter Holding Register Empty */
#define	LSR_TEMT   0x4000 /* Transmitter Empty */
#define	LSR_FIFOE   0x8000 /* Receiver FIFO error */
#define	MSR_DCTS   0x0100 /* Delta Clear to Send */
#define	MSR_DDSR   0x0200 /* Delta Data Set Ready */
#define	MSR_TERI   0x0400 /* Trailing Edge Ring Indicator */
#define	MSR_DDCD   0x0800 /* Delta Data Carrier Detect */
#define	MSR_CTS   0x1000 /* Clear to Send */
#define	MSR_DSR   0x2000 /* Data Set Ready */
#define	MSR_RI   0x4000 /* Ring Indicator */
#define	MSR_DCD   0x8000 /* Data Carrier Detect */
#define	UART_CLK   (1843200) /* 1.8432 MHz */
#define	UART_BAUD(x)   (UART_CLK / (16 * (x)))
#define	RTC_SECONDS   0
#define	RTC_SECONDS_ALARM   1
#define	RTC_MINUTES   2
#define	RTC_MINUTES_ALARM   3
#define	RTC_HOURS   4
#define	RTC_HOURS_ALARM   5
#define	RTC_DAY_OF_WEEK   6
#define	RTC_DAY_OF_MONTH   7
#define	RTC_MONTH   8
#define	RTC_YEAR   9
#define	RTC_FREQ_SELECT   10
#define	RTC_UIP   0x80
#define	RTC_DIV_CTL   0x70
#define	RTC_OSC_ENABLE   0x20
#define	RTC_OSC_DISABLE   0x00
#define	RTC_CONTROL   11
#define	RTC_SET   0x80
#define	RTC_PIE   0x40
#define	RTC_AIE   0x20
#define	RTC_UIE   0x10
#define	RTC_SQWE   0x08
#define	RTC_DM_BINARY   0x04
#define	RTC_24H   0x02
#define	RTC_DST_EN   0x01

Typedefs
typedef struct uart_reg	uart_reg

Macro Definition Documentation

#define ACTIVATE_INDEX   0x30

Definition at line 44 of file smc37c93x.h.

#define AUXIO_PRIMARY_BASE   0x000 /* XXX */

Definition at line 21 of file smc37c93x.h.

#define COM1_PRIMARY_BASE   0x2f8

Definition at line 17 of file smc37c93x.h.

#define COM2_PRIMARY_BASE   0x3f8

Definition at line 18 of file smc37c93x.h.

#define CONFIG_ENTER   0x55

Definition at line 38 of file smc37c93x.h.

#define CONFIG_EXIT   0xaa

Definition at line 39 of file smc37c93x.h.

#define CONFIG_PORT   0x3f0

Definition at line 35 of file smc37c93x.h.

#define CURRENT_LDN_INDEX   0x07

Definition at line 42 of file smc37c93x.h.

#define DATA_PORT   0x3f1

Definition at line 37 of file smc37c93x.h.

#define dll   rbr

Definition at line 89 of file smc37c93x.h.

#define dlm   ier

Definition at line 90 of file smc37c93x.h.

#define DMA_SELECT_INDEX   0x74

Definition at line 48 of file smc37c93x.h.

#define fcr   iir

Definition at line 91 of file smc37c93x.h.

#define FCR_DMA   0x0800 /* DMA mode select */

Definition at line 113 of file smc37c93x.h.

#define FCR_FEN   0x0100 /* FIFO enable */

Definition at line 110 of file smc37c93x.h.

#define FCR_RFRES   0x0200 /* Receiver FIFO reset */

Definition at line 111 of file smc37c93x.h.

#define FCR_RTL   0x4000 /* Receiver triger (LSB) */

Definition at line 114 of file smc37c93x.h.

#define FCR_RTM   0x8000 /* Receiver triger (MSB) */

Definition at line 115 of file smc37c93x.h.

#define FCR_TFRES   0x0400 /* Transmitter FIFO reset */

Definition at line 112 of file smc37c93x.h.

#define FDC_PRIMARY_BASE   0x3f0

Definition at line 13 of file smc37c93x.h.

#define GPIO46_INDEX   0xc6

Definition at line 50 of file smc37c93x.h.

#define GPIO47_INDEX   0xc7

Definition at line 51 of file smc37c93x.h.

#define IDE1_PRIMARY_BASE   0x1f0

Definition at line 14 of file smc37c93x.h.

#define IDE1_SECONDARY_BASE   0x170

Definition at line 15 of file smc37c93x.h.

#define IER_ELSI   0x0400 /* Enable Receiver Line Status Interrupt */

Definition at line 97 of file smc37c93x.h.

#define IER_EMSI   0x0800 /* Enable MODEM Status Interrupt */

Definition at line 98 of file smc37c93x.h.

#define IER_ERDAI   0x0100 /* Enable Received Data Available Interrupt */

Definition at line 95 of file smc37c93x.h.

#define IER_ETHREI   0x0200 /* Enable Transmitter Holding Register Empty Interrupt */

Definition at line 96 of file smc37c93x.h.

#define IIR_FIFO   0xc000 /* FIFOs enabled */

Definition at line 106 of file smc37c93x.h.

#define IIR_IIB0   0x0200 /* Interrupt ID Bit 0 */

Definition at line 103 of file smc37c93x.h.

#define IIR_IIB1   0x0400 /* Interrupt ID Bit 1 */

Definition at line 104 of file smc37c93x.h.

#define IIR_IIB2   0x0800 /* Interrupt ID Bit 2 */

Definition at line 105 of file smc37c93x.h.

#define IIR_IP   0x0100 /* "0" if Interrupt Pending */

Definition at line 102 of file smc37c93x.h.

#define INDEX_PORT   CONFIG_PORT

Definition at line 36 of file smc37c93x.h.

#define IO_BASE_HI_INDEX   0x60

Definition at line 45 of file smc37c93x.h.

#define IO_BASE_LO_INDEX   0x61

Definition at line 46 of file smc37c93x.h.

#define IRQ_SELECT_INDEX   0x70

Definition at line 47 of file smc37c93x.h.

#define KBC_PRIMARY_BASE   0x060

Definition at line 20 of file smc37c93x.h.

#define LCR_DLAB   0x8000 /* Divisor Latch Access Bit */

Definition at line 126 of file smc37c93x.h.

#define LCR_EPS   0x1000 /* Even Parity Select */

Definition at line 123 of file smc37c93x.h.

#define LCR_PEN   0x0800 /* Parity Enable */

Definition at line 122 of file smc37c93x.h.

#define LCR_SB   0x4000 /* Set Break */

Definition at line 125 of file smc37c93x.h.

#define LCR_SP   0x2000 /* Stick Parity */

Definition at line 124 of file smc37c93x.h.

#define LCR_STB   0x0400 /* Number of Stop Bits */

Definition at line 121 of file smc37c93x.h.

#define LCR_WLS0   0x0100 /* Word Length Select Bit 0 */

Definition at line 119 of file smc37c93x.h.

#define LCR_WLS1   0x0200 /* Word Length Select Bit 1 */

Definition at line 120 of file smc37c93x.h.

#define LDN_AUXIO   8

Definition at line 32 of file smc37c93x.h.

#define LDN_COM1   4

Definition at line 28 of file smc37c93x.h.

#define LDN_COM2   5

Definition at line 29 of file smc37c93x.h.

#define LDN_FDC   0

Definition at line 24 of file smc37c93x.h.

#define LDN_IDE1   1

Definition at line 25 of file smc37c93x.h.

#define LDN_IDE2   2

Definition at line 26 of file smc37c93x.h.

#define LDN_KBC   7

Definition at line 31 of file smc37c93x.h.

#define LDN_PARPORT   3

Definition at line 27 of file smc37c93x.h.

#define LDN_RTC   6

Definition at line 30 of file smc37c93x.h.

#define LSR_BI   0x1000 /* Break Interrupt */

Definition at line 142 of file smc37c93x.h.

#define LSR_DR   0x0100 /* Data Ready */

Definition at line 138 of file smc37c93x.h.

#define LSR_FE   0x0800 /* Framing Error */

Definition at line 141 of file smc37c93x.h.

#define LSR_FIFOE   0x8000 /* Receiver FIFO error */

Definition at line 145 of file smc37c93x.h.

#define LSR_OE   0x0200 /* Overrun Error */

Definition at line 139 of file smc37c93x.h.

#define LSR_PE   0x0400 /* Parity Error */

Definition at line 140 of file smc37c93x.h.

#define LSR_TEMT   0x4000 /* Transmitter Empty */

Definition at line 144 of file smc37c93x.h.

#define LSR_THRE   0x2000 /* Transmitter Holding Register Empty */

Definition at line 143 of file smc37c93x.h.

#define MCR_DTR   0x0100 /* Data Terminal Ready */

Definition at line 130 of file smc37c93x.h.

#define MCR_IRQEN   0x0800 /* IRQ Enable */

Definition at line 133 of file smc37c93x.h.

#define MCR_LOOP   0x1000 /* Loop */

Definition at line 134 of file smc37c93x.h.

#define MCR_OUT1   0x0400 /* Out 1 */

Definition at line 132 of file smc37c93x.h.

#define MCR_RTS   0x0200 /* Request to Send */

Definition at line 131 of file smc37c93x.h.

#define MSR_CTS   0x1000 /* Clear to Send */

Definition at line 153 of file smc37c93x.h.

#define MSR_DCD   0x8000 /* Data Carrier Detect */

Definition at line 156 of file smc37c93x.h.

#define MSR_DCTS   0x0100 /* Delta Clear to Send */

Definition at line 149 of file smc37c93x.h.

#define MSR_DDCD   0x0800 /* Delta Data Carrier Detect */

Definition at line 152 of file smc37c93x.h.

#define MSR_DDSR   0x0200 /* Delta Data Set Ready */

Definition at line 150 of file smc37c93x.h.

#define MSR_DSR   0x2000 /* Data Set Ready */

Definition at line 154 of file smc37c93x.h.

#define MSR_RI   0x4000 /* Ring Indicator */

Definition at line 155 of file smc37c93x.h.

#define MSR_TERI   0x0400 /* Trailing Edge Ring Indicator */

Definition at line 151 of file smc37c93x.h.

#define PARPORT_PRIMARY_BASE   0x378

Definition at line 16 of file smc37c93x.h.

#define POWER_CONTROL_INDEX   0x22

Definition at line 43 of file smc37c93x.h.

#define RTC_24H   0x02

Definition at line 187 of file smc37c93x.h.

#define RTC_AIE   0x20

Definition at line 183 of file smc37c93x.h.

#define RTC_CONTROL   11

Definition at line 180 of file smc37c93x.h.

#define RTC_DAY_OF_MONTH   7

Definition at line 171 of file smc37c93x.h.

#define RTC_DAY_OF_WEEK   6

Definition at line 170 of file smc37c93x.h.

#define RTC_DIV_CTL   0x70

Definition at line 176 of file smc37c93x.h.

#define RTC_DM_BINARY   0x04

Definition at line 186 of file smc37c93x.h.

#define RTC_DST_EN   0x01

Definition at line 188 of file smc37c93x.h.

#define RTC_FREQ_SELECT   10

Definition at line 174 of file smc37c93x.h.

#define RTC_HOURS   4

Definition at line 168 of file smc37c93x.h.

#define RTC_HOURS_ALARM   5

Definition at line 169 of file smc37c93x.h.

#define RTC_MINUTES   2

Definition at line 166 of file smc37c93x.h.

#define RTC_MINUTES_ALARM   3

Definition at line 167 of file smc37c93x.h.

#define RTC_MONTH   8

Definition at line 172 of file smc37c93x.h.

#define RTC_OSC_DISABLE   0x00

Definition at line 179 of file smc37c93x.h.

#define RTC_OSC_ENABLE   0x20

Definition at line 178 of file smc37c93x.h.

#define RTC_PIE   0x40

Definition at line 182 of file smc37c93x.h.

#define RTC_PRIMARY_BASE   0x070

Definition at line 19 of file smc37c93x.h.

#define RTC_SECONDS   0

Definition at line 164 of file smc37c93x.h.

#define RTC_SECONDS_ALARM   1

Definition at line 165 of file smc37c93x.h.

#define RTC_SET   0x80

Definition at line 181 of file smc37c93x.h.

#define RTC_SQWE   0x08

Definition at line 185 of file smc37c93x.h.

#define RTC_UIE   0x10

Definition at line 184 of file smc37c93x.h.

#define RTC_UIP   0x80

Definition at line 175 of file smc37c93x.h.

#define RTC_YEAR   9

Definition at line 173 of file smc37c93x.h.

#define tcr   iir

Definition at line 85 of file smc37c93x.h.

#define thr   rbr

Definition at line 84 of file smc37c93x.h.

#define UART_BAUD

(

x

)

(UART_CLK / (16 * (x)))

Definition at line 161 of file smc37c93x.h.

#define UART_CLK   (1843200) /* 1.8432 MHz */

Definition at line 160 of file smc37c93x.h.

#define UART_DLL   0x0 /* Divisor Latch (LS) */

Definition at line 66 of file smc37c93x.h.

#define UART_DLM   0x2 /* Divisor Latch (MS) */

Definition at line 67 of file smc37c93x.h.

#define UART_FCR   0x4 /* FIFO Control Register (Write Only) */

Definition at line 60 of file smc37c93x.h.

#define UART_IER   0x2 /* Interrupt Enable Register */

Definition at line 58 of file smc37c93x.h.

#define UART_IIR   0x4 /* Interrupt Ident Register (Read Only) */

Definition at line 59 of file smc37c93x.h.

#define UART_LCR   0x6 /* Line Control Register */

Definition at line 61 of file smc37c93x.h.

#define UART_LSR   0xa /* Line Status Register */

Definition at line 63 of file smc37c93x.h.

#define UART_MCR   0x8 /* MODEM Control Register */

Definition at line 62 of file smc37c93x.h.

#define UART_MSR   0xc /* MODEM Status Register */

Definition at line 64 of file smc37c93x.h.

#define UART_RBR   0x0 /* Receiver Buffer Register (Read Only) */

Definition at line 56 of file smc37c93x.h.

#define UART_SCR   0xe /* Scratch Register */

Definition at line 65 of file smc37c93x.h.

#define UART_THR   0x0 /* Transmitter Holding Register (Write Only) */

Definition at line 57 of file smc37c93x.h.

Typedef Documentation

typedef struct uart_reg uart_reg