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spear300.c
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1 /*
2  * arch/arm/mach-spear3xx/spear300.c
3  *
4  * SPEAr300 machine source file
5  *
6  * Copyright (C) 2009-2012 ST Microelectronics
7  * Viresh Kumar <[email protected]>
8  *
9  * This file is licensed under the terms of the GNU General Public
10  * License version 2. This program is licensed "as is" without any
11  * warranty of any kind, whether express or implied.
12  */
13 
14 #define pr_fmt(fmt) "SPEAr300: " fmt
15 
16 #include <linux/amba/pl08x.h>
17 #include <linux/of_platform.h>
18 #include <asm/hardware/vic.h>
19 #include <asm/mach/arch.h>
20 #include <plat/shirq.h>
21 #include <mach/generic.h>
22 #include <mach/spear.h>
23 
24 /* Base address of various IPs */
25 #define SPEAR300_TELECOM_BASE UL(0x50000000)
26 
27 /* Interrupt registers offsets and masks */
28 #define SPEAR300_INT_ENB_MASK_REG 0x54
29 #define SPEAR300_INT_STS_MASK_REG 0x58
30 #define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0)
31 #define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1)
32 #define SPEAR300_I2S_IRQ_MASK (1 << 2)
33 #define SPEAR300_TDM_IRQ_MASK (1 << 3)
34 #define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4)
35 #define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5)
36 #define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6)
37 #define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7)
38 #define SPEAR300_GPIO1_IRQ_MASK (1 << 8)
39 
40 #define SPEAR300_SHIRQ_RAS1_MASK 0x1FF
41 
42 #define SPEAR300_SOC_CONFIG_BASE UL(0x99000000)
43 
44 
45 /* SPEAr300 Virtual irq definitions */
46 /* IRQs sharing IRQ_GEN_RAS_1 */
47 #define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0)
48 #define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1)
49 #define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2)
50 #define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3)
51 #define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4)
52 #define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5)
53 #define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6)
54 #define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7)
55 #define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8)
56 
57 /* IRQs sharing IRQ_GEN_RAS_3 */
58 #define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3
59 
60 /* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
61 #define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
62 
63 /* spear3xx shared irq */
64 static struct shirq_dev_config shirq_ras1_config[] = {
65  {
66  .virq = SPEAR300_VIRQ_IT_PERS_S,
67  .enb_mask = SPEAR300_IT_PERS_S_IRQ_MASK,
68  .status_mask = SPEAR300_IT_PERS_S_IRQ_MASK,
69  }, {
70  .virq = SPEAR300_VIRQ_IT_CHANGE_S,
71  .enb_mask = SPEAR300_IT_CHANGE_S_IRQ_MASK,
72  .status_mask = SPEAR300_IT_CHANGE_S_IRQ_MASK,
73  }, {
74  .virq = SPEAR300_VIRQ_I2S,
75  .enb_mask = SPEAR300_I2S_IRQ_MASK,
76  .status_mask = SPEAR300_I2S_IRQ_MASK,
77  }, {
78  .virq = SPEAR300_VIRQ_TDM,
79  .enb_mask = SPEAR300_TDM_IRQ_MASK,
80  .status_mask = SPEAR300_TDM_IRQ_MASK,
81  }, {
82  .virq = SPEAR300_VIRQ_CAMERA_L,
83  .enb_mask = SPEAR300_CAMERA_L_IRQ_MASK,
84  .status_mask = SPEAR300_CAMERA_L_IRQ_MASK,
85  }, {
86  .virq = SPEAR300_VIRQ_CAMERA_F,
87  .enb_mask = SPEAR300_CAMERA_F_IRQ_MASK,
88  .status_mask = SPEAR300_CAMERA_F_IRQ_MASK,
89  }, {
90  .virq = SPEAR300_VIRQ_CAMERA_V,
91  .enb_mask = SPEAR300_CAMERA_V_IRQ_MASK,
92  .status_mask = SPEAR300_CAMERA_V_IRQ_MASK,
93  }, {
94  .virq = SPEAR300_VIRQ_KEYBOARD,
95  .enb_mask = SPEAR300_KEYBOARD_IRQ_MASK,
96  .status_mask = SPEAR300_KEYBOARD_IRQ_MASK,
97  }, {
98  .virq = SPEAR300_VIRQ_GPIO1,
99  .enb_mask = SPEAR300_GPIO1_IRQ_MASK,
100  .status_mask = SPEAR300_GPIO1_IRQ_MASK,
101  },
102 };
103 
104 static struct spear_shirq shirq_ras1 = {
105  .irq = SPEAR3XX_IRQ_GEN_RAS_1,
106  .dev_config = shirq_ras1_config,
107  .dev_count = ARRAY_SIZE(shirq_ras1_config),
108  .regs = {
109  .enb_reg = SPEAR300_INT_ENB_MASK_REG,
110  .status_reg = SPEAR300_INT_STS_MASK_REG,
111  .status_reg_mask = SPEAR300_SHIRQ_RAS1_MASK,
112  .clear_reg = -1,
113  },
114 };
115 
116 /* DMAC platform data's slave info */
117 struct pl08x_channel_data spear300_dma_info[] = {
118  {
119  .bus_id = "uart0_rx",
120  .min_signal = 2,
121  .max_signal = 2,
122  .muxval = 0,
123  .periph_buses = PL08X_AHB1,
124  }, {
125  .bus_id = "uart0_tx",
126  .min_signal = 3,
127  .max_signal = 3,
128  .muxval = 0,
129  .periph_buses = PL08X_AHB1,
130  }, {
131  .bus_id = "ssp0_rx",
132  .min_signal = 8,
133  .max_signal = 8,
134  .muxval = 0,
135  .periph_buses = PL08X_AHB1,
136  }, {
137  .bus_id = "ssp0_tx",
138  .min_signal = 9,
139  .max_signal = 9,
140  .muxval = 0,
141  .periph_buses = PL08X_AHB1,
142  }, {
143  .bus_id = "i2c_rx",
144  .min_signal = 10,
145  .max_signal = 10,
146  .muxval = 0,
147  .periph_buses = PL08X_AHB1,
148  }, {
149  .bus_id = "i2c_tx",
150  .min_signal = 11,
151  .max_signal = 11,
152  .muxval = 0,
153  .periph_buses = PL08X_AHB1,
154  }, {
155  .bus_id = "irda",
156  .min_signal = 12,
157  .max_signal = 12,
158  .muxval = 0,
159  .periph_buses = PL08X_AHB1,
160  }, {
161  .bus_id = "adc",
162  .min_signal = 13,
163  .max_signal = 13,
164  .muxval = 0,
165  .periph_buses = PL08X_AHB1,
166  }, {
167  .bus_id = "to_jpeg",
168  .min_signal = 14,
169  .max_signal = 14,
170  .muxval = 0,
171  .periph_buses = PL08X_AHB1,
172  }, {
173  .bus_id = "from_jpeg",
174  .min_signal = 15,
175  .max_signal = 15,
176  .muxval = 0,
177  .periph_buses = PL08X_AHB1,
178  }, {
179  .bus_id = "ras0_rx",
180  .min_signal = 0,
181  .max_signal = 0,
182  .muxval = 1,
183  .periph_buses = PL08X_AHB1,
184  }, {
185  .bus_id = "ras0_tx",
186  .min_signal = 1,
187  .max_signal = 1,
188  .muxval = 1,
189  .periph_buses = PL08X_AHB1,
190  }, {
191  .bus_id = "ras1_rx",
192  .min_signal = 2,
193  .max_signal = 2,
194  .muxval = 1,
195  .periph_buses = PL08X_AHB1,
196  }, {
197  .bus_id = "ras1_tx",
198  .min_signal = 3,
199  .max_signal = 3,
200  .muxval = 1,
201  .periph_buses = PL08X_AHB1,
202  }, {
203  .bus_id = "ras2_rx",
204  .min_signal = 4,
205  .max_signal = 4,
206  .muxval = 1,
207  .periph_buses = PL08X_AHB1,
208  }, {
209  .bus_id = "ras2_tx",
210  .min_signal = 5,
211  .max_signal = 5,
212  .muxval = 1,
213  .periph_buses = PL08X_AHB1,
214  }, {
215  .bus_id = "ras3_rx",
216  .min_signal = 6,
217  .max_signal = 6,
218  .muxval = 1,
219  .periph_buses = PL08X_AHB1,
220  }, {
221  .bus_id = "ras3_tx",
222  .min_signal = 7,
223  .max_signal = 7,
224  .muxval = 1,
225  .periph_buses = PL08X_AHB1,
226  }, {
227  .bus_id = "ras4_rx",
228  .min_signal = 8,
229  .max_signal = 8,
230  .muxval = 1,
231  .periph_buses = PL08X_AHB1,
232  }, {
233  .bus_id = "ras4_tx",
234  .min_signal = 9,
235  .max_signal = 9,
236  .muxval = 1,
237  .periph_buses = PL08X_AHB1,
238  }, {
239  .bus_id = "ras5_rx",
240  .min_signal = 10,
241  .max_signal = 10,
242  .muxval = 1,
243  .periph_buses = PL08X_AHB1,
244  }, {
245  .bus_id = "ras5_tx",
246  .min_signal = 11,
247  .max_signal = 11,
248  .muxval = 1,
249  .periph_buses = PL08X_AHB1,
250  }, {
251  .bus_id = "ras6_rx",
252  .min_signal = 12,
253  .max_signal = 12,
254  .muxval = 1,
255  .periph_buses = PL08X_AHB1,
256  }, {
257  .bus_id = "ras6_tx",
258  .min_signal = 13,
259  .max_signal = 13,
260  .muxval = 1,
261  .periph_buses = PL08X_AHB1,
262  }, {
263  .bus_id = "ras7_rx",
264  .min_signal = 14,
265  .max_signal = 14,
266  .muxval = 1,
267  .periph_buses = PL08X_AHB1,
268  }, {
269  .bus_id = "ras7_tx",
270  .min_signal = 15,
271  .max_signal = 15,
272  .muxval = 1,
273  .periph_buses = PL08X_AHB1,
274  },
275 };
276 
277 /* Add SPEAr300 auxdata to pass platform data */
278 static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
279  OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
280  &pl022_plat_data),
281  OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
282  &pl080_plat_data),
283  {}
284 };
285 
286 static void __init spear300_dt_init(void)
287 {
288  int ret;
289 
290  pl080_plat_data.slave_channels = spear300_dma_info;
291  pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info);
292 
293  of_platform_populate(NULL, of_default_bus_match_table,
294  spear300_auxdata_lookup, NULL);
295 
296  /* shared irq registration */
297  shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K);
298  if (shirq_ras1.regs.base) {
299  ret = spear_shirq_register(&shirq_ras1);
300  if (ret)
301  pr_err("Error registering Shared IRQ\n");
302  }
303 }
304 
305 static const char * const spear300_dt_board_compat[] = {
306  "st,spear300",
307  "st,spear300-evb",
308  NULL,
309 };
310 
311 static void __init spear300_map_io(void)
312 {
313  spear3xx_map_io();
314 }
315 
316 DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree")
317  .map_io = spear300_map_io,
318  .init_irq = spear3xx_dt_init_irq,
319  .handle_irq = vic_handle_irq,
320  .timer = &spear3xx_timer,
321  .init_machine = spear300_dt_init,
322  .restart = spear_restart,
323  .dt_compat = spear300_dt_board_compat,
324 MACHINE_END
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