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spi-fsl-lib.h
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1 /*
2  * Freescale SPI/eSPI controller driver library.
3  *
4  * Maintainer: Kumar Gala
5  *
6  * Copyright 2010 Freescale Semiconductor, Inc.
7  * Copyright (C) 2006 Polycom, Inc.
8  *
9  * CPM SPI and QE buffer descriptors mode support:
10  * Copyright (c) 2009 MontaVista Software, Inc.
11  * Author: Anton Vorontsov <[email protected]>
12  *
13  * This program is free software; you can redistribute it and/or modify it
14  * under the terms of the GNU General Public License as published by the
15  * Free Software Foundation; either version 2 of the License, or (at your
16  * option) any later version.
17  */
18 #ifndef __SPI_FSL_LIB_H__
19 #define __SPI_FSL_LIB_H__
20 
21 #include <asm/io.h>
22 
23 /* SPI/eSPI Controller driver's private data. */
24 struct mpc8xxx_spi {
25  struct device *dev;
26  void *reg_base;
27 
28  /* rx & tx bufs from the spi_transfer */
29  const void *tx;
30  void *rx;
31 #ifdef CONFIG_SPI_FSL_ESPI
32  int len;
33 #endif
34 
35  int subblock;
39 
41 
42  /* dma addresses for CPM transfers */
45  bool map_tx_dma;
46  bool map_rx_dma;
47 
50 
51  /* functions to deal with different sized buffers */
52  void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
53  u32(*get_tx) (struct mpc8xxx_spi *);
54 
55  /* hooks for different controller driver */
57  void (*spi_remove) (struct mpc8xxx_spi *mspi);
58 
59  unsigned int count;
60  unsigned int irq;
61 
62  unsigned nsecs; /* (clock cycle time)/2 */
63 
64  u32 spibrg; /* SPIBRG input clock */
65  u32 rx_shift; /* RX data reg shift when in qe mode */
66  u32 tx_shift; /* TX data reg shift when in qe mode */
67 
68  unsigned int flags;
69 
71  struct work_struct work;
72 
73  struct list_head queue;
75 
76  struct completion done;
77 };
78 
80  /* functions to deal with different sized buffers */
81  void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
82  u32 (*get_tx) (struct mpc8xxx_spi *);
83  u32 rx_shift; /* RX data reg shift when in qe mode */
84  u32 tx_shift; /* TX data reg shift when in qe mode */
85  u32 hw_mode; /* Holds HW mode register settings */
86 };
87 
88 static inline void mpc8xxx_spi_write_reg(__be32 __iomem *reg, u32 val)
89 {
90  out_be32(reg, val);
91 }
92 
93 static inline u32 mpc8xxx_spi_read_reg(__be32 __iomem *reg)
94 {
95  return in_be32(reg);
96 }
97 
100  int *gpios;
101  bool *alow_flags;
102 };
103 
110 
111 extern struct mpc8xxx_spi_probe_info *to_of_pinfo(
112  struct fsl_spi_platform_data *pdata);
113 extern int mpc8xxx_spi_bufs(struct mpc8xxx_spi *mspi,
114  struct spi_transfer *t, unsigned int len);
115 extern int mpc8xxx_spi_transfer(struct spi_device *spi, struct spi_message *m);
116 extern void mpc8xxx_spi_cleanup(struct spi_device *spi);
117 extern const char *mpc8xxx_spi_strmode(unsigned int flags);
118 extern int mpc8xxx_spi_probe(struct device *dev, struct resource *mem,
119  unsigned int irq);
120 extern int mpc8xxx_spi_remove(struct device *dev);
121 extern int of_mpc8xxx_spi_probe(struct platform_device *ofdev);
122 
123 #endif /* __SPI_FSL_LIB_H__ */