Macros
#define	MAX_GRPS (32)

#define	MAX_SPRS_PER_GRP_BITS (11)

#define	MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS)

#define	MAX_SPRS (0x10000)

#define	SPRGROUP_SYS (0 << MAX_SPRS_PER_GRP_BITS)

#define	SPRGROUP_DMMU (1 << MAX_SPRS_PER_GRP_BITS)

#define	SPRGROUP_IMMU (2 << MAX_SPRS_PER_GRP_BITS)

#define	SPRGROUP_DC (3 << MAX_SPRS_PER_GRP_BITS)

#define	SPRGROUP_IC (4 << MAX_SPRS_PER_GRP_BITS)

#define	SPRGROUP_MAC (5 << MAX_SPRS_PER_GRP_BITS)

#define	SPRGROUP_D (6 << MAX_SPRS_PER_GRP_BITS)

#define	SPRGROUP_PC (7 << MAX_SPRS_PER_GRP_BITS)

#define	SPRGROUP_PM (8 << MAX_SPRS_PER_GRP_BITS)

#define	SPRGROUP_PIC (9 << MAX_SPRS_PER_GRP_BITS)

#define	SPRGROUP_TT (10 << MAX_SPRS_PER_GRP_BITS)

#define	SPRGROUP_FP (11 << MAX_SPRS_PER_GRP_BITS)

#define	SPR_VR (SPRGROUP_SYS + 0)

#define	SPR_UPR (SPRGROUP_SYS + 1)

#define	SPR_CPUCFGR (SPRGROUP_SYS + 2)

#define	SPR_DMMUCFGR (SPRGROUP_SYS + 3)

#define	SPR_IMMUCFGR (SPRGROUP_SYS + 4)

#define	SPR_DCCFGR (SPRGROUP_SYS + 5)

#define	SPR_ICCFGR (SPRGROUP_SYS + 6)

#define	SPR_DCFGR (SPRGROUP_SYS + 7)

#define	SPR_PCCFGR (SPRGROUP_SYS + 8)

#define	SPR_NPC (SPRGROUP_SYS + 16) /* CZ 21/06/01 */

#define	SPR_SR (SPRGROUP_SYS + 17) /* CZ 21/06/01 */

#define	SPR_PPC (SPRGROUP_SYS + 18) /* CZ 21/06/01 */

#define	SPR_FPCSR (SPRGROUP_SYS + 20) /* CZ 21/06/01 */

#define	SPR_EPCR_BASE (SPRGROUP_SYS + 32) /* CZ 21/06/01 */

#define	SPR_EPCR_LAST (SPRGROUP_SYS + 47) /* CZ 21/06/01 */

#define	SPR_EEAR_BASE (SPRGROUP_SYS + 48)

#define	SPR_EEAR_LAST (SPRGROUP_SYS + 63)

#define	SPR_ESR_BASE (SPRGROUP_SYS + 64)

#define	SPR_ESR_LAST (SPRGROUP_SYS + 79)

#define	SPR_GPR_BASE (SPRGROUP_SYS + 1024)

#define	SPR_DMMUCR (SPRGROUP_DMMU + 0)

#define	SPR_DTLBEIR (SPRGROUP_DMMU + 2)

#define	SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)

#define	SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)

#define	SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)

#define	SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)

#define	SPR_IMMUCR (SPRGROUP_IMMU + 0)

#define	SPR_ITLBEIR (SPRGROUP_IMMU + 2)

#define	SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)

#define	SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100)

#define	SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100)

#define	SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100)

#define	SPR_DCCR (SPRGROUP_DC + 0)

#define	SPR_DCBPR (SPRGROUP_DC + 1)

#define	SPR_DCBFR (SPRGROUP_DC + 2)

#define	SPR_DCBIR (SPRGROUP_DC + 3)

#define	SPR_DCBWR (SPRGROUP_DC + 4)

#define	SPR_DCBLR (SPRGROUP_DC + 5)

#define	SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200)

#define	SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200)

#define	SPR_ICCR (SPRGROUP_IC + 0)

#define	SPR_ICBPR (SPRGROUP_IC + 1)

#define	SPR_ICBIR (SPRGROUP_IC + 2)

#define	SPR_ICBLR (SPRGROUP_IC + 3)

#define	SPR_ICR_BASE(WAY) (SPRGROUP_IC + 0x200 + (WAY) * 0x200)

#define	SPR_ICR_LAST(WAY) (SPRGROUP_IC + 0x3ff + (WAY) * 0x200)

#define	SPR_MACLO (SPRGROUP_MAC + 1)

#define	SPR_MACHI (SPRGROUP_MAC + 2)

#define	SPR_DVR(N) (SPRGROUP_D + (N))

#define	SPR_DCR(N) (SPRGROUP_D + 8 + (N))

#define	SPR_DMR1 (SPRGROUP_D + 16)

#define	SPR_DMR2 (SPRGROUP_D + 17)

#define	SPR_DWCR0 (SPRGROUP_D + 18)

#define	SPR_DWCR1 (SPRGROUP_D + 19)

#define	SPR_DSR (SPRGROUP_D + 20)

#define	SPR_DRR (SPRGROUP_D + 21)

#define	SPR_PCCR(N) (SPRGROUP_PC + (N))

#define	SPR_PCMR(N) (SPRGROUP_PC + 8 + (N))

#define	SPR_PMR (SPRGROUP_PM + 0)

#define	SPR_PICMR (SPRGROUP_PIC + 0)

#define	SPR_PICPR (SPRGROUP_PIC + 1)

#define	SPR_PICSR (SPRGROUP_PIC + 2)

#define	SPR_TTMR (SPRGROUP_TT + 0)

#define	SPR_TTCR (SPRGROUP_TT + 1)

#define	SPR_VR_VER 0xff000000 /* Processor version */

#define	SPR_VR_CFG 0x00ff0000 /* Processor configuration */

#define	SPR_VR_RES 0x0000ffc0 /* Reserved */

#define	SPR_VR_REV 0x0000003f /* Processor revision */

#define	SPR_VR_VER_OFF 24

#define	SPR_VR_CFG_OFF 16

#define	SPR_VR_REV_OFF 0

#define	SPR_UPR_UP 0x00000001 /* UPR present */

#define	SPR_UPR_DCP 0x00000002 /* Data cache present */

#define	SPR_UPR_ICP 0x00000004 /* Instruction cache present */

#define	SPR_UPR_DMP 0x00000008 /* Data MMU present */

#define	SPR_UPR_IMP 0x00000010 /* Instruction MMU present */

#define	SPR_UPR_MP 0x00000020 /* MAC present */

#define	SPR_UPR_DUP 0x00000040 /* Debug unit present */

#define	SPR_UPR_PCUP 0x00000080 /* Performance counters unit present */

#define	SPR_UPR_PMP 0x00000100 /* Power management present */

#define	SPR_UPR_PICP 0x00000200 /* PIC present */

#define	SPR_UPR_TTP 0x00000400 /* Tick timer present */

#define	SPR_UPR_RES 0x00fe0000 /* Reserved */

#define	SPR_UPR_CUP 0xff000000 /* Context units present */

#define	SPR_CPUCFGR_NSGF 0x0000000f /* Number of shadow GPR files */

#define	SPR_CPUCFGR_CGF 0x00000010 /* Custom GPR file */

#define	SPR_CPUCFGR_OB32S 0x00000020 /* ORBIS32 supported */

#define	SPR_CPUCFGR_OB64S 0x00000040 /* ORBIS64 supported */

#define	SPR_CPUCFGR_OF32S 0x00000080 /* ORFPX32 supported */

#define	SPR_CPUCFGR_OF64S 0x00000100 /* ORFPX64 supported */

#define	SPR_CPUCFGR_OV64S 0x00000200 /* ORVDX64 supported */

#define	SPR_CPUCFGR_RES 0xfffffc00 /* Reserved */

#define	SPR_DCFGR_NDP 0x00000007 /* Number of matchpoints mask */

#define	SPR_DCFGR_NDP1 0x00000000 /* One matchpoint supported */

#define	SPR_DCFGR_NDP2 0x00000001 /* Two matchpoints supported */

#define	SPR_DCFGR_NDP3 0x00000002 /* Three matchpoints supported */

#define	SPR_DCFGR_NDP4 0x00000003 /* Four matchpoints supported */

#define	SPR_DCFGR_NDP5 0x00000004 /* Five matchpoints supported */

#define	SPR_DCFGR_NDP6 0x00000005 /* Six matchpoints supported */

#define	SPR_DCFGR_NDP7 0x00000006 /* Seven matchpoints supported */

#define	SPR_DCFGR_NDP8 0x00000007 /* Eight matchpoints supported */

#define	SPR_DCFGR_WPCI 0x00000008 /* Watchpoint counters implemented */

#define	MATCHPOINTS_TO_NDP(n)

#define	MAX_MATCHPOINTS 8

#define	MAX_WATCHPOINTS (MAX_MATCHPOINTS + 2)

#define	SPR_SR_SM 0x00000001 /* Supervisor Mode */

#define	SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */

#define	SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */

#define	SPR_SR_DCE 0x00000008 /* Data Cache Enable */

#define	SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */

#define	SPR_SR_DME 0x00000020 /* Data MMU Enable */

#define	SPR_SR_IME 0x00000040 /* Instruction MMU Enable */

#define	SPR_SR_LEE 0x00000080 /* Little Endian Enable */

#define	SPR_SR_CE 0x00000100 /* CID Enable */

#define	SPR_SR_F 0x00000200 /* Condition Flag */

#define	SPR_SR_CY 0x00000400 /* Carry flag */

#define	SPR_SR_OV 0x00000800 /* Overflow flag */

#define	SPR_SR_OVE 0x00001000 /* Overflow flag Exception */

#define	SPR_SR_DSX 0x00002000 /* Delay Slot Exception */

#define	SPR_SR_EPH 0x00004000 /* Exception Prefix High */

#define	SPR_SR_FO 0x00008000 /* Fixed one */

#define	SPR_SR_SUMRA 0x00010000 /* Supervisor SPR read access */

#define	SPR_SR_RES 0x0ffe0000 /* Reserved */

#define	SPR_SR_CID 0xf0000000 /* Context ID */

#define	SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */

#define	SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */

#define	SPR_DMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */

#define	SPR_DMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */

#define	SPR_IMMUCR_P2S 0x0000003e /* Level 2 Page Size */

#define	SPR_IMMUCR_P1S 0x000007c0 /* Level 1 Page Size */

#define	SPR_IMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */

#define	SPR_IMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */

#define	SPR_DTLBMR_V 0x00000001 /* Valid */

#define	SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */

#define	SPR_DTLBMR_CID 0x0000003c /* Context ID */

#define	SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */

#define	SPR_DTLBMR_VPN 0xfffff000 /* Virtual Page Number */

#define	SPR_DTLBTR_CC 0x00000001 /* Cache Coherency */

#define	SPR_DTLBTR_CI 0x00000002 /* Cache Inhibit */

#define	SPR_DTLBTR_WBC 0x00000004 /* Write-Back Cache */

#define	SPR_DTLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */

#define	SPR_DTLBTR_A 0x00000010 /* Accessed */

#define	SPR_DTLBTR_D 0x00000020 /* Dirty */

#define	SPR_DTLBTR_URE 0x00000040 /* User Read Enable */

#define	SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */

#define	SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */

#define	SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */

#define	SPR_DTLBTR_PPN 0xfffff000 /* Physical Page Number */

#define	SPR_ITLBMR_V 0x00000001 /* Valid */

#define	SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */

#define	SPR_ITLBMR_CID 0x0000003c /* Context ID */

#define	SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */

#define	SPR_ITLBMR_VPN 0xfffff000 /* Virtual Page Number */

#define	SPR_ITLBTR_CC 0x00000001 /* Cache Coherency */

#define	SPR_ITLBTR_CI 0x00000002 /* Cache Inhibit */

#define	SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */

#define	SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */

#define	SPR_ITLBTR_A 0x00000010 /* Accessed */

#define	SPR_ITLBTR_D 0x00000020 /* Dirty */

#define	SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */

#define	SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */

#define	SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */

#define	SPR_DCCR_EW 0x000000ff /* Enable ways */

#define	SPR_ICCR_EW 0x000000ff /* Enable ways */

#define	SPR_DCCFGR_NCW 0x00000007

#define	SPR_DCCFGR_NCS 0x00000078

#define	SPR_DCCFGR_CBS 0x00000080

#define	SPR_DCCFGR_CWS 0x00000100

#define	SPR_DCCFGR_CCRI 0x00000200

#define	SPR_DCCFGR_CBIRI 0x00000400

#define	SPR_DCCFGR_CBPRI 0x00000800

#define	SPR_DCCFGR_CBLRI 0x00001000

#define	SPR_DCCFGR_CBFRI 0x00002000

#define	SPR_DCCFGR_CBWBRI 0x00004000

#define	SPR_DCCFGR_NCW_OFF 0

#define	SPR_DCCFGR_NCS_OFF 3

#define	SPR_DCCFGR_CBS_OFF 7

#define	SPR_ICCFGR_NCW 0x00000007

#define	SPR_ICCFGR_NCS 0x00000078

#define	SPR_ICCFGR_CBS 0x00000080

#define	SPR_ICCFGR_CCRI 0x00000200

#define	SPR_ICCFGR_CBIRI 0x00000400

#define	SPR_ICCFGR_CBPRI 0x00000800

#define	SPR_ICCFGR_CBLRI 0x00001000

#define	SPR_ICCFGR_NCW_OFF 0

#define	SPR_ICCFGR_NCS_OFF 3

#define	SPR_ICCFGR_CBS_OFF 7

#define	SPR_DMMUCFGR_NTW 0x00000003

#define	SPR_DMMUCFGR_NTS 0x0000001C

#define	SPR_DMMUCFGR_NAE 0x000000E0

#define	SPR_DMMUCFGR_CRI 0x00000100

#define	SPR_DMMUCFGR_PRI 0x00000200

#define	SPR_DMMUCFGR_TEIRI 0x00000400

#define	SPR_DMMUCFGR_HTR 0x00000800

#define	SPR_DMMUCFGR_NTW_OFF 0

#define	SPR_DMMUCFGR_NTS_OFF 2

#define	SPR_IMMUCFGR_NTW 0x00000003

#define	SPR_IMMUCFGR_NTS 0x0000001C

#define	SPR_IMMUCFGR_NAE 0x000000E0

#define	SPR_IMMUCFGR_CRI 0x00000100

#define	SPR_IMMUCFGR_PRI 0x00000200

#define	SPR_IMMUCFGR_TEIRI 0x00000400

#define	SPR_IMMUCFGR_HTR 0x00000800

#define	SPR_IMMUCFGR_NTW_OFF 0

#define	SPR_IMMUCFGR_NTS_OFF 2

#define	SPR_DCR_DP 0x00000001 /* DVR/DCR present */

#define	SPR_DCR_CC 0x0000000e /* Compare condition */

#define	SPR_DCR_SC 0x00000010 /* Signed compare */

#define	SPR_DCR_CT 0x000000e0 /* Compare to */

#define	SPR_DCR_CC_MASKED 0x00000000

#define	SPR_DCR_CC_EQUAL 0x00000002

#define	SPR_DCR_CC_LESS 0x00000004

#define	SPR_DCR_CC_LESSE 0x00000006

#define	SPR_DCR_CC_GREAT 0x00000008

#define	SPR_DCR_CC_GREATE 0x0000000a

#define	SPR_DCR_CC_NEQUAL 0x0000000c

#define	SPR_DCR_CT_DISABLED 0x00000000

#define	SPR_DCR_CT_IFEA 0x00000020

#define	SPR_DCR_CT_LEA 0x00000040

#define	SPR_DCR_CT_SEA 0x00000060

#define	SPR_DCR_CT_LD 0x00000080

#define	SPR_DCR_CT_SD 0x000000a0

#define	SPR_DCR_CT_LSEA 0x000000c0

#define	SPR_DCR_CT_LSD 0x000000e0

#define	SPR_DMR1_CW 0x000fffff /* Chain register pair data */

#define	SPR_DMR1_CW0_AND 0x00000001

#define	SPR_DMR1_CW0_OR 0x00000002

#define	SPR_DMR1_CW0 (SPR_DMR1_CW0_AND \| SPR_DMR1_CW0_OR)

#define	SPR_DMR1_CW1_AND 0x00000004

#define	SPR_DMR1_CW1_OR 0x00000008

#define	SPR_DMR1_CW1 (SPR_DMR1_CW1_AND \| SPR_DMR1_CW1_OR)

#define	SPR_DMR1_CW2_AND 0x00000010

#define	SPR_DMR1_CW2_OR 0x00000020

#define	SPR_DMR1_CW2 (SPR_DMR1_CW2_AND \| SPR_DMR1_CW2_OR)

#define	SPR_DMR1_CW3_AND 0x00000040

#define	SPR_DMR1_CW3_OR 0x00000080

#define	SPR_DMR1_CW3 (SPR_DMR1_CW3_AND \| SPR_DMR1_CW3_OR)

#define	SPR_DMR1_CW4_AND 0x00000100

#define	SPR_DMR1_CW4_OR 0x00000200

#define	SPR_DMR1_CW4 (SPR_DMR1_CW4_AND \| SPR_DMR1_CW4_OR)

#define	SPR_DMR1_CW5_AND 0x00000400

#define	SPR_DMR1_CW5_OR 0x00000800

#define	SPR_DMR1_CW5 (SPR_DMR1_CW5_AND \| SPR_DMR1_CW5_OR)

#define	SPR_DMR1_CW6_AND 0x00001000

#define	SPR_DMR1_CW6_OR 0x00002000

#define	SPR_DMR1_CW6 (SPR_DMR1_CW6_AND \| SPR_DMR1_CW6_OR)

#define	SPR_DMR1_CW7_AND 0x00004000

#define	SPR_DMR1_CW7_OR 0x00008000

#define	SPR_DMR1_CW7 (SPR_DMR1_CW7_AND \| SPR_DMR1_CW7_OR)

#define	SPR_DMR1_CW8_AND 0x00010000

#define	SPR_DMR1_CW8_OR 0x00020000

#define	SPR_DMR1_CW8 (SPR_DMR1_CW8_AND \| SPR_DMR1_CW8_OR)

#define	SPR_DMR1_CW9_AND 0x00040000

#define	SPR_DMR1_CW9_OR 0x00080000

#define	SPR_DMR1_CW9 (SPR_DMR1_CW9_AND \| SPR_DMR1_CW9_OR)

#define	SPR_DMR1_RES1 0x00300000 /* Reserved */

#define	SPR_DMR1_ST 0x00400000 /* Single-step trace*/

#define	SPR_DMR1_BT 0x00800000 /* Branch trace */

#define	SPR_DMR1_RES2 0xff000000 /* Reserved */

#define	SPR_DMR2_WCE0 0x00000001 /* Watchpoint counter 0 enable */

#define	SPR_DMR2_WCE1 0x00000002 /* Watchpoint counter 0 enable */

#define	SPR_DMR2_AWTC 0x00000ffc /* Assign watchpoints to counters */

#define	SPR_DMR2_AWTC_OFF 2 /* Bit offset to AWTC field */

#define	SPR_DMR2_WGB 0x003ff000 /* Watchpoints generating breakpoint */

#define	SPR_DMR2_WGB_OFF 12 /* Bit offset to WGB field */

#define	SPR_DMR2_WBS 0xffc00000 /* JPB: Watchpoint status */

#define	SPR_DMR2_WBS_OFF 22 /* Bit offset to WBS field */

#define	SPR_DWCR_COUNT 0x0000ffff /* Count */

#define	SPR_DWCR_MATCH 0xffff0000 /* Match */

#define	SPR_DWCR_MATCH_OFF 16 /* Match bit offset */

#define	SPR_DSR_RSTE 0x00000001 /* Reset exception */

#define	SPR_DSR_BUSEE 0x00000002 /* Bus error exception */

#define	SPR_DSR_DPFE 0x00000004 /* Data Page Fault exception */

#define	SPR_DSR_IPFE 0x00000008 /* Insn Page Fault exception */

#define	SPR_DSR_TTE 0x00000010 /* Tick Timer exception */

#define	SPR_DSR_AE 0x00000020 /* Alignment exception */

#define	SPR_DSR_IIE 0x00000040 /* Illegal Instruction exception */

#define	SPR_DSR_IE 0x00000080 /* Interrupt exception */

#define	SPR_DSR_DME 0x00000100 /* DTLB miss exception */

#define	SPR_DSR_IME 0x00000200 /* ITLB miss exception */

#define	SPR_DSR_RE 0x00000400 /* Range exception */

#define	SPR_DSR_SCE 0x00000800 /* System call exception */

#define	SPR_DSR_FPE 0x00001000 /* Floating Point Exception */

#define	SPR_DSR_TE 0x00002000 /* Trap exception */

#define	SPR_DRR_RSTE 0x00000001 /* Reset exception */

#define	SPR_DRR_BUSEE 0x00000002 /* Bus error exception */

#define	SPR_DRR_DPFE 0x00000004 /* Data Page Fault exception */

#define	SPR_DRR_IPFE 0x00000008 /* Insn Page Fault exception */

#define	SPR_DRR_TTE 0x00000010 /* Tick Timer exception */

#define	SPR_DRR_AE 0x00000020 /* Alignment exception */

#define	SPR_DRR_IIE 0x00000040 /* Illegal Instruction exception */

#define	SPR_DRR_IE 0x00000080 /* Interrupt exception */

#define	SPR_DRR_DME 0x00000100 /* DTLB miss exception */

#define	SPR_DRR_IME 0x00000200 /* ITLB miss exception */

#define	SPR_DRR_RE 0x00000400 /* Range exception */

#define	SPR_DRR_SCE 0x00000800 /* System call exception */

#define	SPR_DRR_FPE 0x00001000 /* Floating Point Exception */

#define	SPR_DRR_TE 0x00002000 /* Trap exception */

#define	SPR_PCMR_CP 0x00000001 /* Counter present */

#define	SPR_PCMR_UMRA 0x00000002 /* User mode read access */

#define	SPR_PCMR_CISM 0x00000004 /* Count in supervisor mode */

#define	SPR_PCMR_CIUM 0x00000008 /* Count in user mode */

#define	SPR_PCMR_LA 0x00000010 /* Load access event */

#define	SPR_PCMR_SA 0x00000020 /* Store access event */

#define	SPR_PCMR_IF 0x00000040 /* Instruction fetch event*/

#define	SPR_PCMR_DCM 0x00000080 /* Data cache miss event */

#define	SPR_PCMR_ICM 0x00000100 /* Insn cache miss event */

#define	SPR_PCMR_IFS 0x00000200 /* Insn fetch stall event */

#define	SPR_PCMR_LSUS 0x00000400 /* LSU stall event */

#define	SPR_PCMR_BS 0x00000800 /* Branch stall event */

#define	SPR_PCMR_DTLBM 0x00001000 /* DTLB miss event */

#define	SPR_PCMR_ITLBM 0x00002000 /* ITLB miss event */

#define	SPR_PCMR_DDS 0x00004000 /* Data dependency stall event */

#define	SPR_PCMR_WPE 0x03ff8000 /* Watchpoint events */

#define	SPR_PMR_SDF 0x0000000f /* Slow down factor */

#define	SPR_PMR_DME 0x00000010 /* Doze mode enable */

#define	SPR_PMR_SME 0x00000020 /* Sleep mode enable */

#define	SPR_PMR_DCGE 0x00000040 /* Dynamic clock gating enable */

#define	SPR_PMR_SUME 0x00000080 /* Suspend mode enable */

#define	SPR_PICMR_IUM 0xfffffffc /* Interrupt unmask */

#define	SPR_PICPR_IPRIO 0xfffffffc /* Interrupt priority */

#define	SPR_PICSR_IS 0xffffffff /* Interrupt status */

#define	SPR_TTCR_CNT 0xffffffff /* Count, time period */

#define	SPR_TTMR_TP 0x0fffffff /* Time period */

#define	SPR_TTMR_IP 0x10000000 /* Interrupt Pending */

#define	SPR_TTMR_IE 0x20000000 /* Interrupt Enable */

#define	SPR_TTMR_DI 0x00000000 /* Disabled */

#define	SPR_TTMR_RT 0x40000000 /* Restart tick */

#define	SPR_TTMR_SR 0x80000000 /* Single run */

#define	SPR_TTMR_CR 0xc0000000 /* Continuous run */

#define	SPR_TTMR_M 0xc0000000 /* Tick mode */

#define	SPR_FPCSR_FPEE 0x00000001 /* Floating Point Exception Enable */

#define	SPR_FPCSR_RM 0x00000006 /* Rounding Mode */

#define	SPR_FPCSR_OVF 0x00000008 /* Overflow Flag */

#define	SPR_FPCSR_UNF 0x00000010 /* Underflow Flag */

#define	SPR_FPCSR_SNF 0x00000020 /* SNAN Flag */

#define	SPR_FPCSR_QNF 0x00000040 /* QNAN Flag */

#define	SPR_FPCSR_ZF 0x00000080 /* Zero Flag */

#define	SPR_FPCSR_IXF 0x00000100 /* Inexact Flag */

#define	SPR_FPCSR_IVF 0x00000200 /* Invalid Flag */

#define	SPR_FPCSR_INF 0x00000400 /* Infinity Flag */

#define	SPR_FPCSR_DZF 0x00000800 /* Divide By Zero Flag */

#define	SPR_FPCSR_ALLF

#define	FPCSR_RM_RN (0<<1)

#define	FPCSR_RM_RZ (1<<1)

#define	FPCSR_RM_RIP (2<<1)

#define	FPCSR_RM_RIN (3<<1)

#define	NOP_NOP 0x0000 /* Normal nop instruction */

#define	NOP_EXIT 0x0001 /* End of simulation */

#define	NOP_REPORT 0x0002 /* Simple report */

#define	NOP_PUTC 0x0004 /* JPB: Simputc instruction */

#define	NOP_CNT_RESET 0x0005 /* Reset statistics counters */

#define	NOP_GET_TICKS 0x0006 /* JPB: Get # ticks running */

#define	NOP_GET_PS 0x0007 /* JPB: Get picosecs/cycle */

#define	NOP_REPORT_FIRST 0x0400 /* Report with number */

#define	NOP_REPORT_LAST 0x03ff /* Report with number */

Macro Definition Documentation

#define FPCSR_RM_RIN (3<<1)

Definition at line 587 of file spr_defs.h.

#define FPCSR_RM_RIP (2<<1)

Definition at line 586 of file spr_defs.h.

#define FPCSR_RM_RN (0<<1)

Definition at line 584 of file spr_defs.h.

#define FPCSR_RM_RZ (1<<1)

Definition at line 585 of file spr_defs.h.

#define MATCHPOINTS_TO_NDP ( n )

Value:

(1 == n ? SPR_DCFGR_NDP1 : \
                               2 == n ? SPR_DCFGR_NDP2 : \
                               3 == n ? SPR_DCFGR_NDP3 : \
                               4 == n ? SPR_DCFGR_NDP4 : \
                               5 == n ? SPR_DCFGR_NDP5 : \
                               6 == n ? SPR_DCFGR_NDP6 : \
                               7 == n ? SPR_DCFGR_NDP7 : SPR_DCFGR_NDP8)

Definition at line 191 of file spr_defs.h.

#define MAX_GRPS (32)

Definition at line 25 of file spr_defs.h.

#define MAX_MATCHPOINTS 8

Definition at line 198 of file spr_defs.h.

#define MAX_SPRS (0x10000)

Definition at line 28 of file spr_defs.h.

#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS)

Definition at line 27 of file spr_defs.h.

#define MAX_SPRS_PER_GRP_BITS (11)

Definition at line 26 of file spr_defs.h.

#define MAX_WATCHPOINTS (MAX_MATCHPOINTS + 2)

Definition at line 199 of file spr_defs.h.

#define NOP_CNT_RESET 0x0005 /* Reset statistics counters */

Definition at line 598 of file spr_defs.h.

#define NOP_EXIT 0x0001 /* End of simulation */

Definition at line 594 of file spr_defs.h.

#define NOP_GET_PS 0x0007 /* JPB: Get picosecs/cycle */

Definition at line 600 of file spr_defs.h.

#define NOP_GET_TICKS 0x0006 /* JPB: Get # ticks running */

Definition at line 599 of file spr_defs.h.

#define NOP_NOP 0x0000 /* Normal nop instruction */

Definition at line 593 of file spr_defs.h.

#define NOP_PUTC 0x0004 /* JPB: Simputc instruction */

Definition at line 597 of file spr_defs.h.

#define NOP_REPORT 0x0002 /* Simple report */

Definition at line 595 of file spr_defs.h.

#define NOP_REPORT_FIRST 0x0400 /* Report with number */

Definition at line 601 of file spr_defs.h.

#define NOP_REPORT_LAST 0x03ff /* Report with number */

Definition at line 602 of file spr_defs.h.

#define SPR_CPUCFGR (SPRGROUP_SYS + 2)

Definition at line 47 of file spr_defs.h.

#define SPR_CPUCFGR_CGF 0x00000010 /* Custom GPR file */

Definition at line 166 of file spr_defs.h.

#define SPR_CPUCFGR_NSGF 0x0000000f /* Number of shadow GPR files */

Definition at line 165 of file spr_defs.h.

#define SPR_CPUCFGR_OB32S 0x00000020 /* ORBIS32 supported */

Definition at line 167 of file spr_defs.h.

#define SPR_CPUCFGR_OB64S 0x00000040 /* ORBIS64 supported */

Definition at line 168 of file spr_defs.h.

#define SPR_CPUCFGR_OF32S 0x00000080 /* ORFPX32 supported */

Definition at line 169 of file spr_defs.h.

#define SPR_CPUCFGR_OF64S 0x00000100 /* ORFPX64 supported */

Definition at line 170 of file spr_defs.h.

#define SPR_CPUCFGR_OV64S 0x00000200 /* ORVDX64 supported */

Definition at line 171 of file spr_defs.h.

#define SPR_CPUCFGR_RES 0xfffffc00 /* Reserved */

Definition at line 172 of file spr_defs.h.

#define SPR_DCBFR (SPRGROUP_DC + 2)

Definition at line 85 of file spr_defs.h.

#define SPR_DCBIR (SPRGROUP_DC + 3)

Definition at line 86 of file spr_defs.h.

#define SPR_DCBLR (SPRGROUP_DC + 5)

Definition at line 88 of file spr_defs.h.

#define SPR_DCBPR (SPRGROUP_DC + 1)

Definition at line 84 of file spr_defs.h.

#define SPR_DCBWR (SPRGROUP_DC + 4)

Definition at line 87 of file spr_defs.h.

#define SPR_DCCFGR (SPRGROUP_SYS + 5)

Definition at line 50 of file spr_defs.h.

#define SPR_DCCFGR_CBFRI 0x00002000

Definition at line 318 of file spr_defs.h.

#define SPR_DCCFGR_CBIRI 0x00000400

Definition at line 315 of file spr_defs.h.

#define SPR_DCCFGR_CBLRI 0x00001000

Definition at line 317 of file spr_defs.h.

#define SPR_DCCFGR_CBPRI 0x00000800

Definition at line 316 of file spr_defs.h.

#define SPR_DCCFGR_CBS 0x00000080

Definition at line 312 of file spr_defs.h.

#define SPR_DCCFGR_CBS_OFF 7

Definition at line 323 of file spr_defs.h.

#define SPR_DCCFGR_CBWBRI 0x00004000

Definition at line 319 of file spr_defs.h.

#define SPR_DCCFGR_CCRI 0x00000200

Definition at line 314 of file spr_defs.h.

#define SPR_DCCFGR_CWS 0x00000100

Definition at line 313 of file spr_defs.h.

#define SPR_DCCFGR_NCS 0x00000078

Definition at line 311 of file spr_defs.h.

#define SPR_DCCFGR_NCS_OFF 3

Definition at line 322 of file spr_defs.h.

#define SPR_DCCFGR_NCW 0x00000007

Definition at line 310 of file spr_defs.h.

#define SPR_DCCFGR_NCW_OFF 0

Definition at line 321 of file spr_defs.h.

#define SPR_DCCR (SPRGROUP_DC + 0)

Definition at line 83 of file spr_defs.h.

#define SPR_DCCR_EW 0x000000ff /* Enable ways */

Definition at line 297 of file spr_defs.h.

#define SPR_DCFGR (SPRGROUP_SYS + 7)

Definition at line 52 of file spr_defs.h.

#define SPR_DCFGR_NDP 0x00000007 /* Number of matchpoints mask */

Definition at line 180 of file spr_defs.h.

#define SPR_DCFGR_NDP1 0x00000000 /* One matchpoint supported */

Definition at line 181 of file spr_defs.h.

#define SPR_DCFGR_NDP2 0x00000001 /* Two matchpoints supported */

Definition at line 182 of file spr_defs.h.

#define SPR_DCFGR_NDP3 0x00000002 /* Three matchpoints supported */

Definition at line 183 of file spr_defs.h.

#define SPR_DCFGR_NDP4 0x00000003 /* Four matchpoints supported */

Definition at line 184 of file spr_defs.h.

#define SPR_DCFGR_NDP5 0x00000004 /* Five matchpoints supported */

Definition at line 185 of file spr_defs.h.

#define SPR_DCFGR_NDP6 0x00000005 /* Six matchpoints supported */

Definition at line 186 of file spr_defs.h.

#define SPR_DCFGR_NDP7 0x00000006 /* Seven matchpoints supported */

Definition at line 187 of file spr_defs.h.

#define SPR_DCFGR_NDP8 0x00000007 /* Eight matchpoints supported */

Definition at line 188 of file spr_defs.h.

#define SPR_DCFGR_WPCI 0x00000008 /* Watchpoint counters implemented */

Definition at line 189 of file spr_defs.h.

#define SPR_DCR ( N ) (SPRGROUP_D + 8 + (N))

Definition at line 106 of file spr_defs.h.

#define SPR_DCR_BASE ( WAY ) (SPRGROUP_DC + 0x200 + (WAY) * 0x200)

Definition at line 89 of file spr_defs.h.

#define SPR_DCR_CC 0x0000000e /* Compare condition */

Definition at line 378 of file spr_defs.h.

#define SPR_DCR_CC_EQUAL 0x00000002

Definition at line 384 of file spr_defs.h.

#define SPR_DCR_CC_GREAT 0x00000008

Definition at line 387 of file spr_defs.h.

#define SPR_DCR_CC_GREATE 0x0000000a

Definition at line 388 of file spr_defs.h.

#define SPR_DCR_CC_LESS 0x00000004

Definition at line 385 of file spr_defs.h.

#define SPR_DCR_CC_LESSE 0x00000006

Definition at line 386 of file spr_defs.h.

#define SPR_DCR_CC_MASKED 0x00000000

Definition at line 383 of file spr_defs.h.

#define SPR_DCR_CC_NEQUAL 0x0000000c

Definition at line 389 of file spr_defs.h.

#define SPR_DCR_CT 0x000000e0 /* Compare to */

Definition at line 380 of file spr_defs.h.

#define SPR_DCR_CT_DISABLED 0x00000000

Definition at line 392 of file spr_defs.h.

#define SPR_DCR_CT_IFEA 0x00000020

Definition at line 393 of file spr_defs.h.

#define SPR_DCR_CT_LD 0x00000080

Definition at line 396 of file spr_defs.h.

#define SPR_DCR_CT_LEA 0x00000040

Definition at line 394 of file spr_defs.h.

#define SPR_DCR_CT_LSD 0x000000e0

Definition at line 399 of file spr_defs.h.

#define SPR_DCR_CT_LSEA 0x000000c0

Definition at line 398 of file spr_defs.h.

#define SPR_DCR_CT_SD 0x000000a0

Definition at line 397 of file spr_defs.h.

#define SPR_DCR_CT_SEA 0x00000060

Definition at line 395 of file spr_defs.h.

#define SPR_DCR_DP 0x00000001 /* DVR/DCR present */

Definition at line 377 of file spr_defs.h.

#define SPR_DCR_LAST ( WAY ) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200)

Definition at line 90 of file spr_defs.h.

#define SPR_DCR_SC 0x00000010 /* Signed compare */

Definition at line 379 of file spr_defs.h.

#define SPR_DMMUCFGR (SPRGROUP_SYS + 3)

Definition at line 48 of file spr_defs.h.

#define SPR_DMMUCFGR_CRI 0x00000100

Definition at line 349 of file spr_defs.h.

#define SPR_DMMUCFGR_HTR 0x00000800

Definition at line 352 of file spr_defs.h.

#define SPR_DMMUCFGR_NAE 0x000000E0

Definition at line 348 of file spr_defs.h.

#define SPR_DMMUCFGR_NTS 0x0000001C

Definition at line 347 of file spr_defs.h.

#define SPR_DMMUCFGR_NTS_OFF 2

Definition at line 355 of file spr_defs.h.

#define SPR_DMMUCFGR_NTW 0x00000003

Definition at line 346 of file spr_defs.h.

#define SPR_DMMUCFGR_NTW_OFF 0

Definition at line 354 of file spr_defs.h.

#define SPR_DMMUCFGR_PRI 0x00000200

Definition at line 350 of file spr_defs.h.

#define SPR_DMMUCFGR_TEIRI 0x00000400

Definition at line 351 of file spr_defs.h.

#define SPR_DMMUCR (SPRGROUP_DMMU + 0)

Definition at line 67 of file spr_defs.h.

#define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */

Definition at line 230 of file spr_defs.h.

#define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */

Definition at line 229 of file spr_defs.h.

#define SPR_DMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */

Definition at line 232 of file spr_defs.h.

#define SPR_DMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */

Definition at line 231 of file spr_defs.h.

#define SPR_DMR1 (SPRGROUP_D + 16)

Definition at line 107 of file spr_defs.h.

#define SPR_DMR1_BT 0x00800000 /* Branch trace */

Definition at line 439 of file spr_defs.h.

#define SPR_DMR1_CW 0x000fffff /* Chain register pair data */

Definition at line 406 of file spr_defs.h.

#define SPR_DMR1_CW0 (SPR_DMR1_CW0_AND | SPR_DMR1_CW0_OR)

Definition at line 409 of file spr_defs.h.

#define SPR_DMR1_CW0_AND 0x00000001

Definition at line 407 of file spr_defs.h.

#define SPR_DMR1_CW0_OR 0x00000002

Definition at line 408 of file spr_defs.h.

#define SPR_DMR1_CW1 (SPR_DMR1_CW1_AND | SPR_DMR1_CW1_OR)

Definition at line 412 of file spr_defs.h.

#define SPR_DMR1_CW1_AND 0x00000004

Definition at line 410 of file spr_defs.h.

#define SPR_DMR1_CW1_OR 0x00000008

Definition at line 411 of file spr_defs.h.

#define SPR_DMR1_CW2 (SPR_DMR1_CW2_AND | SPR_DMR1_CW2_OR)

Definition at line 415 of file spr_defs.h.

#define SPR_DMR1_CW2_AND 0x00000010

Definition at line 413 of file spr_defs.h.

#define SPR_DMR1_CW2_OR 0x00000020

Definition at line 414 of file spr_defs.h.

#define SPR_DMR1_CW3 (SPR_DMR1_CW3_AND | SPR_DMR1_CW3_OR)

Definition at line 418 of file spr_defs.h.

#define SPR_DMR1_CW3_AND 0x00000040

Definition at line 416 of file spr_defs.h.

#define SPR_DMR1_CW3_OR 0x00000080

Definition at line 417 of file spr_defs.h.

#define SPR_DMR1_CW4 (SPR_DMR1_CW4_AND | SPR_DMR1_CW4_OR)

Definition at line 421 of file spr_defs.h.

#define SPR_DMR1_CW4_AND 0x00000100

Definition at line 419 of file spr_defs.h.

#define SPR_DMR1_CW4_OR 0x00000200

Definition at line 420 of file spr_defs.h.

#define SPR_DMR1_CW5 (SPR_DMR1_CW5_AND | SPR_DMR1_CW5_OR)

Definition at line 424 of file spr_defs.h.

#define SPR_DMR1_CW5_AND 0x00000400

Definition at line 422 of file spr_defs.h.

#define SPR_DMR1_CW5_OR 0x00000800

Definition at line 423 of file spr_defs.h.

#define SPR_DMR1_CW6 (SPR_DMR1_CW6_AND | SPR_DMR1_CW6_OR)

Definition at line 427 of file spr_defs.h.

#define SPR_DMR1_CW6_AND 0x00001000

Definition at line 425 of file spr_defs.h.

#define SPR_DMR1_CW6_OR 0x00002000

Definition at line 426 of file spr_defs.h.

#define SPR_DMR1_CW7 (SPR_DMR1_CW7_AND | SPR_DMR1_CW7_OR)

Definition at line 430 of file spr_defs.h.

#define SPR_DMR1_CW7_AND 0x00004000

Definition at line 428 of file spr_defs.h.

#define SPR_DMR1_CW7_OR 0x00008000

Definition at line 429 of file spr_defs.h.

#define SPR_DMR1_CW8 (SPR_DMR1_CW8_AND | SPR_DMR1_CW8_OR)

Definition at line 433 of file spr_defs.h.

#define SPR_DMR1_CW8_AND 0x00010000

Definition at line 431 of file spr_defs.h.

#define SPR_DMR1_CW8_OR 0x00020000

Definition at line 432 of file spr_defs.h.

#define SPR_DMR1_CW9 (SPR_DMR1_CW9_AND | SPR_DMR1_CW9_OR)

Definition at line 436 of file spr_defs.h.

#define SPR_DMR1_CW9_AND 0x00040000

Definition at line 434 of file spr_defs.h.

#define SPR_DMR1_CW9_OR 0x00080000

Definition at line 435 of file spr_defs.h.

#define SPR_DMR1_RES1 0x00300000 /* Reserved */

Definition at line 437 of file spr_defs.h.

#define SPR_DMR1_RES2 0xff000000 /* Reserved */

Definition at line 440 of file spr_defs.h.

#define SPR_DMR1_ST 0x00400000 /* Single-step trace*/

Definition at line 438 of file spr_defs.h.

#define SPR_DMR2 (SPRGROUP_D + 17)

Definition at line 108 of file spr_defs.h.

#define SPR_DMR2_AWTC 0x00000ffc /* Assign watchpoints to counters */

Definition at line 448 of file spr_defs.h.

#define SPR_DMR2_AWTC_OFF 2 /* Bit offset to AWTC field */

Definition at line 449 of file spr_defs.h.

#define SPR_DMR2_WBS 0xffc00000 /* JPB: Watchpoint status */

Definition at line 452 of file spr_defs.h.

#define SPR_DMR2_WBS_OFF 22 /* Bit offset to WBS field */

Definition at line 453 of file spr_defs.h.

#define SPR_DMR2_WCE0 0x00000001 /* Watchpoint counter 0 enable */

Definition at line 446 of file spr_defs.h.

#define SPR_DMR2_WCE1 0x00000002 /* Watchpoint counter 0 enable */

Definition at line 447 of file spr_defs.h.

#define SPR_DMR2_WGB 0x003ff000 /* Watchpoints generating breakpoint */

Definition at line 450 of file spr_defs.h.

#define SPR_DMR2_WGB_OFF 12 /* Bit offset to WGB field */

Definition at line 451 of file spr_defs.h.

#define SPR_DRR (SPRGROUP_D + 21)

Definition at line 112 of file spr_defs.h.

#define SPR_DRR_AE 0x00000020 /* Alignment exception */

Definition at line 491 of file spr_defs.h.

#define SPR_DRR_BUSEE 0x00000002 /* Bus error exception */

Definition at line 487 of file spr_defs.h.

#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */

Definition at line 494 of file spr_defs.h.

#define SPR_DRR_DPFE 0x00000004 /* Data Page Fault exception */

Definition at line 488 of file spr_defs.h.

#define SPR_DRR_FPE 0x00001000 /* Floating Point Exception */

Definition at line 498 of file spr_defs.h.

#define SPR_DRR_IE 0x00000080 /* Interrupt exception */

Definition at line 493 of file spr_defs.h.

#define SPR_DRR_IIE 0x00000040 /* Illegal Instruction exception */

Definition at line 492 of file spr_defs.h.

#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */

Definition at line 495 of file spr_defs.h.

#define SPR_DRR_IPFE 0x00000008 /* Insn Page Fault exception */

Definition at line 489 of file spr_defs.h.

#define SPR_DRR_RE 0x00000400 /* Range exception */

Definition at line 496 of file spr_defs.h.

#define SPR_DRR_RSTE 0x00000001 /* Reset exception */

Definition at line 486 of file spr_defs.h.

#define SPR_DRR_SCE 0x00000800 /* System call exception */

Definition at line 497 of file spr_defs.h.

#define SPR_DRR_TE 0x00002000 /* Trap exception */

Definition at line 499 of file spr_defs.h.

#define SPR_DRR_TTE 0x00000010 /* Tick Timer exception */

Definition at line 490 of file spr_defs.h.

#define SPR_DSR (SPRGROUP_D + 20)

Definition at line 111 of file spr_defs.h.

#define SPR_DSR_AE 0x00000020 /* Alignment exception */

Definition at line 472 of file spr_defs.h.

#define SPR_DSR_BUSEE 0x00000002 /* Bus error exception */

Definition at line 468 of file spr_defs.h.

#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */

Definition at line 475 of file spr_defs.h.

#define SPR_DSR_DPFE 0x00000004 /* Data Page Fault exception */

Definition at line 469 of file spr_defs.h.

#define SPR_DSR_FPE 0x00001000 /* Floating Point Exception */

Definition at line 479 of file spr_defs.h.

#define SPR_DSR_IE 0x00000080 /* Interrupt exception */

Definition at line 474 of file spr_defs.h.

#define SPR_DSR_IIE 0x00000040 /* Illegal Instruction exception */

Definition at line 473 of file spr_defs.h.

#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */

Definition at line 476 of file spr_defs.h.

#define SPR_DSR_IPFE 0x00000008 /* Insn Page Fault exception */

Definition at line 470 of file spr_defs.h.

#define SPR_DSR_RE 0x00000400 /* Range exception */

Definition at line 477 of file spr_defs.h.

#define SPR_DSR_RSTE 0x00000001 /* Reset exception */

Definition at line 467 of file spr_defs.h.

#define SPR_DSR_SCE 0x00000800 /* System call exception */

Definition at line 478 of file spr_defs.h.

#define SPR_DSR_TE 0x00002000 /* Trap exception */

Definition at line 480 of file spr_defs.h.

#define SPR_DSR_TTE 0x00000010 /* Tick Timer exception */

Definition at line 471 of file spr_defs.h.

#define SPR_DTLBEIR (SPRGROUP_DMMU + 2)

Definition at line 68 of file spr_defs.h.

#define SPR_DTLBMR_BASE ( WAY ) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)

Definition at line 69 of file spr_defs.h.

#define SPR_DTLBMR_CID 0x0000003c /* Context ID */

Definition at line 249 of file spr_defs.h.

#define SPR_DTLBMR_LAST ( WAY ) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)

Definition at line 70 of file spr_defs.h.

#define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */

Definition at line 250 of file spr_defs.h.

#define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */

Definition at line 248 of file spr_defs.h.

#define SPR_DTLBMR_V 0x00000001 /* Valid */

Definition at line 247 of file spr_defs.h.

#define SPR_DTLBMR_VPN 0xfffff000 /* Virtual Page Number */

Definition at line 251 of file spr_defs.h.

#define SPR_DTLBTR_A 0x00000010 /* Accessed */

Definition at line 261 of file spr_defs.h.

#define SPR_DTLBTR_BASE ( WAY ) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)

Definition at line 71 of file spr_defs.h.

#define SPR_DTLBTR_CC 0x00000001 /* Cache Coherency */

Definition at line 257 of file spr_defs.h.

#define SPR_DTLBTR_CI 0x00000002 /* Cache Inhibit */

Definition at line 258 of file spr_defs.h.

#define SPR_DTLBTR_D 0x00000020 /* Dirty */

Definition at line 262 of file spr_defs.h.

#define SPR_DTLBTR_LAST ( WAY ) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)

Definition at line 72 of file spr_defs.h.

#define SPR_DTLBTR_PPN 0xfffff000 /* Physical Page Number */

Definition at line 267 of file spr_defs.h.

#define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */

Definition at line 265 of file spr_defs.h.

#define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */

Definition at line 266 of file spr_defs.h.

#define SPR_DTLBTR_URE 0x00000040 /* User Read Enable */

Definition at line 263 of file spr_defs.h.

#define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */

Definition at line 264 of file spr_defs.h.

#define SPR_DTLBTR_WBC 0x00000004 /* Write-Back Cache */

Definition at line 259 of file spr_defs.h.

#define SPR_DTLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */

Definition at line 260 of file spr_defs.h.

#define SPR_DVR ( N ) (SPRGROUP_D + (N))

Definition at line 105 of file spr_defs.h.

#define SPR_DWCR0 (SPRGROUP_D + 18)

Definition at line 109 of file spr_defs.h.

#define SPR_DWCR1 (SPRGROUP_D + 19)

Definition at line 110 of file spr_defs.h.

#define SPR_DWCR_COUNT 0x0000ffff /* Count */

Definition at line 459 of file spr_defs.h.

#define SPR_DWCR_MATCH 0xffff0000 /* Match */

Definition at line 460 of file spr_defs.h.

#define SPR_DWCR_MATCH_OFF 16 /* Match bit offset */

Definition at line 461 of file spr_defs.h.

#define SPR_EEAR_BASE (SPRGROUP_SYS + 48)

Definition at line 60 of file spr_defs.h.

#define SPR_EEAR_LAST (SPRGROUP_SYS + 63)

Definition at line 61 of file spr_defs.h.

#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) /* CZ 21/06/01 */

Definition at line 58 of file spr_defs.h.

#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) /* CZ 21/06/01 */

Definition at line 59 of file spr_defs.h.

#define SPR_ESR_BASE (SPRGROUP_SYS + 64)

Definition at line 62 of file spr_defs.h.

#define SPR_ESR_LAST (SPRGROUP_SYS + 79)

Definition at line 63 of file spr_defs.h.

#define SPR_FPCSR (SPRGROUP_SYS + 20) /* CZ 21/06/01 */

Definition at line 57 of file spr_defs.h.

#define SPR_FPCSR_ALLF

Value:

(SPR_FPCSR_OVF | SPR_FPCSR_UNF | SPR_FPCSR_SNF | \
            SPR_FPCSR_QNF | SPR_FPCSR_ZF | SPR_FPCSR_IXF |  \
            SPR_FPCSR_IVF | SPR_FPCSR_INF | SPR_FPCSR_DZF)

Definition at line 580 of file spr_defs.h.

#define SPR_FPCSR_DZF 0x00000800 /* Divide By Zero Flag */

Definition at line 579 of file spr_defs.h.

#define SPR_FPCSR_FPEE 0x00000001 /* Floating Point Exception Enable */

Definition at line 569 of file spr_defs.h.

#define SPR_FPCSR_INF 0x00000400 /* Infinity Flag */

Definition at line 578 of file spr_defs.h.

#define SPR_FPCSR_IVF 0x00000200 /* Invalid Flag */

Definition at line 577 of file spr_defs.h.

#define SPR_FPCSR_IXF 0x00000100 /* Inexact Flag */

Definition at line 576 of file spr_defs.h.

#define SPR_FPCSR_OVF 0x00000008 /* Overflow Flag */

Definition at line 571 of file spr_defs.h.

#define SPR_FPCSR_QNF 0x00000040 /* QNAN Flag */

Definition at line 574 of file spr_defs.h.

#define SPR_FPCSR_RM 0x00000006 /* Rounding Mode */

Definition at line 570 of file spr_defs.h.

#define SPR_FPCSR_SNF 0x00000020 /* SNAN Flag */

Definition at line 573 of file spr_defs.h.

#define SPR_FPCSR_UNF 0x00000010 /* Underflow Flag */

Definition at line 572 of file spr_defs.h.

#define SPR_FPCSR_ZF 0x00000080 /* Zero Flag */

Definition at line 575 of file spr_defs.h.

#define SPR_GPR_BASE (SPRGROUP_SYS + 1024)

Definition at line 64 of file spr_defs.h.

#define SPR_ICBIR (SPRGROUP_IC + 2)

Definition at line 95 of file spr_defs.h.

#define SPR_ICBLR (SPRGROUP_IC + 3)

Definition at line 96 of file spr_defs.h.

#define SPR_ICBPR (SPRGROUP_IC + 1)

Definition at line 94 of file spr_defs.h.

#define SPR_ICCFGR (SPRGROUP_SYS + 6)

Definition at line 51 of file spr_defs.h.

#define SPR_ICCFGR_CBIRI 0x00000400

Definition at line 333 of file spr_defs.h.

#define SPR_ICCFGR_CBLRI 0x00001000

Definition at line 335 of file spr_defs.h.

#define SPR_ICCFGR_CBPRI 0x00000800

Definition at line 334 of file spr_defs.h.

#define SPR_ICCFGR_CBS 0x00000080

Definition at line 331 of file spr_defs.h.

#define SPR_ICCFGR_CBS_OFF 7

Definition at line 339 of file spr_defs.h.

#define SPR_ICCFGR_CCRI 0x00000200

Definition at line 332 of file spr_defs.h.

#define SPR_ICCFGR_NCS 0x00000078

Definition at line 330 of file spr_defs.h.

#define SPR_ICCFGR_NCS_OFF 3

Definition at line 338 of file spr_defs.h.

#define SPR_ICCFGR_NCW 0x00000007

Definition at line 329 of file spr_defs.h.

#define SPR_ICCFGR_NCW_OFF 0

Definition at line 337 of file spr_defs.h.

#define SPR_ICCR (SPRGROUP_IC + 0)

Definition at line 93 of file spr_defs.h.

#define SPR_ICCR_EW 0x000000ff /* Enable ways */

Definition at line 303 of file spr_defs.h.

#define SPR_ICR_BASE ( WAY ) (SPRGROUP_IC + 0x200 + (WAY) * 0x200)

Definition at line 97 of file spr_defs.h.

#define SPR_ICR_LAST ( WAY ) (SPRGROUP_IC + 0x3ff + (WAY) * 0x200)

Definition at line 98 of file spr_defs.h.

#define SPR_IMMUCFGR (SPRGROUP_SYS + 4)

Definition at line 49 of file spr_defs.h.

#define SPR_IMMUCFGR_CRI 0x00000100

Definition at line 365 of file spr_defs.h.

#define SPR_IMMUCFGR_HTR 0x00000800

Definition at line 368 of file spr_defs.h.

#define SPR_IMMUCFGR_NAE 0x000000E0

Definition at line 364 of file spr_defs.h.

#define SPR_IMMUCFGR_NTS 0x0000001C

Definition at line 363 of file spr_defs.h.

#define SPR_IMMUCFGR_NTS_OFF 2

Definition at line 371 of file spr_defs.h.

#define SPR_IMMUCFGR_NTW 0x00000003

Definition at line 362 of file spr_defs.h.

#define SPR_IMMUCFGR_NTW_OFF 0

Definition at line 370 of file spr_defs.h.

#define SPR_IMMUCFGR_PRI 0x00000200

Definition at line 366 of file spr_defs.h.

#define SPR_IMMUCFGR_TEIRI 0x00000400

Definition at line 367 of file spr_defs.h.

#define SPR_IMMUCR (SPRGROUP_IMMU + 0)

Definition at line 75 of file spr_defs.h.

#define SPR_IMMUCR_P1S 0x000007c0 /* Level 1 Page Size */

Definition at line 239 of file spr_defs.h.

#define SPR_IMMUCR_P2S 0x0000003e /* Level 2 Page Size */

Definition at line 238 of file spr_defs.h.

#define SPR_IMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */

Definition at line 241 of file spr_defs.h.

#define SPR_IMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */

Definition at line 240 of file spr_defs.h.

#define SPR_ITLBEIR (SPRGROUP_IMMU + 2)

Definition at line 76 of file spr_defs.h.

#define SPR_ITLBMR_BASE ( WAY ) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)

Definition at line 77 of file spr_defs.h.

#define SPR_ITLBMR_CID 0x0000003c /* Context ID */

Definition at line 275 of file spr_defs.h.

#define SPR_ITLBMR_LAST ( WAY ) (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100)

Definition at line 78 of file spr_defs.h.

#define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */

Definition at line 276 of file spr_defs.h.

#define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */

Definition at line 274 of file spr_defs.h.

#define SPR_ITLBMR_V 0x00000001 /* Valid */

Definition at line 273 of file spr_defs.h.

#define SPR_ITLBMR_VPN 0xfffff000 /* Virtual Page Number */

Definition at line 277 of file spr_defs.h.

#define SPR_ITLBTR_A 0x00000010 /* Accessed */

Definition at line 287 of file spr_defs.h.

#define SPR_ITLBTR_BASE ( WAY ) (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100)

Definition at line 79 of file spr_defs.h.

#define SPR_ITLBTR_CC 0x00000001 /* Cache Coherency */

Definition at line 283 of file spr_defs.h.

#define SPR_ITLBTR_CI 0x00000002 /* Cache Inhibit */

Definition at line 284 of file spr_defs.h.

#define SPR_ITLBTR_D 0x00000020 /* Dirty */

Definition at line 288 of file spr_defs.h.

#define SPR_ITLBTR_LAST ( WAY ) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100)

Definition at line 80 of file spr_defs.h.

#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */

Definition at line 291 of file spr_defs.h.

#define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */

Definition at line 289 of file spr_defs.h.

#define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */

Definition at line 290 of file spr_defs.h.

#define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */

Definition at line 285 of file spr_defs.h.

#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */

Definition at line 286 of file spr_defs.h.

#define SPR_MACHI (SPRGROUP_MAC + 2)

Definition at line 102 of file spr_defs.h.

#define SPR_MACLO (SPRGROUP_MAC + 1)

Definition at line 101 of file spr_defs.h.

#define SPR_NPC (SPRGROUP_SYS + 16) /* CZ 21/06/01 */

Definition at line 54 of file spr_defs.h.

#define SPR_PCCFGR (SPRGROUP_SYS + 8)

Definition at line 53 of file spr_defs.h.

#define SPR_PCCR ( N ) (SPRGROUP_PC + (N))

Definition at line 115 of file spr_defs.h.

#define SPR_PCMR ( N ) (SPRGROUP_PC + 8 + (N))

Definition at line 116 of file spr_defs.h.

#define SPR_PCMR_BS 0x00000800 /* Branch stall event */

Definition at line 516 of file spr_defs.h.

#define SPR_PCMR_CISM 0x00000004 /* Count in supervisor mode */

Definition at line 507 of file spr_defs.h.

#define SPR_PCMR_CIUM 0x00000008 /* Count in user mode */

Definition at line 508 of file spr_defs.h.

#define SPR_PCMR_CP 0x00000001 /* Counter present */

Definition at line 505 of file spr_defs.h.

#define SPR_PCMR_DCM 0x00000080 /* Data cache miss event */

Definition at line 512 of file spr_defs.h.

#define SPR_PCMR_DDS 0x00004000 /* Data dependency stall event */

Definition at line 519 of file spr_defs.h.

#define SPR_PCMR_DTLBM 0x00001000 /* DTLB miss event */

Definition at line 517 of file spr_defs.h.

#define SPR_PCMR_ICM 0x00000100 /* Insn cache miss event */

Definition at line 513 of file spr_defs.h.

#define SPR_PCMR_IF 0x00000040 /* Instruction fetch event*/

Definition at line 511 of file spr_defs.h.

#define SPR_PCMR_IFS 0x00000200 /* Insn fetch stall event */

Definition at line 514 of file spr_defs.h.

#define SPR_PCMR_ITLBM 0x00002000 /* ITLB miss event */

Definition at line 518 of file spr_defs.h.

#define SPR_PCMR_LA 0x00000010 /* Load access event */

Definition at line 509 of file spr_defs.h.

#define SPR_PCMR_LSUS 0x00000400 /* LSU stall event */

Definition at line 515 of file spr_defs.h.

#define SPR_PCMR_SA 0x00000020 /* Store access event */

Definition at line 510 of file spr_defs.h.

#define SPR_PCMR_UMRA 0x00000002 /* User mode read access */

Definition at line 506 of file spr_defs.h.

#define SPR_PCMR_WPE 0x03ff8000 /* Watchpoint events */

Definition at line 520 of file spr_defs.h.

#define SPR_PICMR (SPRGROUP_PIC + 0)

Definition at line 122 of file spr_defs.h.

#define SPR_PICMR_IUM 0xfffffffc /* Interrupt unmask */

Definition at line 536 of file spr_defs.h.

#define SPR_PICPR (SPRGROUP_PIC + 1)

Definition at line 123 of file spr_defs.h.

#define SPR_PICPR_IPRIO 0xfffffffc /* Interrupt priority */

Definition at line 542 of file spr_defs.h.

#define SPR_PICSR (SPRGROUP_PIC + 2)

Definition at line 124 of file spr_defs.h.

#define SPR_PICSR_IS 0xffffffff /* Interrupt status */

Definition at line 548 of file spr_defs.h.

#define SPR_PMR (SPRGROUP_PM + 0)

Definition at line 119 of file spr_defs.h.

#define SPR_PMR_DCGE 0x00000040 /* Dynamic clock gating enable */

Definition at line 529 of file spr_defs.h.

#define SPR_PMR_DME 0x00000010 /* Doze mode enable */

Definition at line 527 of file spr_defs.h.

#define SPR_PMR_SDF 0x0000000f /* Slow down factor */

Definition at line 526 of file spr_defs.h.

#define SPR_PMR_SME 0x00000020 /* Sleep mode enable */

Definition at line 528 of file spr_defs.h.

#define SPR_PMR_SUME 0x00000080 /* Suspend mode enable */

Definition at line 530 of file spr_defs.h.

#define SPR_PPC (SPRGROUP_SYS + 18) /* CZ 21/06/01 */

Definition at line 56 of file spr_defs.h.

#define SPR_SR (SPRGROUP_SYS + 17) /* CZ 21/06/01 */

Definition at line 55 of file spr_defs.h.

#define SPR_SR_CE 0x00000100 /* CID Enable */

Definition at line 213 of file spr_defs.h.

#define SPR_SR_CID 0xf0000000 /* Context ID */

Definition at line 223 of file spr_defs.h.

#define SPR_SR_CY 0x00000400 /* Carry flag */

Definition at line 215 of file spr_defs.h.

#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */

Definition at line 208 of file spr_defs.h.

#define SPR_SR_DME 0x00000020 /* Data MMU Enable */

Definition at line 210 of file spr_defs.h.

#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */

Definition at line 218 of file spr_defs.h.

#define SPR_SR_EPH 0x00004000 /* Exception Prefix High */

Definition at line 219 of file spr_defs.h.

#define SPR_SR_F 0x00000200 /* Condition Flag */

Definition at line 214 of file spr_defs.h.

#define SPR_SR_FO 0x00008000 /* Fixed one */

Definition at line 220 of file spr_defs.h.

#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */

Definition at line 209 of file spr_defs.h.

#define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */

Definition at line 207 of file spr_defs.h.

#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */

Definition at line 211 of file spr_defs.h.

#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */

Definition at line 212 of file spr_defs.h.

#define SPR_SR_OV 0x00000800 /* Overflow flag */

Definition at line 216 of file spr_defs.h.

#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */

Definition at line 217 of file spr_defs.h.

#define SPR_SR_RES 0x0ffe0000 /* Reserved */

Definition at line 222 of file spr_defs.h.

#define SPR_SR_SM 0x00000001 /* Supervisor Mode */

Definition at line 205 of file spr_defs.h.

#define SPR_SR_SUMRA 0x00010000 /* Supervisor SPR read access */

Definition at line 221 of file spr_defs.h.

#define SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */

Definition at line 206 of file spr_defs.h.

#define SPR_TTCR (SPRGROUP_TT + 1)

Definition at line 128 of file spr_defs.h.

#define SPR_TTCR_CNT 0xffffffff /* Count, time period */

Definition at line 555 of file spr_defs.h.

#define SPR_TTMR (SPRGROUP_TT + 0)

Definition at line 127 of file spr_defs.h.

#define SPR_TTMR_CR 0xc0000000 /* Continuous run */

Definition at line 562 of file spr_defs.h.

#define SPR_TTMR_DI 0x00000000 /* Disabled */

Definition at line 559 of file spr_defs.h.

#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */

Definition at line 558 of file spr_defs.h.

#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */

Definition at line 557 of file spr_defs.h.

#define SPR_TTMR_M 0xc0000000 /* Tick mode */

Definition at line 563 of file spr_defs.h.

#define SPR_TTMR_RT 0x40000000 /* Restart tick */

Definition at line 560 of file spr_defs.h.

#define SPR_TTMR_SR 0x80000000 /* Single run */

Definition at line 561 of file spr_defs.h.

#define SPR_TTMR_TP 0x0fffffff /* Time period */

Definition at line 556 of file spr_defs.h.

#define SPR_UPR (SPRGROUP_SYS + 1)

Definition at line 46 of file spr_defs.h.

#define SPR_UPR_CUP 0xff000000 /* Context units present */

Definition at line 159 of file spr_defs.h.

#define SPR_UPR_DCP 0x00000002 /* Data cache present */

Definition at line 148 of file spr_defs.h.

#define SPR_UPR_DMP 0x00000008 /* Data MMU present */

Definition at line 150 of file spr_defs.h.

#define SPR_UPR_DUP 0x00000040 /* Debug unit present */

Definition at line 153 of file spr_defs.h.

#define SPR_UPR_ICP 0x00000004 /* Instruction cache present */

Definition at line 149 of file spr_defs.h.

#define SPR_UPR_IMP 0x00000010 /* Instruction MMU present */

Definition at line 151 of file spr_defs.h.

#define SPR_UPR_MP 0x00000020 /* MAC present */

Definition at line 152 of file spr_defs.h.

#define SPR_UPR_PCUP 0x00000080 /* Performance counters unit present */

Definition at line 154 of file spr_defs.h.

#define SPR_UPR_PICP 0x00000200 /* PIC present */

Definition at line 156 of file spr_defs.h.

#define SPR_UPR_PMP 0x00000100 /* Power management present */

Definition at line 155 of file spr_defs.h.

#define SPR_UPR_RES 0x00fe0000 /* Reserved */

Definition at line 158 of file spr_defs.h.

#define SPR_UPR_TTP 0x00000400 /* Tick timer present */

Definition at line 157 of file spr_defs.h.

#define SPR_UPR_UP 0x00000001 /* UPR present */

Definition at line 147 of file spr_defs.h.

#define SPR_VR (SPRGROUP_SYS + 0)

Definition at line 45 of file spr_defs.h.

#define SPR_VR_CFG 0x00ff0000 /* Processor configuration */

Definition at line 135 of file spr_defs.h.

#define SPR_VR_CFG_OFF 16

Definition at line 140 of file spr_defs.h.

#define SPR_VR_RES 0x0000ffc0 /* Reserved */

Definition at line 136 of file spr_defs.h.

#define SPR_VR_REV 0x0000003f /* Processor revision */

Definition at line 137 of file spr_defs.h.

#define SPR_VR_REV_OFF 0

Definition at line 141 of file spr_defs.h.

#define SPR_VR_VER 0xff000000 /* Processor version */

Definition at line 134 of file spr_defs.h.

#define SPR_VR_VER_OFF 24

Definition at line 139 of file spr_defs.h.

#define SPRGROUP_D (6 << MAX_SPRS_PER_GRP_BITS)

Definition at line 37 of file spr_defs.h.

#define SPRGROUP_DC (3 << MAX_SPRS_PER_GRP_BITS)

Definition at line 34 of file spr_defs.h.

#define SPRGROUP_DMMU (1 << MAX_SPRS_PER_GRP_BITS)

Definition at line 32 of file spr_defs.h.

#define SPRGROUP_FP (11 << MAX_SPRS_PER_GRP_BITS)

Definition at line 42 of file spr_defs.h.

#define SPRGROUP_IC (4 << MAX_SPRS_PER_GRP_BITS)

Definition at line 35 of file spr_defs.h.

#define SPRGROUP_IMMU (2 << MAX_SPRS_PER_GRP_BITS)

Definition at line 33 of file spr_defs.h.

#define SPRGROUP_MAC (5 << MAX_SPRS_PER_GRP_BITS)

Definition at line 36 of file spr_defs.h.

#define SPRGROUP_PC (7 << MAX_SPRS_PER_GRP_BITS)

Definition at line 38 of file spr_defs.h.

#define SPRGROUP_PIC (9 << MAX_SPRS_PER_GRP_BITS)

Definition at line 40 of file spr_defs.h.

#define SPRGROUP_PM (8 << MAX_SPRS_PER_GRP_BITS)

Definition at line 39 of file spr_defs.h.

#define SPRGROUP_SYS (0 << MAX_SPRS_PER_GRP_BITS)

Definition at line 31 of file spr_defs.h.

#define SPRGROUP_TT (10 << MAX_SPRS_PER_GRP_BITS)

Definition at line 41 of file spr_defs.h.

Macros

Macro Definition Documentation