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xd.c
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1 /* Driver for Realtek PCI-Express card reader
2  *
3  * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of the GNU General Public License as published by the
7  * Free Software Foundation; either version 2, or (at your option) any
8  * later version.
9  *
10  * This program is distributed in the hope that it will be useful, but
11  * WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13  * General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, see <http://www.gnu.org/licenses/>.
17  *
18  * Author:
19  * wwang ([email protected])
20  * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21  */
22 
23 #include <linux/blkdev.h>
24 #include <linux/kthread.h>
25 #include <linux/sched.h>
26 #include <linux/vmalloc.h>
27 
28 #include "rtsx.h"
29 #include "rtsx_transport.h"
30 #include "rtsx_scsi.h"
31 #include "rtsx_card.h"
32 #include "xd.h"
33 
34 static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no);
35 static int xd_init_page(struct rtsx_chip *chip, u32 phy_blk, u16 logoff, u8 start_page, u8 end_page);
36 
37 static inline void xd_set_err_code(struct rtsx_chip *chip, u8 err_code)
38 {
39  struct xd_info *xd_card = &(chip->xd_card);
40 
41  xd_card->err_code = err_code;
42 }
43 
44 static inline int xd_check_err_code(struct rtsx_chip *chip, u8 err_code)
45 {
46  struct xd_info *xd_card = &(chip->xd_card);
47 
48  return (xd_card->err_code == err_code);
49 }
50 
51 static int xd_set_init_para(struct rtsx_chip *chip)
52 {
53  struct xd_info *xd_card = &(chip->xd_card);
54  int retval;
55 
56  if (chip->asic_code)
57  xd_card->xd_clock = 47;
58  else
59  xd_card->xd_clock = CLK_50;
60 
61  retval = switch_clock(chip, xd_card->xd_clock);
62  if (retval != STATUS_SUCCESS)
63  TRACE_RET(chip, STATUS_FAIL);
64 
65  return STATUS_SUCCESS;
66 }
67 
68 static int xd_switch_clock(struct rtsx_chip *chip)
69 {
70  struct xd_info *xd_card = &(chip->xd_card);
71  int retval;
72 
73  retval = select_card(chip, XD_CARD);
74  if (retval != STATUS_SUCCESS)
75  TRACE_RET(chip, STATUS_FAIL);
76 
77  retval = switch_clock(chip, xd_card->xd_clock);
78  if (retval != STATUS_SUCCESS)
79  TRACE_RET(chip, STATUS_FAIL);
80 
81  return STATUS_SUCCESS;
82 }
83 
84 static int xd_read_id(struct rtsx_chip *chip, u8 id_cmd, u8 *id_buf, u8 buf_len)
85 {
86  int retval, i;
87  u8 *ptr;
88 
89  rtsx_init_cmd(chip);
90 
91  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, id_cmd);
92  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_READ_ID);
93  rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
94 
95  for (i = 0; i < 4; i++)
96  rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_ADDRESS1 + i), 0, 0);
97 
98  retval = rtsx_send_cmd(chip, XD_CARD, 20);
99  if (retval < 0)
100  TRACE_RET(chip, STATUS_FAIL);
101 
102  ptr = rtsx_get_cmd_data(chip) + 1;
103  if (id_buf && buf_len) {
104  if (buf_len > 4)
105  buf_len = 4;
106  memcpy(id_buf, ptr, buf_len);
107  }
108 
109  return STATUS_SUCCESS;
110 }
111 
112 static void xd_assign_phy_addr(struct rtsx_chip *chip, u32 addr, u8 mode)
113 {
114  struct xd_info *xd_card = &(chip->xd_card);
115 
116  switch (mode) {
117  case XD_RW_ADDR:
118  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, 0);
119  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 0xFF, (u8)addr);
120  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2, 0xFF, (u8)(addr >> 8));
121  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS3, 0xFF, (u8)(addr >> 16));
122  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF,
123  xd_card->addr_cycle | XD_CALC_ECC | XD_BA_NO_TRANSFORM);
124  break;
125 
126  case XD_ERASE_ADDR:
127  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, (u8)addr);
128  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 0xFF, (u8)(addr >> 8));
129  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2, 0xFF, (u8)(addr >> 16));
130  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF,
131  (xd_card->addr_cycle - 1) | XD_CALC_ECC | XD_BA_NO_TRANSFORM);
132  break;
133 
134  default:
135  break;
136  }
137 }
138 
139 static int xd_read_redundant(struct rtsx_chip *chip, u32 page_addr, u8 *buf, int buf_len)
140 {
141  int retval, i;
142 
143  rtsx_init_cmd(chip);
144 
145  xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
146 
147  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_READ_REDUNDANT);
148  rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
149 
150  for (i = 0; i < 6; i++)
151  rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_PAGE_STATUS + i), 0, 0);
152  for (i = 0; i < 4; i++)
153  rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_RESERVED0 + i), 0, 0);
154  rtsx_add_cmd(chip, READ_REG_CMD, XD_PARITY, 0, 0);
155 
156  retval = rtsx_send_cmd(chip, XD_CARD, 500);
157  if (retval < 0)
158  TRACE_RET(chip, STATUS_FAIL);
159 
160  if (buf && buf_len) {
161  u8 *ptr = rtsx_get_cmd_data(chip) + 1;
162 
163  if (buf_len > 11)
164  buf_len = 11;
165  memcpy(buf, ptr, buf_len);
166  }
167 
168  return STATUS_SUCCESS;
169 }
170 
171 static int xd_read_data_from_ppb(struct rtsx_chip *chip, int offset, u8 *buf, int buf_len)
172 {
173  int retval, i;
174 
175  if (!buf || (buf_len < 0))
176  TRACE_RET(chip, STATUS_FAIL);
177 
178  rtsx_init_cmd(chip);
179 
180  for (i = 0; i < buf_len; i++)
181  rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + offset + i, 0, 0);
182 
183  retval = rtsx_send_cmd(chip, 0, 250);
184  if (retval < 0) {
185  rtsx_clear_xd_error(chip);
186  TRACE_RET(chip, STATUS_FAIL);
187  }
188 
189  memcpy(buf, rtsx_get_cmd_data(chip), buf_len);
190 
191  return STATUS_SUCCESS;
192 }
193 
194 static int xd_read_cis(struct rtsx_chip *chip, u32 page_addr, u8 *buf, int buf_len)
195 {
196  int retval;
197  u8 reg;
198 
199  if (!buf || (buf_len < 10))
200  TRACE_RET(chip, STATUS_FAIL);
201 
202  rtsx_init_cmd(chip);
203 
204  xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
205 
206  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
207  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
208  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS);
209 
210  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_READ_PAGES);
211  rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
212 
213  retval = rtsx_send_cmd(chip, XD_CARD, 250);
214  if (retval == -ETIMEDOUT) {
215  rtsx_clear_xd_error(chip);
216  TRACE_RET(chip, STATUS_FAIL);
217  }
218 
219  RTSX_READ_REG(chip, XD_PAGE_STATUS, &reg);
220  if (reg != XD_GPG) {
221  rtsx_clear_xd_error(chip);
222  TRACE_RET(chip, STATUS_FAIL);
223  }
224 
225  RTSX_READ_REG(chip, XD_CTL, &reg);
226  if (!(reg & XD_ECC1_ERROR) || !(reg & XD_ECC1_UNCORRECTABLE)) {
227  retval = xd_read_data_from_ppb(chip, 0, buf, buf_len);
228  if (retval != STATUS_SUCCESS)
229  TRACE_RET(chip, STATUS_FAIL);
230  if (reg & XD_ECC1_ERROR) {
231  u8 ecc_bit, ecc_byte;
232 
233  RTSX_READ_REG(chip, XD_ECC_BIT1, &ecc_bit);
234  RTSX_READ_REG(chip, XD_ECC_BYTE1, &ecc_byte);
235 
236  RTSX_DEBUGP("ECC_BIT1 = 0x%x, ECC_BYTE1 = 0x%x\n", ecc_bit, ecc_byte);
237  if (ecc_byte < buf_len) {
238  RTSX_DEBUGP("Before correct: 0x%x\n", buf[ecc_byte]);
239  buf[ecc_byte] ^= (1 << ecc_bit);
240  RTSX_DEBUGP("After correct: 0x%x\n", buf[ecc_byte]);
241  }
242  }
243  } else if (!(reg & XD_ECC2_ERROR) || !(reg & XD_ECC2_UNCORRECTABLE)) {
244  rtsx_clear_xd_error(chip);
245 
246  retval = xd_read_data_from_ppb(chip, 256, buf, buf_len);
247  if (retval != STATUS_SUCCESS)
248  TRACE_RET(chip, STATUS_FAIL);
249  if (reg & XD_ECC2_ERROR) {
250  u8 ecc_bit, ecc_byte;
251 
252  RTSX_READ_REG(chip, XD_ECC_BIT2, &ecc_bit);
253  RTSX_READ_REG(chip, XD_ECC_BYTE2, &ecc_byte);
254 
255  RTSX_DEBUGP("ECC_BIT2 = 0x%x, ECC_BYTE2 = 0x%x\n", ecc_bit, ecc_byte);
256  if (ecc_byte < buf_len) {
257  RTSX_DEBUGP("Before correct: 0x%x\n", buf[ecc_byte]);
258  buf[ecc_byte] ^= (1 << ecc_bit);
259  RTSX_DEBUGP("After correct: 0x%x\n", buf[ecc_byte]);
260  }
261  }
262  } else {
263  rtsx_clear_xd_error(chip);
264  TRACE_RET(chip, STATUS_FAIL);
265  }
266 
267  return STATUS_SUCCESS;
268 }
269 
270 static void xd_fill_pull_ctl_disable(struct rtsx_chip *chip)
271 {
272  if (CHECK_PID(chip, 0x5209)) {
273  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);
274  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
275  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0xD5);
276  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
277  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
278  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0x15);
279  } else if (CHECK_PID(chip, 0x5208)) {
280  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
281  XD_D3_PD | XD_D2_PD | XD_D1_PD | XD_D0_PD);
282  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
283  XD_D7_PD | XD_D6_PD | XD_D5_PD | XD_D4_PD);
284  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
285  XD_WP_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
286  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
287  XD_RDY_PD | XD_WE_PD | XD_RE_PD | XD_ALE_PD);
288  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
289  MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
290  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, MS_D5_PD | MS_D4_PD);
291  } else if (CHECK_PID(chip, 0x5288)) {
292  if (CHECK_BARO_PKG(chip, QFN)) {
293  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);
294  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
295  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x4B);
296  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x69);
297  }
298  }
299 }
300 
301 static void xd_fill_pull_ctl_stage1_barossa(struct rtsx_chip *chip)
302 {
303  if (CHECK_BARO_PKG(chip, QFN)) {
304  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);
305  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
306  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x4B);
307  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
308  }
309 }
310 
311 static void xd_fill_pull_ctl_enable(struct rtsx_chip *chip)
312 {
313  if (CHECK_PID(chip, 0x5209)) {
314  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0xAA);
315  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
316  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0xD5);
317  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
318  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
319  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0x15);
320  } else if (CHECK_PID(chip, 0x5208)) {
321  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
322  XD_D3_PD | XD_D2_PD | XD_D1_PD | XD_D0_PD);
323  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
324  XD_D7_PD | XD_D6_PD | XD_D5_PD | XD_D4_PD);
325  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
326  XD_WP_PD | XD_CE_PU | XD_CLE_PD | XD_CD_PU);
327  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
328  XD_RDY_PU | XD_WE_PU | XD_RE_PU | XD_ALE_PD);
329  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
330  MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
331  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, MS_D5_PD | MS_D4_PD);
332  } else if (CHECK_PID(chip, 0x5288)) {
333  if (CHECK_BARO_PKG(chip, QFN)) {
334  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);
335  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
336  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x53);
337  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0xA9);
338  }
339  }
340 }
341 
342 static int xd_pull_ctl_disable(struct rtsx_chip *chip)
343 {
344  if (CHECK_PID(chip, 0x5209)) {
345  RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x55);
346  RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, 0x55);
347  RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, 0xD5);
348  RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, 0x55);
349  RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF, 0x55);
350  RTSX_WRITE_REG(chip, CARD_PULL_CTL6, 0xFF, 0x15);
351  } else if (CHECK_PID(chip, 0x5208)) {
352  RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF,
353  XD_D3_PD | XD_D2_PD | XD_D1_PD | XD_D0_PD);
354  RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF,
355  XD_D7_PD | XD_D6_PD | XD_D5_PD | XD_D4_PD);
356  RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF,
357  XD_WP_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
358  RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF,
359  XD_RDY_PD | XD_WE_PD | XD_RE_PD | XD_ALE_PD);
360  RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF,
361  MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
362  RTSX_WRITE_REG(chip, CARD_PULL_CTL6, 0xFF, MS_D5_PD | MS_D4_PD);
363  } else if (CHECK_PID(chip, 0x5288)) {
364  if (CHECK_BARO_PKG(chip, QFN)) {
365  RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x55);
366  RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, 0x55);
367  RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, 0x4B);
368  RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, 0x69);
369  }
370  }
371 
372  return STATUS_SUCCESS;
373 }
374 
375 static void xd_clear_dma_buffer(struct rtsx_chip *chip)
376 {
377  if (CHECK_PID(chip, 0x5209)) {
378  int retval;
379  u8 *buf;
380 
381  RTSX_DEBUGP("xD ECC error, dummy write!\n");
382 
383  buf = kmalloc(512, GFP_KERNEL);
384  if (!buf)
385  return;
386 
387  rtsx_init_cmd(chip);
388 
389  trans_dma_enable(DMA_TO_DEVICE, chip, 512, DMA_512);
390 
391  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
392  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, SD_CLK_EN);
393  if (chip->asic_code) {
394  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0xAA);
395  } else {
396  rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL,
397  FPGA_SD_PULL_CTL_BIT, 0);
398  }
399 
400  rtsx_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0x00);
401  rtsx_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, 0x02);
402  rtsx_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1);
403  rtsx_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0);
404  rtsx_add_cmd(chip, WRITE_REG_CMD, SD_CFG1, 0x03, SD_BUS_WIDTH_4);
405 
406  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
407 
408  rtsx_add_cmd(chip, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
409  SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
410  rtsx_add_cmd(chip, CHECK_REG_CMD, SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
411 
412  rtsx_send_cmd_no_wait(chip);
413 
414  retval = rtsx_transfer_data(chip, SD_CARD, buf, 512, 0, DMA_TO_DEVICE, 100);
415  if (retval < 0) {
416  u8 val;
417 
418  rtsx_read_register(chip, SD_STAT1, &val);
419  RTSX_DEBUGP("SD_STAT1: 0x%x\n", val);
420 
421  rtsx_read_register(chip, SD_STAT2, &val);
422  RTSX_DEBUGP("SD_STAT2: 0x%x\n", val);
423 
424  rtsx_read_register(chip, SD_BUS_STAT, &val);
425  RTSX_DEBUGP("SD_BUS_STAT: 0x%x\n", val);
426 
427  rtsx_write_register(chip, CARD_STOP, SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
428  }
429 
430  kfree(buf);
431 
432  if (chip->asic_code) {
433  rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF, 0x55);
434  } else {
435  rtsx_write_register(chip, FPGA_PULL_CTL,
436  FPGA_SD_PULL_CTL_BIT, FPGA_SD_PULL_CTL_BIT);
437  }
438  rtsx_write_register(chip, CARD_SELECT, 0x07, XD_MOD_SEL);
439  rtsx_write_register(chip, CARD_CLK_EN, SD_CLK_EN, 0);
440  }
441 }
442 
443 static int reset_xd(struct rtsx_chip *chip)
444 {
445  struct xd_info *xd_card = &(chip->xd_card);
446  int retval, i, j;
447  u8 *ptr, id_buf[4], redunt[11];
448 
449  retval = select_card(chip, XD_CARD);
450  if (retval != STATUS_SUCCESS)
451  TRACE_RET(chip, STATUS_FAIL);
452 
453  rtsx_init_cmd(chip);
454 
455  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, 0xFF, XD_PGSTS_NOT_FF);
456  if (chip->asic_code) {
457  if (!CHECK_PID(chip, 0x5288))
458  xd_fill_pull_ctl_disable(chip);
459  else
460  xd_fill_pull_ctl_stage1_barossa(chip);
461  } else {
462  rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
463  (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN3) | 0x20);
464  }
465 
466  if (!chip->ft2_fast_mode)
467  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_INIT, XD_NO_AUTO_PWR_OFF, 0);
468 
469  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, 0);
470 
471  retval = rtsx_send_cmd(chip, XD_CARD, 100);
472  if (retval < 0)
473  TRACE_RET(chip, STATUS_FAIL);
474 
475  if (!chip->ft2_fast_mode) {
476  retval = card_power_off(chip, XD_CARD);
477  if (retval != STATUS_SUCCESS)
478  TRACE_RET(chip, STATUS_FAIL);
479 
480  wait_timeout(250);
481 
482  if (CHECK_PID(chip, 0x5209))
483  RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0xAA);
484 
485  rtsx_init_cmd(chip);
486 
487  if (chip->asic_code) {
488  xd_fill_pull_ctl_enable(chip);
489  } else {
490  rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
491  (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN2) | 0x20);
492  }
493 
494  retval = rtsx_send_cmd(chip, XD_CARD, 100);
495  if (retval < 0)
496  TRACE_RET(chip, STATUS_FAIL);
497 
498  retval = card_power_on(chip, XD_CARD);
499  if (retval != STATUS_SUCCESS)
500  TRACE_RET(chip, STATUS_FAIL);
501 
502 #ifdef SUPPORT_OCP
503  wait_timeout(50);
504  if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
505  RTSX_DEBUGP("Over current, OCPSTAT is 0x%x\n", chip->ocp_stat);
506  TRACE_RET(chip, STATUS_FAIL);
507  }
508 #endif
509  }
510 
511  rtsx_init_cmd(chip);
512 
513  if (chip->ft2_fast_mode) {
514  if (chip->asic_code) {
515  xd_fill_pull_ctl_enable(chip);
516  } else {
517  rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
518  (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN2) | 0x20);
519  }
520  }
521 
522  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, XD_OUTPUT_EN);
523  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CTL, XD_CE_DISEN, XD_CE_DISEN);
524 
525  retval = rtsx_send_cmd(chip, XD_CARD, 100);
526  if (retval < 0)
527  TRACE_RET(chip, STATUS_FAIL);
528 
529  if (!chip->ft2_fast_mode)
530  wait_timeout(200);
531 
532  retval = xd_set_init_para(chip);
533  if (retval != STATUS_SUCCESS)
534  TRACE_RET(chip, STATUS_FAIL);
535 
536  /* Read ID to check if the timing setting is right */
537  for (i = 0; i < 4; i++) {
538  rtsx_init_cmd(chip);
539 
540  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DTCTL, 0xFF,
541  XD_TIME_SETUP_STEP * 3 + XD_TIME_RW_STEP * (2 + i) + XD_TIME_RWN_STEP * i);
542  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CATCTL, 0xFF,
543  XD_TIME_SETUP_STEP * 3 + XD_TIME_RW_STEP * (4 + i) + XD_TIME_RWN_STEP * (3 + i));
544 
545  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_RESET);
546  rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
547 
548  rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
549  rtsx_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0);
550 
551  retval = rtsx_send_cmd(chip, XD_CARD, 100);
552  if (retval < 0)
553  TRACE_RET(chip, STATUS_FAIL);
554 
555  ptr = rtsx_get_cmd_data(chip) + 1;
556 
557  RTSX_DEBUGP("XD_DAT: 0x%x, XD_CTL: 0x%x\n", ptr[0], ptr[1]);
558 
559  if (((ptr[0] & READY_FLAG) != READY_STATE) || !(ptr[1] & XD_RDY))
560  continue;
561 
562  retval = xd_read_id(chip, READ_ID, id_buf, 4);
563  if (retval != STATUS_SUCCESS)
564  TRACE_RET(chip, STATUS_FAIL);
565 
566  RTSX_DEBUGP("READ_ID: 0x%x 0x%x 0x%x 0x%x\n",
567  id_buf[0], id_buf[1], id_buf[2], id_buf[3]);
568 
569  xd_card->device_code = id_buf[1];
570 
571  /* Check if the xD card is supported */
572  switch (xd_card->device_code) {
573  case XD_4M_X8_512_1:
574  case XD_4M_X8_512_2:
575  xd_card->block_shift = 4;
576  xd_card->page_off = 0x0F;
577  xd_card->addr_cycle = 3;
578  xd_card->zone_cnt = 1;
579  xd_card->capacity = 8000;
580  XD_SET_4MB(xd_card);
581  break;
582  case XD_8M_X8_512:
583  xd_card->block_shift = 4;
584  xd_card->page_off = 0x0F;
585  xd_card->addr_cycle = 3;
586  xd_card->zone_cnt = 1;
587  xd_card->capacity = 16000;
588  break;
589  case XD_16M_X8_512:
590  XD_PAGE_512(xd_card);
591  xd_card->addr_cycle = 3;
592  xd_card->zone_cnt = 1;
593  xd_card->capacity = 32000;
594  break;
595  case XD_32M_X8_512:
596  XD_PAGE_512(xd_card);
597  xd_card->addr_cycle = 3;
598  xd_card->zone_cnt = 2;
599  xd_card->capacity = 64000;
600  break;
601  case XD_64M_X8_512:
602  XD_PAGE_512(xd_card);
603  xd_card->addr_cycle = 4;
604  xd_card->zone_cnt = 4;
605  xd_card->capacity = 128000;
606  break;
607  case XD_128M_X8_512:
608  XD_PAGE_512(xd_card);
609  xd_card->addr_cycle = 4;
610  xd_card->zone_cnt = 8;
611  xd_card->capacity = 256000;
612  break;
613  case XD_256M_X8_512:
614  XD_PAGE_512(xd_card);
615  xd_card->addr_cycle = 4;
616  xd_card->zone_cnt = 16;
617  xd_card->capacity = 512000;
618  break;
619  case XD_512M_X8:
620  XD_PAGE_512(xd_card);
621  xd_card->addr_cycle = 4;
622  xd_card->zone_cnt = 32;
623  xd_card->capacity = 1024000;
624  break;
625  case xD_1G_X8_512:
626  XD_PAGE_512(xd_card);
627  xd_card->addr_cycle = 4;
628  xd_card->zone_cnt = 64;
629  xd_card->capacity = 2048000;
630  break;
631  case xD_2G_X8_512:
632  XD_PAGE_512(xd_card);
633  xd_card->addr_cycle = 4;
634  xd_card->zone_cnt = 128;
635  xd_card->capacity = 4096000;
636  break;
637  default:
638  continue;
639  }
640 
641  /* Confirm timing setting */
642  for (j = 0; j < 10; j++) {
643  retval = xd_read_id(chip, READ_ID, id_buf, 4);
644  if (retval != STATUS_SUCCESS)
645  TRACE_RET(chip, STATUS_FAIL);
646 
647  if (id_buf[1] != xd_card->device_code)
648  break;
649  }
650 
651  if (j == 10)
652  break;
653  }
654 
655  if (i == 4) {
656  xd_card->block_shift = 0;
657  xd_card->page_off = 0;
658  xd_card->addr_cycle = 0;
659  xd_card->capacity = 0;
660 
661  TRACE_RET(chip, STATUS_FAIL);
662  }
663 
664  retval = xd_read_id(chip, READ_xD_ID, id_buf, 4);
665  if (retval != STATUS_SUCCESS)
666  TRACE_RET(chip, STATUS_FAIL);
667  RTSX_DEBUGP("READ_xD_ID: 0x%x 0x%x 0x%x 0x%x\n",
668  id_buf[0], id_buf[1], id_buf[2], id_buf[3]);
669  if (id_buf[2] != XD_ID_CODE)
670  TRACE_RET(chip, STATUS_FAIL);
671 
672  /* Search CIS block */
673  for (i = 0; i < 24; i++) {
674  u32 page_addr;
675 
676  if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS)
677  TRACE_RET(chip, STATUS_FAIL);
678 
679  page_addr = (u32)i << xd_card->block_shift;
680 
681  for (j = 0; j < 3; j++) {
682  retval = xd_read_redundant(chip, page_addr, redunt, 11);
683  if (retval == STATUS_SUCCESS)
684  break;
685  }
686  if (j == 3)
687  continue;
688 
689  if (redunt[BLOCK_STATUS] != XD_GBLK)
690  continue;
691 
692  j = 0;
693  if (redunt[PAGE_STATUS] != XD_GPG) {
694  for (j = 1; j <= 8; j++) {
695  retval = xd_read_redundant(chip, page_addr + j, redunt, 11);
696  if (retval == STATUS_SUCCESS) {
697  if (redunt[PAGE_STATUS] == XD_GPG)
698  break;
699  }
700  }
701 
702  if (j == 9)
703  break;
704  }
705 
706  /* Check CIS data */
707  if ((redunt[BLOCK_STATUS] == XD_GBLK) && (redunt[PARITY] & XD_BA1_ALL0)) {
708  u8 buf[10];
709 
710  page_addr += j;
711 
712  retval = xd_read_cis(chip, page_addr, buf, 10);
713  if (retval != STATUS_SUCCESS)
714  TRACE_RET(chip, STATUS_FAIL);
715 
716  if ((buf[0] == 0x01) && (buf[1] == 0x03) && (buf[2] == 0xD9)
717  && (buf[3] == 0x01) && (buf[4] == 0xFF)
718  && (buf[5] == 0x18) && (buf[6] == 0x02)
719  && (buf[7] == 0xDF) && (buf[8] == 0x01)
720  && (buf[9] == 0x20)) {
721  xd_card->cis_block = (u16)i;
722  }
723  }
724 
725  break;
726  }
727 
728  RTSX_DEBUGP("CIS block: 0x%x\n", xd_card->cis_block);
729  if (xd_card->cis_block == 0xFFFF)
730  TRACE_RET(chip, STATUS_FAIL);
731 
732  chip->capacity[chip->card2lun[XD_CARD]] = xd_card->capacity;
733 
734  return STATUS_SUCCESS;
735 }
736 
737 static int xd_check_data_blank(u8 *redunt)
738 {
739  int i;
740 
741  for (i = 0; i < 6; i++) {
742  if (redunt[PAGE_STATUS + i] != 0xFF)
743  return 0;
744  }
745 
746  if ((redunt[PARITY] & (XD_ECC1_ALL1 | XD_ECC2_ALL1)) != (XD_ECC1_ALL1 | XD_ECC2_ALL1))
747  return 0;
748 
749 
750  for (i = 0; i < 4; i++) {
751  if (redunt[RESERVED0 + i] != 0xFF)
752  return 0;
753  }
754 
755  return 1;
756 }
757 
758 static u16 xd_load_log_block_addr(u8 *redunt)
759 {
760  u16 addr = 0xFFFF;
761 
762  if (redunt[PARITY] & XD_BA1_BA2_EQL)
763  addr = ((u16)redunt[BLOCK_ADDR1_H] << 8) | redunt[BLOCK_ADDR1_L];
764  else if (redunt[PARITY] & XD_BA1_VALID)
765  addr = ((u16)redunt[BLOCK_ADDR1_H] << 8) | redunt[BLOCK_ADDR1_L];
766  else if (redunt[PARITY] & XD_BA2_VALID)
767  addr = ((u16)redunt[BLOCK_ADDR2_H] << 8) | redunt[BLOCK_ADDR2_L];
768 
769  return addr;
770 }
771 
772 static int xd_init_l2p_tbl(struct rtsx_chip *chip)
773 {
774  struct xd_info *xd_card = &(chip->xd_card);
775  int size, i;
776 
777  RTSX_DEBUGP("xd_init_l2p_tbl: zone_cnt = %d\n", xd_card->zone_cnt);
778 
779  if (xd_card->zone_cnt < 1)
780  TRACE_RET(chip, STATUS_FAIL);
781 
782  size = xd_card->zone_cnt * sizeof(struct zone_entry);
783  RTSX_DEBUGP("Buffer size for l2p table is %d\n", size);
784 
785  xd_card->zone = (struct zone_entry *)vmalloc(size);
786  if (!xd_card->zone)
787  TRACE_RET(chip, STATUS_ERROR);
788 
789  for (i = 0; i < xd_card->zone_cnt; i++) {
790  xd_card->zone[i].build_flag = 0;
791  xd_card->zone[i].l2p_table = NULL;
792  xd_card->zone[i].free_table = NULL;
793  xd_card->zone[i].get_index = 0;
794  xd_card->zone[i].set_index = 0;
795  xd_card->zone[i].unused_blk_cnt = 0;
796  }
797 
798  return STATUS_SUCCESS;
799 }
800 
801 static inline void free_zone(struct zone_entry *zone)
802 {
803  RTSX_DEBUGP("free_zone\n");
804 
805  if (!zone)
806  return;
807 
808  zone->build_flag = 0;
809  zone->set_index = 0;
810  zone->get_index = 0;
811  zone->unused_blk_cnt = 0;
812  if (zone->l2p_table) {
813  vfree(zone->l2p_table);
814  zone->l2p_table = NULL;
815  }
816  if (zone->free_table) {
817  vfree(zone->free_table);
818  zone->free_table = NULL;
819  }
820 }
821 
822 static void xd_set_unused_block(struct rtsx_chip *chip, u32 phy_blk)
823 {
824  struct xd_info *xd_card = &(chip->xd_card);
825  struct zone_entry *zone;
826  int zone_no;
827 
828  zone_no = (int)phy_blk >> 10;
829  if (zone_no >= xd_card->zone_cnt) {
830  RTSX_DEBUGP("Set unused block to invalid zone (zone_no = %d, zone_cnt = %d)\n",
831  zone_no, xd_card->zone_cnt);
832  return;
833  }
834  zone = &(xd_card->zone[zone_no]);
835 
836  if (zone->free_table == NULL) {
837  if (xd_build_l2p_tbl(chip, zone_no) != STATUS_SUCCESS)
838  return;
839  }
840 
841  if ((zone->set_index >= XD_FREE_TABLE_CNT)
842  || (zone->set_index < 0)) {
843  free_zone(zone);
844  RTSX_DEBUGP("Set unused block fail, invalid set_index\n");
845  return;
846  }
847 
848  RTSX_DEBUGP("Set unused block to index %d\n", zone->set_index);
849 
850  zone->free_table[zone->set_index++] = (u16) (phy_blk & 0x3ff);
851  if (zone->set_index >= XD_FREE_TABLE_CNT)
852  zone->set_index = 0;
853  zone->unused_blk_cnt++;
854 }
855 
856 static u32 xd_get_unused_block(struct rtsx_chip *chip, int zone_no)
857 {
858  struct xd_info *xd_card = &(chip->xd_card);
859  struct zone_entry *zone;
860  u32 phy_blk;
861 
862  if (zone_no >= xd_card->zone_cnt) {
863  RTSX_DEBUGP("Get unused block from invalid zone (zone_no = %d, zone_cnt = %d)\n",
864  zone_no, xd_card->zone_cnt);
865  return BLK_NOT_FOUND;
866  }
867  zone = &(xd_card->zone[zone_no]);
868 
869  if ((zone->unused_blk_cnt == 0) || (zone->set_index == zone->get_index)) {
870  free_zone(zone);
871  RTSX_DEBUGP("Get unused block fail, no unused block available\n");
872  return BLK_NOT_FOUND;
873  }
874  if ((zone->get_index >= XD_FREE_TABLE_CNT) || (zone->get_index < 0)) {
875  free_zone(zone);
876  RTSX_DEBUGP("Get unused block fail, invalid get_index\n");
877  return BLK_NOT_FOUND;
878  }
879 
880  RTSX_DEBUGP("Get unused block from index %d\n", zone->get_index);
881 
882  phy_blk = zone->free_table[zone->get_index];
883  zone->free_table[zone->get_index++] = 0xFFFF;
884  if (zone->get_index >= XD_FREE_TABLE_CNT)
885  zone->get_index = 0;
886  zone->unused_blk_cnt--;
887 
888  phy_blk += ((u32)(zone_no) << 10);
889  return phy_blk;
890 }
891 
892 static void xd_set_l2p_tbl(struct rtsx_chip *chip, int zone_no, u16 log_off, u16 phy_off)
893 {
894  struct xd_info *xd_card = &(chip->xd_card);
895  struct zone_entry *zone;
896 
897  zone = &(xd_card->zone[zone_no]);
898  zone->l2p_table[log_off] = phy_off;
899 }
900 
901 static u32 xd_get_l2p_tbl(struct rtsx_chip *chip, int zone_no, u16 log_off)
902 {
903  struct xd_info *xd_card = &(chip->xd_card);
904  struct zone_entry *zone;
905  int retval;
906 
907  zone = &(xd_card->zone[zone_no]);
908  if (zone->l2p_table[log_off] == 0xFFFF) {
909  u32 phy_blk = 0;
910  int i;
911 
912 #ifdef XD_DELAY_WRITE
913  retval = xd_delay_write(chip);
914  if (retval != STATUS_SUCCESS) {
915  RTSX_DEBUGP("In xd_get_l2p_tbl, delay write fail!\n");
916  return BLK_NOT_FOUND;
917  }
918 #endif
919 
920  if (zone->unused_blk_cnt <= 0) {
921  RTSX_DEBUGP("No unused block!\n");
922  return BLK_NOT_FOUND;
923  }
924 
925  for (i = 0; i < zone->unused_blk_cnt; i++) {
926  phy_blk = xd_get_unused_block(chip, zone_no);
927  if (phy_blk == BLK_NOT_FOUND) {
928  RTSX_DEBUGP("No unused block available!\n");
929  return BLK_NOT_FOUND;
930  }
931 
932  retval = xd_init_page(chip, phy_blk, log_off, 0, xd_card->page_off + 1);
933  if (retval == STATUS_SUCCESS)
934  break;
935  }
936  if (i >= zone->unused_blk_cnt) {
937  RTSX_DEBUGP("No good unused block available!\n");
938  return BLK_NOT_FOUND;
939  }
940 
941  xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(phy_blk & 0x3FF));
942  return phy_blk;
943  }
944 
945  return (u32)zone->l2p_table[log_off] + ((u32)(zone_no) << 10);
946 }
947 
948 int reset_xd_card(struct rtsx_chip *chip)
949 {
950  struct xd_info *xd_card = &(chip->xd_card);
951  int retval;
952 
953  memset(xd_card, 0, sizeof(struct xd_info));
954 
955  xd_card->block_shift = 0;
956  xd_card->page_off = 0;
957  xd_card->addr_cycle = 0;
958  xd_card->capacity = 0;
959  xd_card->zone_cnt = 0;
960  xd_card->cis_block = 0xFFFF;
961  xd_card->delay_write.delay_write_flag = 0;
962 
963  retval = enable_card_clock(chip, XD_CARD);
964  if (retval != STATUS_SUCCESS)
965  TRACE_RET(chip, STATUS_FAIL);
966 
967  retval = reset_xd(chip);
968  if (retval != STATUS_SUCCESS)
969  TRACE_RET(chip, STATUS_FAIL);
970 
971  retval = xd_init_l2p_tbl(chip);
972  if (retval != STATUS_SUCCESS)
973  TRACE_RET(chip, STATUS_FAIL);
974 
975  return STATUS_SUCCESS;
976 }
977 
978 static int xd_mark_bad_block(struct rtsx_chip *chip, u32 phy_blk)
979 {
980  struct xd_info *xd_card = &(chip->xd_card);
981  int retval;
982  u32 page_addr;
983  u8 reg = 0;
984 
985  RTSX_DEBUGP("mark block 0x%x as bad block\n", phy_blk);
986 
987  if (phy_blk == BLK_NOT_FOUND)
988  TRACE_RET(chip, STATUS_FAIL);
989 
990  rtsx_init_cmd(chip);
991 
992  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG);
993  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, XD_LATER_BBLK);
994  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 0xFF, 0xFF);
995  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, 0xFF);
996  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_H, 0xFF, 0xFF);
997  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_L, 0xFF, 0xFF);
998  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED0, 0xFF, 0xFF);
999  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED1, 0xFF, 0xFF);
1000  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED2, 0xFF, 0xFF);
1001  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED3, 0xFF, 0xFF);
1002 
1003  page_addr = phy_blk << xd_card->block_shift;
1004 
1005  xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1006 
1007  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, xd_card->page_off + 1);
1008 
1009  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_WRITE_REDUNDANT);
1010  rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
1011 
1012  retval = rtsx_send_cmd(chip, XD_CARD, 500);
1013  if (retval < 0) {
1014  rtsx_clear_xd_error(chip);
1015  rtsx_read_register(chip, XD_DAT, &reg);
1016  if (reg & PROGRAM_ERROR)
1017  xd_set_err_code(chip, XD_PRG_ERROR);
1018  else
1019  xd_set_err_code(chip, XD_TO_ERROR);
1020  TRACE_RET(chip, STATUS_FAIL);
1021  }
1022 
1023  return STATUS_SUCCESS;
1024 }
1025 
1026 static int xd_init_page(struct rtsx_chip *chip, u32 phy_blk, u16 logoff, u8 start_page, u8 end_page)
1027 {
1028  struct xd_info *xd_card = &(chip->xd_card);
1029  int retval;
1030  u32 page_addr;
1031  u8 reg = 0;
1032 
1033  RTSX_DEBUGP("Init block 0x%x\n", phy_blk);
1034 
1035  if (start_page > end_page)
1036  TRACE_RET(chip, STATUS_FAIL);
1037  if (phy_blk == BLK_NOT_FOUND)
1038  TRACE_RET(chip, STATUS_FAIL);
1039 
1040  rtsx_init_cmd(chip);
1041 
1042  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, 0xFF);
1043  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, 0xFF);
1044  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 0xFF, (u8)(logoff >> 8));
1045  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, (u8)logoff);
1046 
1047  page_addr = (phy_blk << xd_card->block_shift) + start_page;
1048 
1049  xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1050 
1051  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_BA_TRANSFORM, XD_BA_TRANSFORM);
1052 
1053  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, (end_page - start_page));
1054 
1055  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_WRITE_REDUNDANT);
1056  rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
1057 
1058  retval = rtsx_send_cmd(chip, XD_CARD, 500);
1059  if (retval < 0) {
1060  rtsx_clear_xd_error(chip);
1061  rtsx_read_register(chip, XD_DAT, &reg);
1062  if (reg & PROGRAM_ERROR) {
1063  xd_mark_bad_block(chip, phy_blk);
1064  xd_set_err_code(chip, XD_PRG_ERROR);
1065  } else {
1066  xd_set_err_code(chip, XD_TO_ERROR);
1067  }
1068  TRACE_RET(chip, STATUS_FAIL);
1069  }
1070 
1071  return STATUS_SUCCESS;
1072 }
1073 
1074 static int xd_copy_page(struct rtsx_chip *chip, u32 old_blk, u32 new_blk, u8 start_page, u8 end_page)
1075 {
1076  struct xd_info *xd_card = &(chip->xd_card);
1077  u32 old_page, new_page;
1078  u8 i, reg = 0;
1079  int retval;
1080 
1081  RTSX_DEBUGP("Copy page from block 0x%x to block 0x%x\n", old_blk, new_blk);
1082 
1083  if (start_page > end_page)
1084  TRACE_RET(chip, STATUS_FAIL);
1085 
1086  if ((old_blk == BLK_NOT_FOUND) || (new_blk == BLK_NOT_FOUND))
1087  TRACE_RET(chip, STATUS_FAIL);
1088 
1089  old_page = (old_blk << xd_card->block_shift) + start_page;
1090  new_page = (new_blk << xd_card->block_shift) + start_page;
1091 
1092  XD_CLR_BAD_NEWBLK(xd_card);
1093 
1094  RTSX_WRITE_REG(chip, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
1095 
1096  for (i = start_page; i < end_page; i++) {
1097  if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1098  rtsx_clear_xd_error(chip);
1099  xd_set_err_code(chip, XD_NO_CARD);
1100  TRACE_RET(chip, STATUS_FAIL);
1101  }
1102 
1103  rtsx_init_cmd(chip);
1104 
1105  xd_assign_phy_addr(chip, old_page, XD_RW_ADDR);
1106 
1107  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
1108  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS, 0);
1109  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_READ_PAGES);
1110  rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
1111 
1112  retval = rtsx_send_cmd(chip, XD_CARD, 500);
1113  if (retval < 0) {
1114  rtsx_clear_xd_error(chip);
1115  reg = 0;
1116  rtsx_read_register(chip, XD_CTL, &reg);
1117  if (reg & (XD_ECC1_ERROR | XD_ECC2_ERROR)) {
1118  wait_timeout(100);
1119 
1120  if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1121  xd_set_err_code(chip, XD_NO_CARD);
1122  TRACE_RET(chip, STATUS_FAIL);
1123  }
1124 
1125  if (((reg & (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) ==
1126  (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE))
1127  || ((reg & (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE)) ==
1128  (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))) {
1129  rtsx_write_register(chip, XD_PAGE_STATUS, 0xFF, XD_BPG);
1130  rtsx_write_register(chip, XD_BLOCK_STATUS, 0xFF, XD_GBLK);
1131  XD_SET_BAD_OLDBLK(xd_card);
1132  RTSX_DEBUGP("old block 0x%x ecc error\n", old_blk);
1133  }
1134  } else {
1135  xd_set_err_code(chip, XD_TO_ERROR);
1136  TRACE_RET(chip, STATUS_FAIL);
1137  }
1138  }
1139 
1140  if (XD_CHK_BAD_OLDBLK(xd_card))
1141  rtsx_clear_xd_error(chip);
1142 
1143  rtsx_init_cmd(chip);
1144 
1145  xd_assign_phy_addr(chip, new_page, XD_RW_ADDR);
1146  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
1147  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1148  XD_TRANSFER_START | XD_WRITE_PAGES);
1149  rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
1150 
1151  retval = rtsx_send_cmd(chip, XD_CARD, 300);
1152  if (retval < 0) {
1153  rtsx_clear_xd_error(chip);
1154  reg = 0;
1155  rtsx_read_register(chip, XD_DAT, &reg);
1156  if (reg & PROGRAM_ERROR) {
1157  xd_mark_bad_block(chip, new_blk);
1158  xd_set_err_code(chip, XD_PRG_ERROR);
1159  XD_SET_BAD_NEWBLK(xd_card);
1160  } else {
1161  xd_set_err_code(chip, XD_TO_ERROR);
1162  }
1163  TRACE_RET(chip, STATUS_FAIL);
1164  }
1165 
1166  old_page++;
1167  new_page++;
1168  }
1169 
1170  return STATUS_SUCCESS;
1171 }
1172 
1173 static int xd_reset_cmd(struct rtsx_chip *chip)
1174 {
1175  int retval;
1176  u8 *ptr;
1177 
1178  rtsx_init_cmd(chip);
1179 
1180  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_RESET);
1181  rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
1182  rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
1183  rtsx_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0);
1184 
1185  retval = rtsx_send_cmd(chip, XD_CARD, 100);
1186  if (retval < 0)
1187  TRACE_RET(chip, STATUS_FAIL);
1188 
1189  ptr = rtsx_get_cmd_data(chip) + 1;
1190  if (((ptr[0] & READY_FLAG) == READY_STATE) && (ptr[1] & XD_RDY))
1191  return STATUS_SUCCESS;
1192 
1193  TRACE_RET(chip, STATUS_FAIL);
1194 }
1195 
1196 static int xd_erase_block(struct rtsx_chip *chip, u32 phy_blk)
1197 {
1198  struct xd_info *xd_card = &(chip->xd_card);
1199  u32 page_addr;
1200  u8 reg = 0, *ptr;
1201  int i, retval;
1202 
1203  if (phy_blk == BLK_NOT_FOUND)
1204  TRACE_RET(chip, STATUS_FAIL);
1205 
1206  page_addr = phy_blk << xd_card->block_shift;
1207 
1208  for (i = 0; i < 3; i++) {
1209  rtsx_init_cmd(chip);
1210 
1211  xd_assign_phy_addr(chip, page_addr, XD_ERASE_ADDR);
1212 
1213  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_ERASE);
1214  rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
1215  rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
1216 
1217  retval = rtsx_send_cmd(chip, XD_CARD, 250);
1218  if (retval < 0) {
1219  rtsx_clear_xd_error(chip);
1220  rtsx_read_register(chip, XD_DAT, &reg);
1221  if (reg & PROGRAM_ERROR) {
1222  xd_mark_bad_block(chip, phy_blk);
1223  xd_set_err_code(chip, XD_PRG_ERROR);
1224  TRACE_RET(chip, STATUS_FAIL);
1225  } else {
1226  xd_set_err_code(chip, XD_ERASE_FAIL);
1227  }
1228  retval = xd_reset_cmd(chip);
1229  if (retval != STATUS_SUCCESS)
1230  TRACE_RET(chip, STATUS_FAIL);
1231  continue;
1232  }
1233 
1234  ptr = rtsx_get_cmd_data(chip) + 1;
1235  if (*ptr & PROGRAM_ERROR) {
1236  xd_mark_bad_block(chip, phy_blk);
1237  xd_set_err_code(chip, XD_PRG_ERROR);
1238  TRACE_RET(chip, STATUS_FAIL);
1239  }
1240 
1241  return STATUS_SUCCESS;
1242  }
1243 
1244  xd_mark_bad_block(chip, phy_blk);
1245  xd_set_err_code(chip, XD_ERASE_FAIL);
1246  TRACE_RET(chip, STATUS_FAIL);
1247 }
1248 
1249 
1250 static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no)
1251 {
1252  struct xd_info *xd_card = &(chip->xd_card);
1253  struct zone_entry *zone;
1254  int retval;
1255  u32 start, end, i;
1256  u16 max_logoff, cur_fst_page_logoff, cur_lst_page_logoff, ent_lst_page_logoff;
1257  u8 redunt[11];
1258 
1259  RTSX_DEBUGP("xd_build_l2p_tbl: %d\n", zone_no);
1260 
1261  if (xd_card->zone == NULL) {
1262  retval = xd_init_l2p_tbl(chip);
1263  if (retval != STATUS_SUCCESS)
1264  return retval;
1265  }
1266 
1267  if (xd_card->zone[zone_no].build_flag) {
1268  RTSX_DEBUGP("l2p table of zone %d has been built\n", zone_no);
1269  return STATUS_SUCCESS;
1270  }
1271 
1272  zone = &(xd_card->zone[zone_no]);
1273 
1274  if (zone->l2p_table == NULL) {
1275  zone->l2p_table = (u16 *)vmalloc(2000);
1276  if (zone->l2p_table == NULL)
1277  TRACE_GOTO(chip, Build_Fail);
1278  }
1279  memset((u8 *)(zone->l2p_table), 0xff, 2000);
1280 
1281  if (zone->free_table == NULL) {
1282  zone->free_table = (u16 *)vmalloc(XD_FREE_TABLE_CNT * 2);
1283  if (zone->free_table == NULL)
1284  TRACE_GOTO(chip, Build_Fail);
1285  }
1286  memset((u8 *)(zone->free_table), 0xff, XD_FREE_TABLE_CNT * 2);
1287 
1288  if (zone_no == 0) {
1289  if (xd_card->cis_block == 0xFFFF)
1290  start = 0;
1291  else
1292  start = xd_card->cis_block + 1;
1293  if (XD_CHK_4MB(xd_card)) {
1294  end = 0x200;
1295  max_logoff = 499;
1296  } else {
1297  end = 0x400;
1298  max_logoff = 999;
1299  }
1300  } else {
1301  start = (u32)(zone_no) << 10;
1302  end = (u32)(zone_no + 1) << 10;
1303  max_logoff = 999;
1304  }
1305 
1306  RTSX_DEBUGP("start block 0x%x, end block 0x%x\n", start, end);
1307 
1308  zone->set_index = zone->get_index = 0;
1309  zone->unused_blk_cnt = 0;
1310 
1311  for (i = start; i < end; i++) {
1312  u32 page_addr = i << xd_card->block_shift;
1313  u32 phy_block;
1314 
1315  retval = xd_read_redundant(chip, page_addr, redunt, 11);
1316  if (retval != STATUS_SUCCESS)
1317  continue;
1318 
1319  if (redunt[BLOCK_STATUS] != 0xFF) {
1320  RTSX_DEBUGP("bad block\n");
1321  continue;
1322  }
1323 
1324  if (xd_check_data_blank(redunt)) {
1325  RTSX_DEBUGP("blank block\n");
1326  xd_set_unused_block(chip, i);
1327  continue;
1328  }
1329 
1330  cur_fst_page_logoff = xd_load_log_block_addr(redunt);
1331  if ((cur_fst_page_logoff == 0xFFFF) || (cur_fst_page_logoff > max_logoff)) {
1332  retval = xd_erase_block(chip, i);
1333  if (retval == STATUS_SUCCESS)
1334  xd_set_unused_block(chip, i);
1335  continue;
1336  }
1337 
1338  if ((zone_no == 0) && (cur_fst_page_logoff == 0) && (redunt[PAGE_STATUS] != XD_GPG))
1339  XD_SET_MBR_FAIL(xd_card);
1340 
1341  if (zone->l2p_table[cur_fst_page_logoff] == 0xFFFF) {
1342  zone->l2p_table[cur_fst_page_logoff] = (u16)(i & 0x3FF);
1343  continue;
1344  }
1345 
1346  phy_block = zone->l2p_table[cur_fst_page_logoff] + ((u32)((zone_no) << 10));
1347 
1348  page_addr = ((i + 1) << xd_card->block_shift) - 1;
1349 
1350  retval = xd_read_redundant(chip, page_addr, redunt, 11);
1351  if (retval != STATUS_SUCCESS)
1352  continue;
1353 
1354  cur_lst_page_logoff = xd_load_log_block_addr(redunt);
1355  if (cur_lst_page_logoff == cur_fst_page_logoff) {
1356  int m;
1357 
1358  page_addr = ((phy_block + 1) << xd_card->block_shift) - 1;
1359 
1360  for (m = 0; m < 3; m++) {
1361  retval = xd_read_redundant(chip, page_addr, redunt, 11);
1362  if (retval == STATUS_SUCCESS)
1363  break;
1364  }
1365 
1366  if (m == 3) {
1367  zone->l2p_table[cur_fst_page_logoff] = (u16)(i & 0x3FF);
1368  retval = xd_erase_block(chip, phy_block);
1369  if (retval == STATUS_SUCCESS)
1370  xd_set_unused_block(chip, phy_block);
1371  continue;
1372  }
1373 
1374  ent_lst_page_logoff = xd_load_log_block_addr(redunt);
1375  if (ent_lst_page_logoff != cur_fst_page_logoff) {
1376  zone->l2p_table[cur_fst_page_logoff] = (u16)(i & 0x3FF);
1377  retval = xd_erase_block(chip, phy_block);
1378  if (retval == STATUS_SUCCESS)
1379  xd_set_unused_block(chip, phy_block);
1380  continue;
1381  } else {
1382  retval = xd_erase_block(chip, i);
1383  if (retval == STATUS_SUCCESS)
1384  xd_set_unused_block(chip, i);
1385  }
1386  } else {
1387  retval = xd_erase_block(chip, i);
1388  if (retval == STATUS_SUCCESS)
1389  xd_set_unused_block(chip, i);
1390  }
1391  }
1392 
1393  if (XD_CHK_4MB(xd_card))
1394  end = 500;
1395  else
1396  end = 1000;
1397 
1398  i = 0;
1399  for (start = 0; start < end; start++) {
1400  if (zone->l2p_table[start] == 0xFFFF)
1401  i++;
1402  }
1403 
1404  RTSX_DEBUGP("Block count %d, invalid L2P entry %d\n", end, i);
1405  RTSX_DEBUGP("Total unused block: %d\n", zone->unused_blk_cnt);
1406 
1407  if ((zone->unused_blk_cnt - i) < 1)
1408  chip->card_wp |= XD_CARD;
1409 
1410  zone->build_flag = 1;
1411 
1412  return STATUS_SUCCESS;
1413 
1414 Build_Fail:
1415  if (zone->l2p_table) {
1416  vfree(zone->l2p_table);
1417  zone->l2p_table = NULL;
1418  }
1419  if (zone->free_table) {
1420  vfree(zone->free_table);
1421  zone->free_table = NULL;
1422  }
1423 
1424  return STATUS_FAIL;
1425 }
1426 
1427 static int xd_send_cmd(struct rtsx_chip *chip, u8 cmd)
1428 {
1429  int retval;
1430 
1431  rtsx_init_cmd(chip);
1432 
1433  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, cmd);
1434  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_SET_CMD);
1435  rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
1436 
1437  retval = rtsx_send_cmd(chip, XD_CARD, 200);
1438  if (retval < 0)
1439  TRACE_RET(chip, STATUS_FAIL);
1440 
1441  return STATUS_SUCCESS;
1442 }
1443 
1444 static int xd_read_multiple_pages(struct rtsx_chip *chip, u32 phy_blk, u32 log_blk,
1445  u8 start_page, u8 end_page, u8 *buf, unsigned int *index, unsigned int *offset)
1446 {
1447  struct xd_info *xd_card = &(chip->xd_card);
1448  u32 page_addr, new_blk;
1449  u16 log_off;
1450  u8 reg_val, page_cnt;
1451  int zone_no, retval, i;
1452 
1453  if (start_page > end_page)
1454  TRACE_RET(chip, STATUS_FAIL);
1455 
1456  page_cnt = end_page - start_page;
1457  zone_no = (int)(log_blk / 1000);
1458  log_off = (u16)(log_blk % 1000);
1459 
1460  if ((phy_blk & 0x3FF) == 0x3FF) {
1461  for (i = 0; i < 256; i++) {
1462  page_addr = ((u32)i) << xd_card->block_shift;
1463 
1464  retval = xd_read_redundant(chip, page_addr, NULL, 0);
1465  if (retval == STATUS_SUCCESS)
1466  break;
1467 
1468  if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1469  xd_set_err_code(chip, XD_NO_CARD);
1470  TRACE_RET(chip, STATUS_FAIL);
1471  }
1472  }
1473  }
1474 
1475  page_addr = (phy_blk << xd_card->block_shift) + start_page;
1476 
1477  rtsx_init_cmd(chip);
1478 
1479  xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1480  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_PPB_TO_SIE, XD_PPB_TO_SIE);
1481  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
1482  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt);
1483  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
1484  XD_AUTO_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS);
1485 
1486  trans_dma_enable(chip->srb->sc_data_direction, chip, page_cnt * 512, DMA_512);
1487 
1488  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_READ_PAGES);
1489  rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1490  XD_TRANSFER_END | XD_PPB_EMPTY, XD_TRANSFER_END | XD_PPB_EMPTY);
1491 
1492  rtsx_send_cmd_no_wait(chip);
1493 
1494  retval = rtsx_transfer_data_partial(chip, XD_CARD, buf, page_cnt * 512, scsi_sg_count(chip->srb),
1495  index, offset, DMA_FROM_DEVICE, chip->xd_timeout);
1496  if (retval < 0) {
1497  rtsx_clear_xd_error(chip);
1498  xd_clear_dma_buffer(chip);
1499 
1500  if (retval == -ETIMEDOUT) {
1501  xd_set_err_code(chip, XD_TO_ERROR);
1502  TRACE_RET(chip, STATUS_FAIL);
1503  } else {
1504  TRACE_GOTO(chip, Fail);
1505  }
1506  }
1507 
1508  return STATUS_SUCCESS;
1509 
1510 Fail:
1511  RTSX_READ_REG(chip, XD_PAGE_STATUS, &reg_val);
1512 
1513  if (reg_val != XD_GPG)
1514  xd_set_err_code(chip, XD_PRG_ERROR);
1515 
1516  RTSX_READ_REG(chip, XD_CTL, &reg_val);
1517 
1518  if (((reg_val & (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE))
1519  == (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE))
1520  || ((reg_val & (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))
1521  == (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))) {
1522  wait_timeout(100);
1523 
1524  if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1525  xd_set_err_code(chip, XD_NO_CARD);
1526  TRACE_RET(chip, STATUS_FAIL);
1527  }
1528 
1529  xd_set_err_code(chip, XD_ECC_ERROR);
1530 
1531  new_blk = xd_get_unused_block(chip, zone_no);
1532  if (new_blk == NO_NEW_BLK) {
1533  XD_CLR_BAD_OLDBLK(xd_card);
1534  TRACE_RET(chip, STATUS_FAIL);
1535  }
1536 
1537  retval = xd_copy_page(chip, phy_blk, new_blk, 0, xd_card->page_off + 1);
1538  if (retval != STATUS_SUCCESS) {
1539  if (!XD_CHK_BAD_NEWBLK(xd_card)) {
1540  retval = xd_erase_block(chip, new_blk);
1541  if (retval == STATUS_SUCCESS)
1542  xd_set_unused_block(chip, new_blk);
1543  } else {
1544  XD_CLR_BAD_NEWBLK(xd_card);
1545  }
1546  XD_CLR_BAD_OLDBLK(xd_card);
1547  TRACE_RET(chip, STATUS_FAIL);
1548  }
1549  xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF));
1550  xd_erase_block(chip, phy_blk);
1551  xd_mark_bad_block(chip, phy_blk);
1552  XD_CLR_BAD_OLDBLK(xd_card);
1553  }
1554 
1555  TRACE_RET(chip, STATUS_FAIL);
1556 }
1557 
1558 static int xd_finish_write(struct rtsx_chip *chip,
1559  u32 old_blk, u32 new_blk, u32 log_blk, u8 page_off)
1560 {
1561  struct xd_info *xd_card = &(chip->xd_card);
1562  int retval, zone_no;
1563  u16 log_off;
1564 
1565  RTSX_DEBUGP("xd_finish_write, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x\n",
1566  old_blk, new_blk, log_blk);
1567 
1568  if (page_off > xd_card->page_off)
1569  TRACE_RET(chip, STATUS_FAIL);
1570 
1571  zone_no = (int)(log_blk / 1000);
1572  log_off = (u16)(log_blk % 1000);
1573 
1574  if (old_blk == BLK_NOT_FOUND) {
1575  retval = xd_init_page(chip, new_blk, log_off,
1576  page_off, xd_card->page_off + 1);
1577  if (retval != STATUS_SUCCESS) {
1578  retval = xd_erase_block(chip, new_blk);
1579  if (retval == STATUS_SUCCESS)
1580  xd_set_unused_block(chip, new_blk);
1581  TRACE_RET(chip, STATUS_FAIL);
1582  }
1583  } else {
1584  retval = xd_copy_page(chip, old_blk, new_blk,
1585  page_off, xd_card->page_off + 1);
1586  if (retval != STATUS_SUCCESS) {
1587  if (!XD_CHK_BAD_NEWBLK(xd_card)) {
1588  retval = xd_erase_block(chip, new_blk);
1589  if (retval == STATUS_SUCCESS)
1590  xd_set_unused_block(chip, new_blk);
1591  }
1592  XD_CLR_BAD_NEWBLK(xd_card);
1593  TRACE_RET(chip, STATUS_FAIL);
1594  }
1595 
1596  retval = xd_erase_block(chip, old_blk);
1597  if (retval == STATUS_SUCCESS) {
1598  if (XD_CHK_BAD_OLDBLK(xd_card)) {
1599  xd_mark_bad_block(chip, old_blk);
1600  XD_CLR_BAD_OLDBLK(xd_card);
1601  } else {
1602  xd_set_unused_block(chip, old_blk);
1603  }
1604  } else {
1605  xd_set_err_code(chip, XD_NO_ERROR);
1606  XD_CLR_BAD_OLDBLK(xd_card);
1607  }
1608  }
1609 
1610  xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF));
1611 
1612  return STATUS_SUCCESS;
1613 }
1614 
1615 static int xd_prepare_write(struct rtsx_chip *chip,
1616  u32 old_blk, u32 new_blk, u32 log_blk, u8 page_off)
1617 {
1618  int retval;
1619 
1620  RTSX_DEBUGP("%s, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x, page_off = %d\n",
1621  __func__, old_blk, new_blk, log_blk, (int)page_off);
1622 
1623  if (page_off) {
1624  retval = xd_copy_page(chip, old_blk, new_blk, 0, page_off);
1625  if (retval != STATUS_SUCCESS)
1626  TRACE_RET(chip, STATUS_FAIL);
1627  }
1628 
1629  return STATUS_SUCCESS;
1630 }
1631 
1632 
1633 static int xd_write_multiple_pages(struct rtsx_chip *chip, u32 old_blk, u32 new_blk, u32 log_blk,
1634  u8 start_page, u8 end_page, u8 *buf, unsigned int *index, unsigned int *offset)
1635 {
1636  struct xd_info *xd_card = &(chip->xd_card);
1637  u32 page_addr;
1638  int zone_no, retval;
1639  u16 log_off;
1640  u8 page_cnt, reg_val;
1641 
1642  RTSX_DEBUGP("%s, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x\n",
1643  __func__, old_blk, new_blk, log_blk);
1644 
1645  if (start_page > end_page)
1646  TRACE_RET(chip, STATUS_FAIL);
1647 
1648  page_cnt = end_page - start_page;
1649  zone_no = (int)(log_blk / 1000);
1650  log_off = (u16)(log_blk % 1000);
1651 
1652  page_addr = (new_blk << xd_card->block_shift) + start_page;
1653 
1654  retval = xd_send_cmd(chip, READ1_1);
1655  if (retval != STATUS_SUCCESS)
1656  TRACE_RET(chip, STATUS_FAIL);
1657 
1658  rtsx_init_cmd(chip);
1659 
1660  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 0xFF, (u8)(log_off >> 8));
1661  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, (u8)log_off);
1662  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, XD_GBLK);
1663  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG);
1664 
1665  xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1666 
1667  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_BA_TRANSFORM, XD_BA_TRANSFORM);
1668  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt);
1669  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
1670 
1671  trans_dma_enable(chip->srb->sc_data_direction, chip, page_cnt * 512, DMA_512);
1672 
1673  rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_WRITE_PAGES);
1674  rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
1675 
1676  rtsx_send_cmd_no_wait(chip);
1677 
1678  retval = rtsx_transfer_data_partial(chip, XD_CARD, buf, page_cnt * 512, scsi_sg_count(chip->srb),
1679  index, offset, DMA_TO_DEVICE, chip->xd_timeout);
1680  if (retval < 0) {
1681  rtsx_clear_xd_error(chip);
1682 
1683  if (retval == -ETIMEDOUT) {
1684  xd_set_err_code(chip, XD_TO_ERROR);
1685  TRACE_RET(chip, STATUS_FAIL);
1686  } else {
1687  TRACE_GOTO(chip, Fail);
1688  }
1689  }
1690 
1691  if (end_page == (xd_card->page_off + 1)) {
1692  xd_card->delay_write.delay_write_flag = 0;
1693 
1694  if (old_blk != BLK_NOT_FOUND) {
1695  retval = xd_erase_block(chip, old_blk);
1696  if (retval == STATUS_SUCCESS) {
1697  if (XD_CHK_BAD_OLDBLK(xd_card)) {
1698  xd_mark_bad_block(chip, old_blk);
1699  XD_CLR_BAD_OLDBLK(xd_card);
1700  } else {
1701  xd_set_unused_block(chip, old_blk);
1702  }
1703  } else {
1704  xd_set_err_code(chip, XD_NO_ERROR);
1705  XD_CLR_BAD_OLDBLK(xd_card);
1706  }
1707  }
1708  xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF));
1709  }
1710 
1711  return STATUS_SUCCESS;
1712 
1713 Fail:
1714  RTSX_READ_REG(chip, XD_DAT, &reg_val);
1715  if (reg_val & PROGRAM_ERROR) {
1716  xd_set_err_code(chip, XD_PRG_ERROR);
1717  xd_mark_bad_block(chip, new_blk);
1718  }
1719 
1720  TRACE_RET(chip, STATUS_FAIL);
1721 }
1722 
1723 #ifdef XD_DELAY_WRITE
1724 int xd_delay_write(struct rtsx_chip *chip)
1725 {
1726  struct xd_info *xd_card = &(chip->xd_card);
1727  struct xd_delay_write_tag *delay_write = &(xd_card->delay_write);
1728  int retval;
1729 
1730  if (delay_write->delay_write_flag) {
1731  RTSX_DEBUGP("xd_delay_write\n");
1732  retval = xd_switch_clock(chip);
1733  if (retval != STATUS_SUCCESS)
1734  TRACE_RET(chip, STATUS_FAIL);
1735 
1736  delay_write->delay_write_flag = 0;
1737  retval = xd_finish_write(chip,
1738  delay_write->old_phyblock, delay_write->new_phyblock,
1739  delay_write->logblock, delay_write->pageoff);
1740  if (retval != STATUS_SUCCESS)
1741  TRACE_RET(chip, STATUS_FAIL);
1742  }
1743 
1744  return STATUS_SUCCESS;
1745 }
1746 #endif
1747 
1748 int xd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 start_sector, u16 sector_cnt)
1749 {
1750  struct xd_info *xd_card = &(chip->xd_card);
1751  unsigned int lun = SCSI_LUN(srb);
1752 #ifdef XD_DELAY_WRITE
1753  struct xd_delay_write_tag *delay_write = &(xd_card->delay_write);
1754 #endif
1755  int retval, zone_no;
1756  unsigned int index = 0, offset = 0;
1757  u32 log_blk, old_blk = 0, new_blk = 0;
1758  u16 log_off, total_sec_cnt = sector_cnt;
1759  u8 start_page, end_page = 0, page_cnt;
1760  u8 *ptr;
1761 
1762  xd_set_err_code(chip, XD_NO_ERROR);
1763 
1764  xd_card->cleanup_counter = 0;
1765 
1766  RTSX_DEBUGP("xd_rw: scsi_sg_count = %d\n", scsi_sg_count(srb));
1767 
1768  ptr = (u8 *)scsi_sglist(srb);
1769 
1770  retval = xd_switch_clock(chip);
1771  if (retval != STATUS_SUCCESS)
1772  TRACE_RET(chip, STATUS_FAIL);
1773 
1774 
1775  if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1776  chip->card_fail |= XD_CARD;
1777  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1778  TRACE_RET(chip, STATUS_FAIL);
1779  }
1780 
1781  log_blk = start_sector >> xd_card->block_shift;
1782  start_page = (u8)start_sector & xd_card->page_off;
1783  zone_no = (int)(log_blk / 1000);
1784  log_off = (u16)(log_blk % 1000);
1785 
1786  if (xd_card->zone[zone_no].build_flag == 0) {
1787  retval = xd_build_l2p_tbl(chip, zone_no);
1788  if (retval != STATUS_SUCCESS) {
1789  chip->card_fail |= XD_CARD;
1790  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1791  TRACE_RET(chip, STATUS_FAIL);
1792  }
1793  }
1794 
1795  if (srb->sc_data_direction == DMA_TO_DEVICE) {
1796 #ifdef XD_DELAY_WRITE
1797  if (delay_write->delay_write_flag &&
1798  (delay_write->logblock == log_blk) &&
1799  (start_page > delay_write->pageoff)) {
1800  delay_write->delay_write_flag = 0;
1801  if (delay_write->old_phyblock != BLK_NOT_FOUND) {
1802  retval = xd_copy_page(chip,
1803  delay_write->old_phyblock,
1804  delay_write->new_phyblock,
1805  delay_write->pageoff, start_page);
1806  if (retval != STATUS_SUCCESS) {
1807  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
1808  TRACE_RET(chip, STATUS_FAIL);
1809  }
1810  }
1811  old_blk = delay_write->old_phyblock;
1812  new_blk = delay_write->new_phyblock;
1813  } else if (delay_write->delay_write_flag &&
1814  (delay_write->logblock == log_blk) &&
1815  (start_page == delay_write->pageoff)) {
1816  delay_write->delay_write_flag = 0;
1817  old_blk = delay_write->old_phyblock;
1818  new_blk = delay_write->new_phyblock;
1819  } else {
1820  retval = xd_delay_write(chip);
1821  if (retval != STATUS_SUCCESS) {
1822  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
1823  TRACE_RET(chip, STATUS_FAIL);
1824  }
1825 #endif
1826  old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
1827  new_blk = xd_get_unused_block(chip, zone_no);
1828  if ((old_blk == BLK_NOT_FOUND) || (new_blk == BLK_NOT_FOUND)) {
1829  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
1830  TRACE_RET(chip, STATUS_FAIL);
1831  }
1832 
1833  retval = xd_prepare_write(chip, old_blk, new_blk, log_blk, start_page);
1834  if (retval != STATUS_SUCCESS) {
1835  if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1836  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1837  TRACE_RET(chip, STATUS_FAIL);
1838  }
1839  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
1840  TRACE_RET(chip, STATUS_FAIL);
1841  }
1842 #ifdef XD_DELAY_WRITE
1843  }
1844 #endif
1845  } else {
1846 #ifdef XD_DELAY_WRITE
1847  retval = xd_delay_write(chip);
1848  if (retval != STATUS_SUCCESS) {
1849  if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1850  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1851  TRACE_RET(chip, STATUS_FAIL);
1852  }
1853  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
1854  TRACE_RET(chip, STATUS_FAIL);
1855  }
1856 #endif
1857 
1858  old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
1859  if (old_blk == BLK_NOT_FOUND) {
1860  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
1861  TRACE_RET(chip, STATUS_FAIL);
1862  }
1863  }
1864 
1865  RTSX_DEBUGP("old_blk = 0x%x\n", old_blk);
1866 
1867  while (total_sec_cnt) {
1868  if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1869  chip->card_fail |= XD_CARD;
1870  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1871  TRACE_RET(chip, STATUS_FAIL);
1872  }
1873 
1874  if ((start_page + total_sec_cnt) > (xd_card->page_off + 1))
1875  end_page = xd_card->page_off + 1;
1876  else
1877  end_page = start_page + (u8)total_sec_cnt;
1878 
1879  page_cnt = end_page - start_page;
1880  if (srb->sc_data_direction == DMA_FROM_DEVICE) {
1881  retval = xd_read_multiple_pages(chip, old_blk, log_blk,
1882  start_page, end_page, ptr, &index, &offset);
1883  if (retval != STATUS_SUCCESS) {
1884  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
1885  TRACE_RET(chip, STATUS_FAIL);
1886  }
1887  } else {
1888  retval = xd_write_multiple_pages(chip, old_blk, new_blk, log_blk,
1889  start_page, end_page, ptr, &index, &offset);
1890  if (retval != STATUS_SUCCESS) {
1891  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
1892  TRACE_RET(chip, STATUS_FAIL);
1893  }
1894  }
1895 
1896  total_sec_cnt -= page_cnt;
1897  if (scsi_sg_count(srb) == 0)
1898  ptr += page_cnt * 512;
1899 
1900  if (total_sec_cnt == 0)
1901  break;
1902 
1903  log_blk++;
1904  zone_no = (int)(log_blk / 1000);
1905  log_off = (u16)(log_blk % 1000);
1906 
1907  if (xd_card->zone[zone_no].build_flag == 0) {
1908  retval = xd_build_l2p_tbl(chip, zone_no);
1909  if (retval != STATUS_SUCCESS) {
1910  chip->card_fail |= XD_CARD;
1911  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1912  TRACE_RET(chip, STATUS_FAIL);
1913  }
1914  }
1915 
1916  old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
1917  if (old_blk == BLK_NOT_FOUND) {
1918  if (srb->sc_data_direction == DMA_FROM_DEVICE)
1919  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
1920  else
1921  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
1922 
1923  TRACE_RET(chip, STATUS_FAIL);
1924  }
1925 
1926  if (srb->sc_data_direction == DMA_TO_DEVICE) {
1927  new_blk = xd_get_unused_block(chip, zone_no);
1928  if (new_blk == BLK_NOT_FOUND) {
1929  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
1930  TRACE_RET(chip, STATUS_FAIL);
1931  }
1932  }
1933 
1934  start_page = 0;
1935  }
1936 
1937  if ((srb->sc_data_direction == DMA_TO_DEVICE) &&
1938  (end_page != (xd_card->page_off + 1))) {
1939 #ifdef XD_DELAY_WRITE
1940  delay_write->delay_write_flag = 1;
1941  delay_write->old_phyblock = old_blk;
1942  delay_write->new_phyblock = new_blk;
1943  delay_write->logblock = log_blk;
1944  delay_write->pageoff = end_page;
1945 #else
1946  if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1947  chip->card_fail |= XD_CARD;
1948  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1949  TRACE_RET(chip, STATUS_FAIL);
1950  }
1951 
1952  retval = xd_finish_write(chip, old_blk, new_blk, log_blk, end_page);
1953  if (retval != STATUS_SUCCESS) {
1954  if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1955  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1956  TRACE_RET(chip, STATUS_FAIL);
1957  }
1958  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
1959  TRACE_RET(chip, STATUS_FAIL);
1960  }
1961 #endif
1962  }
1963 
1964  scsi_set_resid(srb, 0);
1965 
1966  return STATUS_SUCCESS;
1967 }
1968 
1969 void xd_free_l2p_tbl(struct rtsx_chip *chip)
1970 {
1971  struct xd_info *xd_card = &(chip->xd_card);
1972  int i = 0;
1973 
1974  if (xd_card->zone != NULL) {
1975  for (i = 0; i < xd_card->zone_cnt; i++) {
1976  if (xd_card->zone[i].l2p_table != NULL) {
1977  vfree(xd_card->zone[i].l2p_table);
1978  xd_card->zone[i].l2p_table = NULL;
1979  }
1980  if (xd_card->zone[i].free_table != NULL) {
1981  vfree(xd_card->zone[i].free_table);
1982  xd_card->zone[i].free_table = NULL;
1983  }
1984  }
1985  vfree(xd_card->zone);
1986  xd_card->zone = NULL;
1987  }
1988 }
1989 
1990 void xd_cleanup_work(struct rtsx_chip *chip)
1991 {
1992 #ifdef XD_DELAY_WRITE
1993  struct xd_info *xd_card = &(chip->xd_card);
1994 
1995  if (xd_card->delay_write.delay_write_flag) {
1996  RTSX_DEBUGP("xD: delay write\n");
1997  xd_delay_write(chip);
1998  xd_card->cleanup_counter = 0;
1999  }
2000 #endif
2001 }
2002 
2003 int xd_power_off_card3v3(struct rtsx_chip *chip)
2004 {
2005  int retval;
2006 
2007  retval = disable_card_clock(chip, XD_CARD);
2008  if (retval != STATUS_SUCCESS)
2009  TRACE_RET(chip, STATUS_FAIL);
2010 
2011  RTSX_WRITE_REG(chip, CARD_OE, XD_OUTPUT_EN, 0);
2012 
2013  if (!chip->ft2_fast_mode) {
2014  retval = card_power_off(chip, XD_CARD);
2015  if (retval != STATUS_SUCCESS)
2016  TRACE_RET(chip, STATUS_FAIL);
2017 
2018  wait_timeout(50);
2019  }
2020 
2021  if (chip->asic_code) {
2022  retval = xd_pull_ctl_disable(chip);
2023  if (retval != STATUS_SUCCESS)
2024  TRACE_RET(chip, STATUS_FAIL);
2025  } else {
2026  RTSX_WRITE_REG(chip, FPGA_PULL_CTL, 0xFF, 0xDF);
2027  }
2028 
2029  return STATUS_SUCCESS;
2030 }
2031 
2032 int release_xd_card(struct rtsx_chip *chip)
2033 {
2034  struct xd_info *xd_card = &(chip->xd_card);
2035  int retval;
2036 
2037  RTSX_DEBUGP("release_xd_card\n");
2038 
2039  chip->card_ready &= ~XD_CARD;
2040  chip->card_fail &= ~XD_CARD;
2041  chip->card_wp &= ~XD_CARD;
2042 
2043  xd_card->delay_write.delay_write_flag = 0;
2044 
2045  xd_free_l2p_tbl(chip);
2046 
2047  retval = xd_power_off_card3v3(chip);
2048  if (retval != STATUS_SUCCESS)
2049  TRACE_RET(chip, STATUS_FAIL);
2050 
2051  return STATUS_SUCCESS;
2052 }
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