|
| #define | DEBUG(x) do {} while (0) |
| |
| #define | DDEBUG(prefix, scmd, fmt, a...) do {} while (0) |
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| #define | CDEBUG(prefix, scmd, fmt, a...) do {} while (0) |
| |
| #define | NCR_700_COMMAND_SLOTS_PER_HOST 64 |
| |
| #define | NCR_700_SG_SEGMENTS 32 |
| |
| #define | NCR_700_MAX_LUNS 32 |
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| #define | NCR_700_LUN_MASK (NCR_700_MAX_LUNS - 1) |
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| #define | NCR_700_MAX_TAGS 16 |
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| #define | NCR_700_DEFAULT_TAGS 4 |
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| #define | NCR_700_CMD_PER_LUN 2 |
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| #define | NCR_700_INTERNAL_SENSE_MAGIC 0x42 |
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| #define | SCRIPT_MOVE_DATA_IN 0x09000000 |
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| #define | SCRIPT_MOVE_DATA_OUT 0x08000000 |
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| #define | SCRIPT_NOP 0x80000000 |
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| #define | SCRIPT_RETURN 0x90080000 |
| |
| #define | NCR_700_DEV_NEGOTIATED_SYNC (1<<16) |
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| #define | NCR_700_DEV_BEGIN_SYNC_NEGOTIATION (1<<17) |
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| #define | NCR_700_DEV_PRINT_SYNC_NEGOTIATION (1<<19) |
| |
| #define | NCR_700_SLOT_MASK 0xFC |
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| #define | NCR_700_SLOT_MAGIC 0xb8 |
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| #define | NCR_700_SLOT_FREE (0|NCR_700_SLOT_MAGIC) /* slot may be used */ |
| |
| #define | NCR_700_SLOT_BUSY (1|NCR_700_SLOT_MAGIC) /* slot has command active on HA */ |
| |
| #define | NCR_700_SLOT_QUEUED (2|NCR_700_SLOT_MAGIC) /* slot has command to be made active on HA */ |
| |
| #define | NCR_700_FLAG_AUTOSENSE 0x01 |
| |
| #define | MSG_ARRAY_SIZE 8 |
| |
| #define | MSGOUT_OFFSET (L1_CACHE_ALIGN(sizeof(SCRIPT))) |
| |
| #define | MSGIN_OFFSET (MSGOUT_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE)) |
| |
| #define | STATUS_OFFSET (MSGIN_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE)) |
| |
| #define | SLOTS_OFFSET (STATUS_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE)) |
| |
| #define | TOTAL_MEM_SIZE (SLOTS_OFFSET + L1_CACHE_ALIGN(sizeof(struct NCR_700_command_slot) * NCR_700_COMMAND_SLOTS_PER_HOST)) |
| |
| #define | bEBus 0 |
| |
| #define | bS_to_cpu(x) (bSWAP ? le32_to_cpu(x) : (x)) |
| |
| #define | bS_to_host(x) (bSWAP ? cpu_to_le32(x) : (x)) |
| |
| #define | SCNTL0_REG 0x00 |
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| #define | FULL_ARBITRATION 0xc0 |
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| #define | PARITY 0x08 |
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| #define | ENABLE_PARITY 0x04 |
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| #define | AUTO_ATN 0x02 |
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| #define | SCNTL1_REG 0x01 |
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| #define | SLOW_BUS 0x80 |
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| #define | ENABLE_SELECT 0x20 |
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| #define | ASSERT_RST 0x08 |
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| #define | ASSERT_EVEN_PARITY 0x04 |
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| #define | SDID_REG 0x02 |
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| #define | SIEN_REG 0x03 |
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| #define | PHASE_MM_INT 0x80 |
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| #define | FUNC_COMP_INT 0x40 |
| |
| #define | SEL_TIMEOUT_INT 0x20 |
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| #define | SELECT_INT 0x10 |
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| #define | GROSS_ERR_INT 0x08 |
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| #define | UX_DISC_INT 0x04 |
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| #define | RST_INT 0x02 |
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| #define | PAR_ERR_INT 0x01 |
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| #define | SCID_REG 0x04 |
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| #define | SXFER_REG 0x05 |
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| #define | ASYNC_OPERATION 0x00 |
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| #define | SODL_REG 0x06 |
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| #define | SOCL_REG 0x07 |
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| #define | SFBR_REG 0x08 |
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| #define | SIDL_REG 0x09 |
| |
| #define | SBDL_REG 0x0A |
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| #define | SBCL_REG 0x0B |
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| #define | SBCL_IO 0x01 |
| |
| #define | SYNC_DIV_AS_ASYNC 0x00 |
| |
| #define | SYNC_DIV_1_0 0x01 |
| |
| #define | SYNC_DIV_1_5 0x02 |
| |
| #define | SYNC_DIV_2_0 0x03 |
| |
| #define | DSTAT_REG 0x0C |
| |
| #define | ILGL_INST_DETECTED 0x01 |
| |
| #define | WATCH_DOG_INTERRUPT 0x02 |
| |
| #define | SCRIPT_INT_RECEIVED 0x04 |
| |
| #define | ABORTED 0x10 |
| |
| #define | SSTAT0_REG 0x0D |
| |
| #define | PARITY_ERROR 0x01 |
| |
| #define | SCSI_RESET_DETECTED 0x02 |
| |
| #define | UNEXPECTED_DISCONNECT 0x04 |
| |
| #define | SCSI_GROSS_ERROR 0x08 |
| |
| #define | SELECTED 0x10 |
| |
| #define | SELECTION_TIMEOUT 0x20 |
| |
| #define | FUNCTION_COMPLETE 0x40 |
| |
| #define | PHASE_MISMATCH 0x80 |
| |
| #define | SSTAT1_REG 0x0E |
| |
| #define | SIDL_REG_FULL 0x80 |
| |
| #define | SODR_REG_FULL 0x40 |
| |
| #define | SODL_REG_FULL 0x20 |
| |
| #define | SSTAT2_REG 0x0F |
| |
| #define | CTEST0_REG 0x14 |
| |
| #define | BTB_TIMER_DISABLE 0x40 |
| |
| #define | CTEST1_REG 0x15 |
| |
| #define | CTEST2_REG 0x16 |
| |
| #define | CTEST3_REG 0x17 |
| |
| #define | CTEST4_REG 0x18 |
| |
| #define | DISABLE_FIFO 0x00 |
| |
| #define | SLBE 0x10 |
| |
| #define | SFWR 0x08 |
| |
| #define | BYTE_LANE0 0x04 |
| |
| #define | BYTE_LANE1 0x05 |
| |
| #define | BYTE_LANE2 0x06 |
| |
| #define | BYTE_LANE3 0x07 |
| |
| #define | SCSI_ZMODE 0x20 |
| |
| #define | ZMODE 0x40 |
| |
| #define | CTEST5_REG 0x19 |
| |
| #define | MASTER_CONTROL 0x10 |
| |
| #define | DMA_DIRECTION 0x08 |
| |
| #define | CTEST7_REG 0x1B |
| |
| #define | BURST_DISABLE 0x80 /* 710 only */ |
| |
| #define | SEL_TIMEOUT_DISABLE 0x10 /* 710 only */ |
| |
| #define | DFP 0x08 |
| |
| #define | EVP 0x04 |
| |
| #define | CTEST7_TT1 0x02 |
| |
| #define | DIFF 0x01 |
| |
| #define | CTEST6_REG 0x1A |
| |
| #define | TEMP_REG 0x1C |
| |
| #define | DFIFO_REG 0x20 |
| |
| #define | FLUSH_DMA_FIFO 0x80 |
| |
| #define | CLR_FIFO 0x40 |
| |
| #define | ISTAT_REG 0x21 |
| |
| #define | ABORT_OPERATION 0x80 |
| |
| #define | SOFTWARE_RESET_710 0x40 |
| |
| #define | DMA_INT_PENDING 0x01 |
| |
| #define | SCSI_INT_PENDING 0x02 |
| |
| #define | CONNECTED 0x08 |
| |
| #define | CTEST8_REG 0x22 |
| |
| #define | LAST_DIS_ENBL 0x01 |
| |
| #define | SHORTEN_FILTERING 0x04 |
| |
| #define | ENABLE_ACTIVE_NEGATION 0x10 |
| |
| #define | GENERATE_RECEIVE_PARITY 0x20 |
| |
| #define | CLR_FIFO_710 0x04 |
| |
| #define | FLUSH_DMA_FIFO_710 0x08 |
| |
| #define | CTEST9_REG 0x23 |
| |
| #define | DBC_REG 0x24 |
| |
| #define | DCMD_REG 0x27 |
| |
| #define | DNAD_REG 0x28 |
| |
| #define | DIEN_REG 0x39 |
| |
| #define | BUS_FAULT 0x20 |
| |
| #define | ABORT_INT 0x10 |
| |
| #define | INT_INST_INT 0x04 |
| |
| #define | WD_INT 0x02 |
| |
| #define | ILGL_INST_INT 0x01 |
| |
| #define | DCNTL_REG 0x3B |
| |
| #define | SOFTWARE_RESET 0x01 |
| |
| #define | COMPAT_700_MODE 0x01 |
| |
| #define | SCRPTS_16BITS 0x20 |
| |
| #define | EA_710 0x20 |
| |
| #define | ASYNC_DIV_2_0 0x00 |
| |
| #define | ASYNC_DIV_1_5 0x40 |
| |
| #define | ASYNC_DIV_1_0 0x80 |
| |
| #define | ASYNC_DIV_3_0 0xc0 |
| |
| #define | DMODE_710_REG 0x38 |
| |
| #define | DMODE_700_REG 0x34 |
| |
| #define | BURST_LENGTH_1 0x00 |
| |
| #define | BURST_LENGTH_2 0x40 |
| |
| #define | BURST_LENGTH_4 0x80 |
| |
| #define | BURST_LENGTH_8 0xC0 |
| |
| #define | DMODE_FC1 0x10 |
| |
| #define | DMODE_FC2 0x20 |
| |
| #define | BW16 32 |
| |
| #define | MODE_286 16 |
| |
| #define | IO_XFER 8 |
| |
| #define | FIXED_ADDR 4 |
| |
| #define | DSP_REG 0x2C |
| |
| #define | DSPS_REG 0x30 |
| |
| #define | NCR_700_MAX_OFFSET 8 |
| |
| #define | NCR_710_MAX_OFFSET 8 |
| |
| #define | NCR_700_MIN_XFERP 1 |
| |
| #define | NCR_710_MIN_XFERP 0 |
| |
| #define | NCR_700_MIN_PERIOD 25 /* for SDTR message, 100ns */ |
| |
| #define | script_patch_32(dev, script, symbol, value) |
| |
| #define | script_patch_32_abs(dev, script, symbol, value) |
| |
| #define | script_patch_ID(dev, script, symbol, value) |
| |
| #define | script_patch_16(dev, script, symbol, value) |
| |
1.8.2