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rf.c
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1 /*
2  * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
3  * All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation; either version 2 of the License, or
8  * (at your option) any later version.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
18  *
19  *
20  * File: rf.c
21  *
22  * Purpose: rf function code
23  *
24  * Author: Jerry Chen
25  *
26  * Date: Feb. 19, 2004
27  *
28  * Functions:
29  * IFRFbWriteEmbedded - Embedded write RF register via MAC
30  *
31  * Revision History:
32  *
33  */
34 
35 #include "mac.h"
36 #include "srom.h"
37 #include "rf.h"
38 #include "baseband.h"
39 
40 /*--------------------- Static Definitions -------------------------*/
41 
42 //static int msglevel =MSG_LEVEL_INFO;
43 
44 #define BY_AL2230_REG_LEN 23 //24bit
45 #define CB_AL2230_INIT_SEQ 15
46 #define SWITCH_CHANNEL_DELAY_AL2230 200 //us
47 #define AL2230_PWR_IDX_LEN 64
48 
49 
50 #define BY_AL7230_REG_LEN 23 //24bit
51 #define CB_AL7230_INIT_SEQ 16
52 #define SWITCH_CHANNEL_DELAY_AL7230 200 //us
53 #define AL7230_PWR_IDX_LEN 64
54 
55 /*--------------------- Static Classes ----------------------------*/
56 
57 /*--------------------- Static Variables --------------------------*/
58 
59 
60 
61 const unsigned long dwAL2230InitTable[CB_AL2230_INIT_SEQ] = {
62  0x03F79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
63  0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
64  0x01A00200+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
65  0x00FFF300+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
66  0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
67  0x0F4DC500+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
68  0x0805B600+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
69  0x0146C700+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
70  0x00068800+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
71  0x0403B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
72  0x00DBBA00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
73  0x00099B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, //
74  0x0BDFFC00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
75  0x00000D00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
76  0x00580F00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW
77  };
78 
79 const unsigned long dwAL2230ChannelTable0[CB_MAX_CHANNEL] = {
80  0x03F79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz
81  0x03F79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz
82  0x03E79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz
83  0x03E79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz
84  0x03F7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz
85  0x03F7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz
86  0x03E7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz
87  0x03E7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz
88  0x03F7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz
89  0x03F7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz
90  0x03E7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz
91  0x03E7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz
92  0x03F7C000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz
93  0x03E7C000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW // channel = 14, Tf = 2412M
94  };
95 
96 const unsigned long dwAL2230ChannelTable1[CB_MAX_CHANNEL] = {
97  0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz
98  0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz
99  0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz
100  0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz
101  0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz
102  0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz
103  0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz
104  0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz
105  0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz
106  0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz
107  0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz
108  0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz
109  0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz
110  0x06666100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW // channel = 14, Tf = 2412M
111  };
112 
113 unsigned long dwAL2230PowerTable[AL2230_PWR_IDX_LEN] = {
114  0x04040900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
115  0x04041900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
116  0x04042900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
117  0x04043900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
118  0x04044900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
119  0x04045900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
120  0x04046900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
121  0x04047900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
122  0x04048900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
123  0x04049900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
124  0x0404A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
125  0x0404B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
126  0x0404C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
127  0x0404D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
128  0x0404E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
129  0x0404F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
130  0x04050900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
131  0x04051900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
132  0x04052900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
133  0x04053900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
134  0x04054900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
135  0x04055900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
136  0x04056900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
137  0x04057900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
138  0x04058900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
139  0x04059900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
140  0x0405A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
141  0x0405B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
142  0x0405C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
143  0x0405D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
144  0x0405E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
145  0x0405F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
146  0x04060900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
147  0x04061900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
148  0x04062900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
149  0x04063900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
150  0x04064900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
151  0x04065900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
152  0x04066900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
153  0x04067900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
154  0x04068900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
155  0x04069900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
156  0x0406A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
157  0x0406B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
158  0x0406C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
159  0x0406D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
160  0x0406E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
161  0x0406F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
162  0x04070900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
163  0x04071900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
164  0x04072900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
165  0x04073900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
166  0x04074900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
167  0x04075900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
168  0x04076900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
169  0x04077900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
170  0x04078900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
171  0x04079900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
172  0x0407A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
173  0x0407B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
174  0x0407C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
175  0x0407D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
176  0x0407E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
177  0x0407F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW
178  };
179 
180 //{{ RobertYu:20050104
181 // 40MHz reference frequency
182 // Need to Pull PLLON(PE3) low when writing channel registers through 3-wire.
183 const unsigned long dwAL7230InitTable[CB_AL7230_INIT_SEQ] = {
184  0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Channel1 // Need modify for 11a
185  0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Channel1 // Need modify for 11a
186  0x841FF200+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 451FE2
187  0x3FDFA300+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 5FDFA3
188  0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // 11b/g // Need modify for 11a
189  //0x802B4500+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 8D1B45
190  // RoberYu:20050113, Rev0.47 Regsiter Setting Guide
191  0x802B5500+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 8D1B55
192  0x56AF3600+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
193  0xCE020700+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 860207
194  0x6EBC0800+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
195  0x221BB900+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
196  0xE0000A00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: E0600A
197  0x08031B00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10)
198  //0x00093C00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 00143C
199  // RoberYu:20050113, Rev0.47 Regsiter Setting Guide
200  0x000A3C00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 00143C
201  0xFFFFFD00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
202  0x00000E00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
203  0x1ABA8F00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // Need modify for 11a: 12BACF
204  };
205 
206 const unsigned long dwAL7230InitTableAMode[CB_AL7230_INIT_SEQ] = {
207  0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Channel184 // Need modify for 11b/g
208  0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Channel184 // Need modify for 11b/g
209  0x451FE200+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g
210  0x5FDFA300+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g
211  0x67F78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // 11a // Need modify for 11b/g
212  0x853F5500+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g, RoberYu:20050113
213  0x56AF3600+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
214  0xCE020700+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g
215  0x6EBC0800+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
216  0x221BB900+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
217  0xE0600A00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g
218  0x08031B00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10)
219  0x00147C00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g
220  0xFFFFFD00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
221  0x00000E00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW,
222  0x12BACF00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // Need modify for 11b/g
223  };
224 
225 
226 const unsigned long dwAL7230ChannelTable0[CB_MAX_CHANNEL] = {
227  0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz
228  0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz
229  0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz
230  0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz
231  0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz
232  0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz
233  0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz
234  0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz //RobertYu: 20050218, update for APNode 0.49
235  0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz //RobertYu: 20050218, update for APNode 0.49
236  0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz //RobertYu: 20050218, update for APNode 0.49
237  0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz //RobertYu: 20050218, update for APNode 0.49
238  0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz //RobertYu: 20050218, update for APNode 0.49
239  0x0037C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz //RobertYu: 20050218, update for APNode 0.49
240  0x0037C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 14, Tf = 2484MHz
241 
242  // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22)
243  0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 183, Tf = 4915MHz (15)
244  0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 184, Tf = 4920MHz (16)
245  0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 185, Tf = 4925MHz (17)
246  0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 187, Tf = 4935MHz (18)
247  0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 188, Tf = 4940MHz (19)
248  0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 189, Tf = 4945MHz (20)
249  0x0FF53000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 192, Tf = 4960MHz (21)
250  0x0FF53000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 196, Tf = 4980MHz (22)
251 
252  // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
253  // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56)
254 
255  0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 5035MHz (23)
256  0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 5040MHz (24)
257  0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 5045MHz (25)
258  0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 5055MHz (26)
259  0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 5060MHz (27)
260  0x0FF55000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 16, Tf = 5080MHz (28)
261  0x0FF56000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 34, Tf = 5170MHz (29)
262  0x0FF56000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 36, Tf = 5180MHz (30)
263  0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 38, Tf = 5190MHz (31) //RobertYu: 20050218, update for APNode 0.49
264  0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 40, Tf = 5200MHz (32)
265  0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 42, Tf = 5210MHz (33)
266  0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 44, Tf = 5220MHz (34)
267  0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 46, Tf = 5230MHz (35)
268  0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 48, Tf = 5240MHz (36)
269  0x0FF58000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 52, Tf = 5260MHz (37)
270  0x0FF58000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 56, Tf = 5280MHz (38)
271  0x0FF58000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 60, Tf = 5300MHz (39)
272  0x0FF59000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 64, Tf = 5320MHz (40)
273 
274  0x0FF5C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 100, Tf = 5500MHz (41)
275  0x0FF5C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 104, Tf = 5520MHz (42)
276  0x0FF5C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 108, Tf = 5540MHz (43)
277  0x0FF5D000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 112, Tf = 5560MHz (44)
278  0x0FF5D000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 116, Tf = 5580MHz (45)
279  0x0FF5D000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 120, Tf = 5600MHz (46)
280  0x0FF5E000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 124, Tf = 5620MHz (47)
281  0x0FF5E000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 128, Tf = 5640MHz (48)
282  0x0FF5E000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 132, Tf = 5660MHz (49)
283  0x0FF5F000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 136, Tf = 5680MHz (50)
284  0x0FF5F000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 140, Tf = 5700MHz (51)
285  0x0FF60000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 149, Tf = 5745MHz (52)
286  0x0FF60000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 153, Tf = 5765MHz (53)
287  0x0FF60000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 157, Tf = 5785MHz (54)
288  0x0FF61000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 161, Tf = 5805MHz (55)
289  0x0FF61000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // channel = 165, Tf = 5825MHz (56)
290  };
291 
292 const unsigned long dwAL7230ChannelTable1[CB_MAX_CHANNEL] = {
293  0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz
294  0x1B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz
295  0x03333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz
296  0x0B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz
297  0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz
298  0x1B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz
299  0x03333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz
300  0x0B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz
301  0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz
302  0x1B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz
303  0x03333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz
304  0x0B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz
305  0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz
306  0x06666100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 14, Tf = 2484MHz
307 
308  // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22)
309  0x1D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 183, Tf = 4915MHz (15)
310  0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 184, Tf = 4920MHz (16)
311  0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 185, Tf = 4925MHz (17)
312  0x08000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 187, Tf = 4935MHz (18)
313  0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 188, Tf = 4940MHz (19)
314  0x0D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 189, Tf = 4945MHz (20)
315  0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 192, Tf = 4960MHz (21)
316  0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 196, Tf = 4980MHz (22)
317 
318  // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
319  // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56)
320  0x1D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 5035MHz (23)
321  0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 5040MHz (24)
322  0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 5045MHz (25)
323  0x08000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 5055MHz (26)
324  0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 5060MHz (27)
325  0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 16, Tf = 5080MHz (28)
326  0x05555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 34, Tf = 5170MHz (29)
327  0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 36, Tf = 5180MHz (30)
328  0x10000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 38, Tf = 5190MHz (31)
329  0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 40, Tf = 5200MHz (32)
330  0x1AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 42, Tf = 5210MHz (33)
331  0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 44, Tf = 5220MHz (34)
332  0x05555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 46, Tf = 5230MHz (35)
333  0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 48, Tf = 5240MHz (36)
334  0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 52, Tf = 5260MHz (37)
335  0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 56, Tf = 5280MHz (38)
336  0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 60, Tf = 5300MHz (39)
337  0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 64, Tf = 5320MHz (40)
338  0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 100, Tf = 5500MHz (41)
339  0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 104, Tf = 5520MHz (42)
340  0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 108, Tf = 5540MHz (43)
341  0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 112, Tf = 5560MHz (44)
342  0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 116, Tf = 5580MHz (45)
343  0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 120, Tf = 5600MHz (46)
344  0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 124, Tf = 5620MHz (47)
345  0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 128, Tf = 5640MHz (48)
346  0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 132, Tf = 5660MHz (49)
347  0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 136, Tf = 5680MHz (50)
348  0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 140, Tf = 5700MHz (51)
349  0x18000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 149, Tf = 5745MHz (52)
350  0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 153, Tf = 5765MHz (53)
351  0x0D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 157, Tf = 5785MHz (54)
352  0x18000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 161, Tf = 5805MHz (55)
353  0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // channel = 165, Tf = 5825MHz (56)
354  };
355 
356 const unsigned long dwAL7230ChannelTable2[CB_MAX_CHANNEL] = {
357  0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz
358  0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz
359  0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz
360  0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz
361  0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz
362  0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz
363  0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz
364  0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz
365  0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz
366  0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz
367  0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz
368  0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz
369  0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz
370  0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 14, Tf = 2484MHz
371 
372  // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22)
373  0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 183, Tf = 4915MHz (15)
374  0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 184, Tf = 4920MHz (16)
375  0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 185, Tf = 4925MHz (17)
376  0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 187, Tf = 4935MHz (18)
377  0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 188, Tf = 4940MHz (19)
378  0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 189, Tf = 4945MHz (20)
379  0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 192, Tf = 4960MHz (21)
380  0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 196, Tf = 4980MHz (22)
381 
382  // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
383  // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56)
384  0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 5035MHz (23)
385  0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 5040MHz (24)
386  0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 5045MHz (25)
387  0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 5055MHz (26)
388  0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 5060MHz (27)
389  0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 16, Tf = 5080MHz (28)
390  0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 34, Tf = 5170MHz (29)
391  0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 36, Tf = 5180MHz (30)
392  0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 38, Tf = 5190MHz (31)
393  0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 40, Tf = 5200MHz (32)
394  0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 42, Tf = 5210MHz (33)
395  0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 44, Tf = 5220MHz (34)
396  0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 46, Tf = 5230MHz (35)
397  0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 48, Tf = 5240MHz (36)
398  0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 52, Tf = 5260MHz (37)
399  0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 56, Tf = 5280MHz (38)
400  0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 60, Tf = 5300MHz (39)
401  0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 64, Tf = 5320MHz (40)
402  0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 100, Tf = 5500MHz (41)
403  0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 104, Tf = 5520MHz (42)
404  0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 108, Tf = 5540MHz (43)
405  0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 112, Tf = 5560MHz (44)
406  0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 116, Tf = 5580MHz (45)
407  0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 120, Tf = 5600MHz (46)
408  0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 124, Tf = 5620MHz (47)
409  0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 128, Tf = 5640MHz (48)
410  0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 132, Tf = 5660MHz (49)
411  0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 136, Tf = 5680MHz (50)
412  0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 140, Tf = 5700MHz (51)
413  0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 149, Tf = 5745MHz (52)
414  0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 153, Tf = 5765MHz (53)
415  0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 157, Tf = 5785MHz (54)
416  0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 161, Tf = 5805MHz (55)
417  0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // channel = 165, Tf = 5825MHz (56)
418  };
419 //}} RobertYu
420 
421 
422 
423 
424 /*--------------------- Static Functions --------------------------*/
425 
426 
427 
428 
429 /*
430  * Description: AIROHA IFRF chip init function
431  *
432  * Parameters:
433  * In:
434  * dwIoBase - I/O base address
435  * Out:
436  * none
437  *
438  * Return Value: true if succeeded; false if failed.
439  *
440  */
441 bool s_bAL7230Init (unsigned long dwIoBase)
442 {
443  int ii;
444  bool bResult;
445 
446  bResult = true;
447 
448  //3-wire control for normal mode
449  VNSvOutPortB(dwIoBase + MAC_REG_SOFTPWRCTL, 0);
450 
451  MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPECTI |
452  SOFTPWRCTL_TXPEINV));
453  BBvPowerSaveModeOFF(dwIoBase); //RobertYu:20050106, have DC value for Calibration
454 
455  for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++)
456  bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[ii]);
457 
458  // PLL On
459  MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);
460 
461  //Calibration
462  MACvTimer0MicroSDelay(dwIoBase, 150);//150us
463  bResult &= IFRFbWriteEmbedded(dwIoBase, (0x9ABA8F00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW)); //TXDCOC:active, RCK:disable
464  MACvTimer0MicroSDelay(dwIoBase, 30);//30us
465  bResult &= IFRFbWriteEmbedded(dwIoBase, (0x3ABA8F00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW)); //TXDCOC:disable, RCK:active
466  MACvTimer0MicroSDelay(dwIoBase, 30);//30us
467  bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[CB_AL7230_INIT_SEQ-1]); //TXDCOC:disable, RCK:disable
468 
469  MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3 |
470  SOFTPWRCTL_SWPE2 |
471  SOFTPWRCTL_SWPECTI |
472  SOFTPWRCTL_TXPEINV));
473 
474  BBvPowerSaveModeON(dwIoBase); // RobertYu:20050106
475 
476  // PE1: TX_ON, PE2: RX_ON, PE3: PLLON
477  //3-wire control for power saving mode
478  VNSvOutPortB(dwIoBase + MAC_REG_PSPWRSIG, (PSSIG_WPE3 | PSSIG_WPE2)); //1100 0000
479 
480  return bResult;
481 }
482 
483 // Need to Pull PLLON low when writing channel registers through 3-wire interface
484 bool s_bAL7230SelectChannel (unsigned long dwIoBase, unsigned char byChannel)
485 {
486  bool bResult;
487 
488  bResult = true;
489 
490  // PLLON Off
491  MACvWordRegBitsOff(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);
492 
493  bResult &= IFRFbWriteEmbedded (dwIoBase, dwAL7230ChannelTable0[byChannel-1]); //Reg0
494  bResult &= IFRFbWriteEmbedded (dwIoBase, dwAL7230ChannelTable1[byChannel-1]); //Reg1
495  bResult &= IFRFbWriteEmbedded (dwIoBase, dwAL7230ChannelTable2[byChannel-1]); //Reg4
496 
497  // PLLOn On
498  MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);
499 
500  // Set Channel[7] = 0 to tell H/W channel is changing now.
501  VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel & 0x7F));
502  MACvTimer0MicroSDelay(dwIoBase, SWITCH_CHANNEL_DELAY_AL7230);
503  // Set Channel[7] = 1 to tell H/W channel change is done.
504  VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel | 0x80));
505 
506  return bResult;
507 }
508 
509 /*
510  * Description: Select channel with UW2452 chip
511  *
512  * Parameters:
513  * In:
514  * dwIoBase - I/O base address
515  * uChannel - Channel number
516  * Out:
517  * none
518  *
519  * Return Value: true if succeeded; false if failed.
520  *
521  */
522 
523 
524 //{{ RobertYu: 20041210
525 /*
526  * Description: UW2452 IFRF chip init function
527  *
528  * Parameters:
529  * In:
530  * dwIoBase - I/O base address
531  * Out:
532  * none
533  *
534  * Return Value: true if succeeded; false if failed.
535  *
536  */
537 
538 
539 
540 //}} RobertYu
542 
543 /*
544  * Description: VT3226 IFRF chip init function
545  *
546  * Parameters:
547  * In:
548  * dwIoBase - I/O base address
549  * Out:
550  * none
551  *
552  * Return Value: true if succeeded; false if failed.
553  *
554  */
555 
556 /*
557  * Description: Select channel with VT3226 chip
558  *
559  * Parameters:
560  * In:
561  * dwIoBase - I/O base address
562  * uChannel - Channel number
563  * Out:
564  * none
565  *
566  * Return Value: true if succeeded; false if failed.
567  *
568  */
569 
570 
571 
572 /*--------------------- Export Variables --------------------------*/
573 
574 /*--------------------- Export Functions --------------------------*/
575 
576 /*
577  * Description: Write to IF/RF, by embedded programming
578  *
579  * Parameters:
580  * In:
581  * dwIoBase - I/O base address
582  * dwData - data to write
583  * Out:
584  * none
585  *
586  * Return Value: true if succeeded; false if failed.
587  *
588  */
589 bool IFRFbWriteEmbedded (unsigned long dwIoBase, unsigned long dwData)
590 {
591  unsigned short ww;
592  unsigned long dwValue;
593 
594  VNSvOutPortD(dwIoBase + MAC_REG_IFREGCTL, dwData);
595 
596  // W_MAX_TIMEOUT is the timeout period
597  for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
598  VNSvInPortD(dwIoBase + MAC_REG_IFREGCTL, &dwValue);
599  if (dwValue & IFREGCTL_DONE)
600  break;
601  }
602 
603  if (ww == W_MAX_TIMEOUT) {
604 // DBG_PORT80_ALWAYS(0x32);
605  return false;
606  }
607  return true;
608 }
609 
610 
611 
612 /*
613  * Description: RFMD RF2959 IFRF chip init function
614  *
615  * Parameters:
616  * In:
617  * dwIoBase - I/O base address
618  * Out:
619  * none
620  *
621  * Return Value: true if succeeded; false if failed.
622  *
623  */
624 
625 /*
626  * Description: Select channel with RFMD 2959 chip
627  *
628  * Parameters:
629  * In:
630  * dwIoBase - I/O base address
631  * uChannel - Channel number
632  * Out:
633  * none
634  *
635  * Return Value: true if succeeded; false if failed.
636  *
637  */
638 
639 /*
640  * Description: AIROHA IFRF chip init function
641  *
642  * Parameters:
643  * In:
644  * dwIoBase - I/O base address
645  * Out:
646  * none
647  *
648  * Return Value: true if succeeded; false if failed.
649  *
650  */
651 bool RFbAL2230Init (unsigned long dwIoBase)
652 {
653  int ii;
654  bool bResult;
655 
656  bResult = true;
657 
658  //3-wire control for normal mode
659  VNSvOutPortB(dwIoBase + MAC_REG_SOFTPWRCTL, 0);
660 
661  MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPECTI |
662  SOFTPWRCTL_TXPEINV));
663 //2008-8-21 chester <add>
664  // PLL Off
665 
666  MACvWordRegBitsOff(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);
667 
668 
669 
670  //patch abnormal AL2230 frequency output
671 //2008-8-21 chester <add>
672  IFRFbWriteEmbedded(dwIoBase, (0x07168700+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW));
673 
674 
675  for (ii = 0; ii < CB_AL2230_INIT_SEQ; ii++)
676  bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL2230InitTable[ii]);
677 //2008-8-21 chester <add>
678 MACvTimer0MicroSDelay(dwIoBase, 30); //delay 30 us
679 
680  // PLL On
681  MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);
682 
683  MACvTimer0MicroSDelay(dwIoBase, 150);//150us
684  bResult &= IFRFbWriteEmbedded(dwIoBase, (0x00d80f00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW));
685  MACvTimer0MicroSDelay(dwIoBase, 30);//30us
686  bResult &= IFRFbWriteEmbedded(dwIoBase, (0x00780f00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW));
687  MACvTimer0MicroSDelay(dwIoBase, 30);//30us
688  bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL2230InitTable[CB_AL2230_INIT_SEQ-1]);
689 
690  MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3 |
691  SOFTPWRCTL_SWPE2 |
692  SOFTPWRCTL_SWPECTI |
693  SOFTPWRCTL_TXPEINV));
694 
695  //3-wire control for power saving mode
696  VNSvOutPortB(dwIoBase + MAC_REG_PSPWRSIG, (PSSIG_WPE3 | PSSIG_WPE2)); //1100 0000
697 
698  return bResult;
699 }
700 
701 bool RFbAL2230SelectChannel (unsigned long dwIoBase, unsigned char byChannel)
702 {
703  bool bResult;
704 
705  bResult = true;
706 
707  bResult &= IFRFbWriteEmbedded (dwIoBase, dwAL2230ChannelTable0[byChannel-1]);
708  bResult &= IFRFbWriteEmbedded (dwIoBase, dwAL2230ChannelTable1[byChannel-1]);
709 
710  // Set Channel[7] = 0 to tell H/W channel is changing now.
711  VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel & 0x7F));
712  MACvTimer0MicroSDelay(dwIoBase, SWITCH_CHANNEL_DELAY_AL2230);
713  // Set Channel[7] = 1 to tell H/W channel change is done.
714  VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel | 0x80));
715 
716  return bResult;
717 }
718 
719 /*
720  * Description: UW2451 IFRF chip init function
721  *
722  * Parameters:
723  * In:
724  * dwIoBase - I/O base address
725  * Out:
726  * none
727  *
728  * Return Value: true if succeeded; false if failed.
729  *
730  */
731 
732 
733 /*
734  * Description: Select channel with UW2451 chip
735  *
736  * Parameters:
737  * In:
738  * dwIoBase - I/O base address
739  * uChannel - Channel number
740  * Out:
741  * none
742  *
743  * Return Value: true if succeeded; false if failed.
744  *
745  */
746 
747 /*
748  * Description: Set sleep mode to UW2451 chip
749  *
750  * Parameters:
751  * In:
752  * dwIoBase - I/O base address
753  * uChannel - Channel number
754  * Out:
755  * none
756  *
757  * Return Value: true if succeeded; false if failed.
758  *
759  */
760 
761 /*
762  * Description: RF init function
763  *
764  * Parameters:
765  * In:
766  * byBBType
767  * byRFType
768  * Out:
769  * none
770  *
771  * Return Value: true if succeeded; false if failed.
772  *
773  */
774 bool RFbInit (
775  PSDevice pDevice
776  )
777 {
778 bool bResult = true;
779  switch (pDevice->byRFType) {
780  case RF_AIROHA :
781  case RF_AL2230S:
782  pDevice->byMaxPwrLevel = AL2230_PWR_IDX_LEN;
783  bResult = RFbAL2230Init(pDevice->PortOffset);
784  break;
785  case RF_AIROHA7230 :
786  pDevice->byMaxPwrLevel = AL7230_PWR_IDX_LEN;
787  bResult = s_bAL7230Init(pDevice->PortOffset);
788  break;
789  case RF_NOTHING :
790  bResult = true;
791  break;
792  default :
793  bResult = false;
794  break;
795  }
796  return bResult;
797 }
798 
799 /*
800  * Description: RF ShutDown function
801  *
802  * Parameters:
803  * In:
804  * byBBType
805  * byRFType
806  * Out:
807  * none
808  *
809  * Return Value: true if succeeded; false if failed.
810  *
811  */
812 bool RFbShutDown (
813  PSDevice pDevice
814  )
815 {
816 bool bResult = true;
817 
818  switch (pDevice->byRFType) {
819  case RF_AIROHA7230 :
820  bResult = IFRFbWriteEmbedded (pDevice->PortOffset, 0x1ABAEF00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW);
821  break;
822  default :
823  bResult = true;
824  break;
825  }
826  return bResult;
827 }
828 
829 /*
830  * Description: Select channel
831  *
832  * Parameters:
833  * In:
834  * byRFType
835  * byChannel - Channel number
836  * Out:
837  * none
838  *
839  * Return Value: true if succeeded; false if failed.
840  *
841  */
842 bool RFbSelectChannel (unsigned long dwIoBase, unsigned char byRFType, unsigned char byChannel)
843 {
844 bool bResult = true;
845  switch (byRFType) {
846 
847  case RF_AIROHA :
848  case RF_AL2230S:
849  bResult = RFbAL2230SelectChannel(dwIoBase, byChannel);
850  break;
851  //{{ RobertYu: 20050104
852  case RF_AIROHA7230 :
853  bResult = s_bAL7230SelectChannel(dwIoBase, byChannel);
854  break;
855  //}} RobertYu
856  case RF_NOTHING :
857  bResult = true;
858  break;
859  default:
860  bResult = false;
861  break;
862  }
863  return bResult;
864 }
865 
866 /*
867  * Description: Write WakeProgSyn
868  *
869  * Parameters:
870  * In:
871  * dwIoBase - I/O base address
872  * uChannel - channel number
873  * bySleepCnt - SleepProgSyn count
874  *
875  * Return Value: None.
876  *
877  */
878 bool RFvWriteWakeProgSyn (unsigned long dwIoBase, unsigned char byRFType, unsigned int uChannel)
879 {
880  int ii;
881  unsigned char byInitCount = 0;
882  unsigned char bySleepCount = 0;
883 
884  VNSvOutPortW(dwIoBase + MAC_REG_MISCFFNDEX, 0);
885  switch (byRFType) {
886  case RF_AIROHA:
887  case RF_AL2230S:
888 
889  if (uChannel > CB_MAX_CHANNEL_24G)
890  return false;
891 
892  byInitCount = CB_AL2230_INIT_SEQ + 2; // Init Reg + Channel Reg (2)
893  bySleepCount = 0;
894  if (byInitCount > (MISCFIFO_SYNDATASIZE - bySleepCount)) {
895  return false;
896  }
897 
898  for (ii = 0; ii < CB_AL2230_INIT_SEQ; ii++ ) {
899  MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230InitTable[ii]);
900  }
901  MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230ChannelTable0[uChannel-1]);
902  ii ++;
903  MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230ChannelTable1[uChannel-1]);
904  break;
905 
906  //{{ RobertYu: 20050104
907  // Need to check, PLLON need to be low for channel setting
908  case RF_AIROHA7230:
909  byInitCount = CB_AL7230_INIT_SEQ + 3; // Init Reg + Channel Reg (3)
910  bySleepCount = 0;
911  if (byInitCount > (MISCFIFO_SYNDATASIZE - bySleepCount)) {
912  return false;
913  }
914 
915  if (uChannel <= CB_MAX_CHANNEL_24G)
916  {
917  for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++ ) {
918  MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230InitTable[ii]);
919  }
920  }
921  else
922  {
923  for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++ ) {
924  MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230InitTableAMode[ii]);
925  }
926  }
927 
928  MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable0[uChannel-1]);
929  ii ++;
930  MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable1[uChannel-1]);
931  ii ++;
932  MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable2[uChannel-1]);
933  break;
934  //}} RobertYu
935 
936  case RF_NOTHING :
937  return true;
938  break;
939 
940  default:
941  return false;
942  break;
943  }
944 
945  MACvSetMISCFifo(dwIoBase, MISCFIFO_SYNINFO_IDX, (unsigned long )MAKEWORD(bySleepCount, byInitCount));
946 
947  return true;
948 }
949 
950 /*
951  * Description: Set Tx power
952  *
953  * Parameters:
954  * In:
955  * dwIoBase - I/O base address
956  * dwRFPowerTable - RF Tx Power Setting
957  * Out:
958  * none
959  *
960  * Return Value: true if succeeded; false if failed.
961  *
962  */
963 bool RFbSetPower (
964  PSDevice pDevice,
965  unsigned int uRATE,
966  unsigned int uCH
967  )
968 {
969 bool bResult = true;
970 unsigned char byPwr = 0;
971 unsigned char byDec = 0;
972 unsigned char byPwrdBm = 0;
973 
974  if (pDevice->dwDiagRefCount != 0) {
975  return true;
976  }
977  if ((uCH < 1) || (uCH > CB_MAX_CHANNEL)) {
978  return false;
979  }
980 
981  switch (uRATE) {
982  case RATE_1M:
983  case RATE_2M:
984  case RATE_5M:
985  case RATE_11M:
986  byPwr = pDevice->abyCCKPwrTbl[uCH];
987  byPwrdBm = pDevice->abyCCKDefaultPwr[uCH];
988 //PLICE_DEBUG->
989  //byPwr+=5;
990 //PLICE_DEBUG <-
991 
992 //printk("Rate <11:byPwr is %d\n",byPwr);
993  break;
994  case RATE_6M:
995  case RATE_9M:
996  case RATE_18M:
997  byPwr = pDevice->abyOFDMPwrTbl[uCH];
998  if (pDevice->byRFType == RF_UW2452) {
999  byDec = byPwr + 14;
1000  } else {
1001  byDec = byPwr + 10;
1002  }
1003  if (byDec >= pDevice->byMaxPwrLevel) {
1004  byDec = pDevice->byMaxPwrLevel-1;
1005  }
1006  if (pDevice->byRFType == RF_UW2452) {
1007  byPwrdBm = byDec - byPwr;
1008  byPwrdBm /= 3;
1009  } else {
1010  byPwrdBm = byDec - byPwr;
1011  byPwrdBm >>= 1;
1012  }
1013  byPwrdBm += pDevice->abyOFDMDefaultPwr[uCH];
1014  byPwr = byDec;
1015 //PLICE_DEBUG->
1016  //byPwr+=5;
1017 //PLICE_DEBUG<-
1018 
1019 //printk("Rate <24:byPwr is %d\n",byPwr);
1020  break;
1021  case RATE_24M:
1022  case RATE_36M:
1023  case RATE_48M:
1024  case RATE_54M:
1025  byPwr = pDevice->abyOFDMPwrTbl[uCH];
1026  byPwrdBm = pDevice->abyOFDMDefaultPwr[uCH];
1027 //PLICE_DEBUG->
1028  //byPwr+=5;
1029 //PLICE_DEBUG<-
1030 //printk("Rate < 54:byPwr is %d\n",byPwr);
1031  break;
1032  }
1033 
1034 // if (pDevice->byLocalID <= REV_ID_VT3253_B1) {
1035  if (pDevice->byCurPwr == byPwr) {
1036  return true;
1037  }
1038  bResult = RFbRawSetPower(pDevice, byPwr, uRATE);
1039 // }
1040  if (bResult == true) {
1041  pDevice->byCurPwr = byPwr;
1042  }
1043  return bResult;
1044 }
1045 
1046 /*
1047  * Description: Set Tx power
1048  *
1049  * Parameters:
1050  * In:
1051  * dwIoBase - I/O base address
1052  * dwRFPowerTable - RF Tx Power Setting
1053  * Out:
1054  * none
1055  *
1056  * Return Value: true if succeeded; false if failed.
1057  *
1058  */
1059 
1060 bool RFbRawSetPower (
1061  PSDevice pDevice,
1062  unsigned char byPwr,
1063  unsigned int uRATE
1064  )
1065 {
1066 bool bResult = true;
1067 unsigned long dwMax7230Pwr = 0;
1068 
1069  if (byPwr >= pDevice->byMaxPwrLevel) {
1070  return (false);
1071  }
1072  switch (pDevice->byRFType) {
1073 
1074  case RF_AIROHA :
1075  bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, dwAL2230PowerTable[byPwr]);
1076  if (uRATE <= RATE_11M) {
1077  bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, 0x0001B400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
1078  } else {
1079  bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
1080  }
1081  break;
1082 
1083 
1084  case RF_AL2230S :
1085  bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, dwAL2230PowerTable[byPwr]);
1086  if (uRATE <= RATE_11M) {
1087  bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, 0x040C1400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
1088  bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, 0x00299B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
1089  }else {
1090  bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
1091  bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, 0x00099B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
1092  }
1093 
1094  break;
1095 
1096  case RF_AIROHA7230:
1097  // 0x080F1B00 for 3 wire control TxGain(D10) and 0x31 as TX Gain value
1098  dwMax7230Pwr = 0x080C0B00 | ( (byPwr) << 12 ) |
1099  (BY_AL7230_REG_LEN << 3 ) | IFREGCTL_REGW;
1100 
1101  bResult &= IFRFbWriteEmbedded(pDevice->PortOffset, dwMax7230Pwr);
1102  break;
1103 
1104 
1105  default :
1106  break;
1107  }
1108  return bResult;
1109 }
1110 
1111 /*+
1112  *
1113  * Routine Description:
1114  * Translate RSSI to dBm
1115  *
1116  * Parameters:
1117  * In:
1118  * pDevice - The adapter to be translated
1119  * byCurrRSSI - RSSI to be translated
1120  * Out:
1121  * pdwdbm - Translated dbm number
1122  *
1123  * Return Value: none
1124  *
1125 -*/
1126 void
1127 RFvRSSITodBm (
1128  PSDevice pDevice,
1129  unsigned char byCurrRSSI,
1130  long * pldBm
1131  )
1132 {
1133  unsigned char byIdx = (((byCurrRSSI & 0xC0) >> 6) & 0x03);
1134  long b = (byCurrRSSI & 0x3F);
1135  long a = 0;
1136  unsigned char abyAIROHARF[4] = {0, 18, 0, 40};
1137 
1138  switch (pDevice->byRFType) {
1139  case RF_AIROHA:
1140  case RF_AL2230S:
1141  case RF_AIROHA7230: //RobertYu: 20040104
1142  a = abyAIROHARF[byIdx];
1143  break;
1144  default:
1145  break;
1146  }
1147 
1148  *pldBm = -1 * (a + b * 2);
1149 }
1150 
1152 //{{ RobertYu: 20050104
1153 
1154 
1155 // Post processing for the 11b/g and 11a.
1156 // for save time on changing Reg2,3,5,7,10,12,15
1157 bool RFbAL7230SelectChannelPostProcess (unsigned long dwIoBase, unsigned char byOldChannel, unsigned char byNewChannel)
1158 {
1159  bool bResult;
1160 
1161  bResult = true;
1162 
1163  // if change between 11 b/g and 11a need to update the following register
1164  // Channel Index 1~14
1165 
1166  if( (byOldChannel <= CB_MAX_CHANNEL_24G) && (byNewChannel > CB_MAX_CHANNEL_24G) )
1167  {
1168  // Change from 2.4G to 5G
1169  bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTableAMode[2]); //Reg2
1170  bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTableAMode[3]); //Reg3
1171  bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTableAMode[5]); //Reg5
1172  bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTableAMode[7]); //Reg7
1173  bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTableAMode[10]);//Reg10
1174  bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTableAMode[12]);//Reg12
1175  bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTableAMode[15]);//Reg15
1176  }
1177  else if( (byOldChannel > CB_MAX_CHANNEL_24G) && (byNewChannel <= CB_MAX_CHANNEL_24G) )
1178  {
1179  // change from 5G to 2.4G
1180  bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[2]); //Reg2
1181  bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[3]); //Reg3
1182  bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[5]); //Reg5
1183  bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[7]); //Reg7
1184  bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[10]);//Reg10
1185  bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[12]);//Reg12
1186  bResult &= IFRFbWriteEmbedded(dwIoBase, dwAL7230InitTable[15]);//Reg15
1187  }
1188 
1189  return bResult;
1190 }
1191 
1192 
1193 //}} RobertYu
1195 
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