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arch
arm
plat-nomadik
include
plat
ste_dma40.h
Go to the documentation of this file.
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/*
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* Copyright (C) ST-Ericsson SA 2007-2010
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* Author: Per Forlin <
[email protected]
> for ST-Ericsson
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* Author: Jonas Aaberg <
[email protected]
> for ST-Ericsson
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* License terms: GNU General Public License (GPL) version 2
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*/
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#ifndef STE_DMA40_H
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#define STE_DMA40_H
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#include <
linux/dmaengine.h
>
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#include <
linux/scatterlist.h
>
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#include <
linux/workqueue.h
>
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#include <
linux/interrupt.h
>
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/*
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* Maxium size for a single dma descriptor
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* Size is limited to 16 bits.
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* Size is in the units of addr-widths (1,2,4,8 bytes)
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* Larger transfers will be split up to multiple linked desc
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*/
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#define STEDMA40_MAX_SEG_SIZE 0xFFFF
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/* dev types for memcpy */
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#define STEDMA40_DEV_DST_MEMORY (-1)
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#define STEDMA40_DEV_SRC_MEMORY (-1)
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enum
stedma40_mode
{
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STEDMA40_MODE_LOGICAL
= 0,
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STEDMA40_MODE_PHYSICAL
,
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STEDMA40_MODE_OPERATION
,
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};
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enum
stedma40_mode_opt
{
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STEDMA40_PCHAN_BASIC_MODE
= 0,
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STEDMA40_LCHAN_SRC_LOG_DST_LOG
= 0,
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STEDMA40_PCHAN_MODULO_MODE
,
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STEDMA40_PCHAN_DOUBLE_DST_MODE
,
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STEDMA40_LCHAN_SRC_PHY_DST_LOG
,
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STEDMA40_LCHAN_SRC_LOG_DST_PHY
,
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};
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#define STEDMA40_ESIZE_8_BIT 0x0
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#define STEDMA40_ESIZE_16_BIT 0x1
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#define STEDMA40_ESIZE_32_BIT 0x2
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#define STEDMA40_ESIZE_64_BIT 0x3
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/* The value 4 indicates that PEN-reg shall be set to 0 */
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#define STEDMA40_PSIZE_PHY_1 0x4
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#define STEDMA40_PSIZE_PHY_2 0x0
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#define STEDMA40_PSIZE_PHY_4 0x1
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#define STEDMA40_PSIZE_PHY_8 0x2
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#define STEDMA40_PSIZE_PHY_16 0x3
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/*
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* The number of elements differ in logical and
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* physical mode
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*/
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#define STEDMA40_PSIZE_LOG_1 STEDMA40_PSIZE_PHY_2
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#define STEDMA40_PSIZE_LOG_4 STEDMA40_PSIZE_PHY_4
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#define STEDMA40_PSIZE_LOG_8 STEDMA40_PSIZE_PHY_8
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#define STEDMA40_PSIZE_LOG_16 STEDMA40_PSIZE_PHY_16
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/* Maximum number of possible physical channels */
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#define STEDMA40_MAX_PHYS 32
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enum
stedma40_flow_ctrl
{
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STEDMA40_NO_FLOW_CTRL
,
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STEDMA40_FLOW_CTRL
,
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};
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enum
stedma40_periph_data_width
{
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STEDMA40_BYTE_WIDTH
=
STEDMA40_ESIZE_8_BIT
,
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STEDMA40_HALFWORD_WIDTH
=
STEDMA40_ESIZE_16_BIT
,
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STEDMA40_WORD_WIDTH
=
STEDMA40_ESIZE_32_BIT
,
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STEDMA40_DOUBLEWORD_WIDTH
=
STEDMA40_ESIZE_64_BIT
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};
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enum
stedma40_xfer_dir
{
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STEDMA40_MEM_TO_MEM
= 1,
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STEDMA40_MEM_TO_PERIPH
,
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STEDMA40_PERIPH_TO_MEM
,
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STEDMA40_PERIPH_TO_PERIPH
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};
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struct
stedma40_half_channel_info
{
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bool
big_endian
;
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enum
stedma40_periph_data_width
data_width
;
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int
psize
;
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enum
stedma40_flow_ctrl
flow_ctrl
;
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};
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struct
stedma40_chan_cfg
{
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enum
stedma40_xfer_dir
dir
;
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bool
high_priority
;
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bool
realtime
;
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enum
stedma40_mode
mode
;
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enum
stedma40_mode_opt
mode_opt
;
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int
src_dev_type
;
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int
dst_dev_type
;
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struct
stedma40_half_channel_info
src_info
;
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struct
stedma40_half_channel_info
dst_info
;
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bool
use_fixed_channel
;
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int
phy_channel
;
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};
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struct
stedma40_platform_data
{
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u32
dev_len
;
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const
dma_addr_t
*
dev_tx
;
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const
dma_addr_t
*
dev_rx
;
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int
*
memcpy
;
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u32
memcpy_len
;
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struct
stedma40_chan_cfg
*
memcpy_conf_phy
;
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struct
stedma40_chan_cfg
*
memcpy_conf_log
;
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int
disabled_channels
[
STEDMA40_MAX_PHYS
];
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bool
use_esram_lcla
;
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};
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#ifdef CONFIG_STE_DMA40
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bool
stedma40_filter
(
struct
dma_chan
*
chan
,
void
*
data
);
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static
inline
struct
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dma_async_tx_descriptor
*stedma40_slave_mem(
struct
dma_chan
*
chan
,
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dma_addr_t
addr
,
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unsigned
int
size
,
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enum
dma_transfer_direction
direction
,
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unsigned
long
flags
)
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{
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struct
scatterlist
sg
;
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sg_init_table
(&
sg
, 1);
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sg
.dma_address =
addr
;
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sg
.length =
size
;
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return
dmaengine_prep_slave_sg(chan, &
sg
, 1, direction, flags);
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}
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#else
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static
inline
bool
stedma40_filter
(
struct
dma_chan
*
chan
,
void
*
data
)
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{
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return
false
;
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}
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static
inline
struct
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dma_async_tx_descriptor
*stedma40_slave_mem(
struct
dma_chan
*
chan
,
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dma_addr_t
addr
,
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unsigned
int
size
,
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enum
dma_transfer_direction
direction
,
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unsigned
long
flags
)
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{
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return
NULL
;
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}
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#endif
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#endif
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