| enum | {
CARM_MAX_PORTS = 8,
CARM_SHM_SIZE = (4096 << 7),
CARM_MINORS_PER_MAJOR = 256 / CARM_MAX_PORTS,
CARM_MAX_WAIT_Q = CARM_MAX_PORTS + 1,
CARM_MAX_REQ = 64,
CARM_MSG_LOW_WATER = (CARM_MAX_REQ / 4),
CARM_MAX_REQ_SG = 32,
CARM_MAX_HOST_SG = 600,
CARM_SG_LOW_WATER = (CARM_MAX_HOST_SG / 4),
CARM_IHQP = 0x1c,
CARM_INT_STAT = 0x10,
CARM_INT_MASK = 0x14,
CARM_HMUC = 0x18,
RBUF_ADDR_LO = 0x20,
RBUF_ADDR_HI = 0x24,
RBUF_BYTE_SZ = 0x28,
CARM_RESP_IDX = 0x2c,
CARM_CMS0 = 0x30,
CARM_LMUC = 0x48,
CARM_HMPHA = 0x6c,
CARM_INITC = 0xb5,
INT_RESERVED = 0xfffffff0,
INT_WATCHDOG = (1 << 3),
INT_Q_OVERFLOW = (1 << 2),
INT_Q_AVAILABLE = (1 << 1),
INT_RESPONSE = (1 << 0),
INT_ACK_MASK = INT_WATCHDOG | INT_Q_OVERFLOW,
INT_DEF_MASK,
CARM_HAVE_RESP = 0x01,
CARM_MSG_READ = 1,
CARM_MSG_WRITE = 2,
CARM_MSG_VERIFY = 3,
CARM_MSG_GET_CAPACITY = 4,
CARM_MSG_FLUSH = 5,
CARM_MSG_IOCTL = 6,
CARM_MSG_ARRAY = 8,
CARM_MSG_MISC = 9,
CARM_CME = (1 << 2),
CARM_RME = (1 << 1),
CARM_WZBC = (1 << 0),
CARM_RMI = (1 << 0),
CARM_Q_FULL = (1 << 3),
CARM_MSG_SIZE = 288,
CARM_Q_LEN = 48,
CARM_IOC_SCAN_CHAN = 5,
CARM_IOC_GET_TCQ = 13,
CARM_IOC_SET_TCQ = 14,
IOC_SCAN_CHAN_NODEV = 0x1f,
IOC_SCAN_CHAN_OFFSET = 0x40,
CARM_ARRAY_INFO = 0,
ARRAY_NO_EXIST = (1 << 31),
RMSG_SZ = 8,
RMSG_Q_LEN = 48,
RMSG_OK = 1,
RBUF_LEN = RMSG_SZ * RMSG_Q_LEN,
PDC_SHM_SIZE = (4096 << 7),
MISC_GET_FW_VER = 2,
MISC_ALLOC_MEM = 3,
MISC_SET_TIME = 5,
FW_VER_4PORT = (1 << 2),
FW_VER_NON_RAID = (1 << 1),
FW_VER_ZCR = (1 << 0),
FL_NON_RAID = FW_VER_NON_RAID,
FL_4PORT = FW_VER_4PORT,
FL_FW_VER_MASK = (FW_VER_NON_RAID | FW_VER_4PORT),
FL_DAC = (1 << 16),
FL_DYN_MAJOR = (1 << 17)
} |
1.8.2