#include <eeprom.h>

Data Fields
u16	ee_magic

u16	ee_protect

u16	ee_regdomain

u16	ee_version

u16	ee_header

u16	ee_ant_gain

u8	ee_rfkill_pin

bool	ee_rfkill_pol

bool	ee_is_hb63

bool	ee_serdes

u16	ee_misc0

u16	ee_misc1

u16	ee_misc2

u16	ee_misc3

u16	ee_misc4

u16	ee_misc5

u16	ee_misc6

u16	ee_cck_ofdm_gain_delta

u16	ee_cck_ofdm_power_delta

u16	ee_scaled_cck_delta

u16	ee_i_cal [AR5K_EEPROM_N_MODES]

u16	ee_q_cal [AR5K_EEPROM_N_MODES]

u16	ee_fixed_bias [AR5K_EEPROM_N_MODES]

u16	ee_turbo_max_power [AR5K_EEPROM_N_MODES]

u16	ee_xr_power [AR5K_EEPROM_N_MODES]

u16	ee_switch_settling [AR5K_EEPROM_N_MODES]

u16	ee_atn_tx_rx [AR5K_EEPROM_N_MODES]

u16	ee_ant_control [AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC]

u16	ee_ob [AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]

u16	ee_db [AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]

u16	ee_tx_end2xlna_enable [AR5K_EEPROM_N_MODES]

u16	ee_tx_end2xpa_disable [AR5K_EEPROM_N_MODES]

u16	ee_tx_frm2xpa_enable [AR5K_EEPROM_N_MODES]

u16	ee_thr_62 [AR5K_EEPROM_N_MODES]

u16	ee_xlna_gain [AR5K_EEPROM_N_MODES]

u16	ee_xpd [AR5K_EEPROM_N_MODES]

u16	ee_x_gain [AR5K_EEPROM_N_MODES]

u16	ee_i_gain [AR5K_EEPROM_N_MODES]

u16	ee_margin_tx_rx [AR5K_EEPROM_N_MODES]

u16	ee_switch_settling_turbo [AR5K_EEPROM_N_MODES]

u16	ee_margin_tx_rx_turbo [AR5K_EEPROM_N_MODES]

u16	ee_atn_tx_rx_turbo [AR5K_EEPROM_N_MODES]

u16	ee_false_detect [AR5K_EEPROM_N_MODES]

u8	ee_pd_gains [AR5K_EEPROM_N_MODES]

u8	ee_pdc_to_idx [AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PD_GAINS]

u8	ee_n_piers [AR5K_EEPROM_N_MODES]

struct ath5k_chan_pcal_info	ee_pwr_cal_a [AR5K_EEPROM_N_5GHZ_CHAN]

struct ath5k_chan_pcal_info	ee_pwr_cal_b [AR5K_EEPROM_N_2GHZ_CHAN_MAX]

struct ath5k_chan_pcal_info	ee_pwr_cal_g [AR5K_EEPROM_N_2GHZ_CHAN_MAX]

u8	ee_rate_target_pwr_num [AR5K_EEPROM_N_MODES]

struct ath5k_rate_pcal_info	ee_rate_tpwr_a [AR5K_EEPROM_N_5GHZ_CHAN]

struct ath5k_rate_pcal_info	ee_rate_tpwr_b [AR5K_EEPROM_N_2GHZ_CHAN_MAX]

struct ath5k_rate_pcal_info	ee_rate_tpwr_g [AR5K_EEPROM_N_2GHZ_CHAN_MAX]

u8	ee_ctls

u8	ee_ctl [AR5K_EEPROM_MAX_CTLS]

struct ath5k_edge_power	ee_ctl_pwr [AR5K_EEPROM_N_EDGES *AR5K_EEPROM_MAX_CTLS]

s16	ee_noise_floor_thr [AR5K_EEPROM_N_MODES]

s8	ee_adc_desired_size [AR5K_EEPROM_N_MODES]

s8	ee_pga_desired_size [AR5K_EEPROM_N_MODES]

s8	ee_adc_desired_size_turbo [AR5K_EEPROM_N_MODES]

s8	ee_pga_desired_size_turbo [AR5K_EEPROM_N_MODES]

s8	ee_pd_gain_overlap

u16	ee_spur_chans [AR5K_EEPROM_N_SPUR_CHANS][AR5K_EEPROM_N_FREQ_BANDS]

u32	ee_antenna [AR5K_EEPROM_N_MODES][AR5K_ANT_MAX]

Detailed Description

struct ath5k_eeprom_info - EEPROM calibration data

: ath/regd.c takes care of COUNTRY_ERD and WORLDWIDE_ROAMING flags : Antenna gain in 0.5dB steps signed [5211 only?] : difference in gainF to output the same power for OFDM and CCK packets : power difference between OFDM (6Mbps) and CCK (11Mbps) rate in G mode. 0.1dB steps : for Japan Channel 14: 0.1dB resolution

: Initial I coefficient to correct I/Q mismatch in the receive path : Initial Q coefficient to correct I/Q mismatch in the receive path : use ee_ob and ee_db settings or use automatic control : RX/TX Switch settling time : Difference in attenuation between TX and RX in 1dB steps : Antenna Control Settings : Bias current for Output stage of PA B/G mode: Index [0] is used for AR2112/5112, otherwise [1] A mode: [0] 5.15-5.25 [1] 5.25-5.50 [2] 5.50-5.70 [3] 5.70-5.85 GHz : Bias current for Output stage of PA. see : Time difference from when BB finishes sending a frame to when the external LNA is activated : Time difference from when BB finishes sending a frame to when the external PA switch is deactivated : Time difference from when MAC sends frame to when external PA switch is activated : Clear Channel Assessment (CCA) sensitivity (IEEE802.11a section 17.3.10.5 ) : Total gain of the LNA (information only) : Use external (1) or internal power detector : Gain for external power detector output (differences in EEMAP versions!) : Initial gain value after reset : Margin in dB when final attenuation stage should be used

: Backoff in Sensitivity (dB) on channels with spur signals : Noise floor threshold in 1dB steps : Desired amplitude for ADC, used by AGC; in 0.5 dB steps : Desired output of PGA (for BB gain) in 0.5 dB steps : PD ADC curves need to overlap in 0.5dB steps (ee_map>=2)

Definition at line 409 of file eeprom.h.