clk_pll Struct Reference

#include <clk.h>

Data Fields
struct clk_hw	hw
unsigned short	regofs
void __iomem *	reg
spinlock_t *	lock
int	type
void __iomem *	base
u8	power
unsigned long	rate
struct clk_vco *	vco
const char *	parent [1]

Detailed Description

struct clk_pll - mxs pll clock : clk_hw for the pll : base address of the pll : the shift of power bit : the clock rate of the pll

The mxs pll is a fixed rate clock with power and gate control, and the shift of gate bit is always 31.

Definition at line 64 of file clk-prima2.c.

Field Documentation

void __iomem* base

Definition at line 32 of file clk-pll.c.

struct clk_hw hw

Definition at line 65 of file clk-prima2.c.

spinlock_t * lock

Definition at line 48 of file clk-vt8500.c.

const char* parent[1]

Definition at line 105 of file clk.h.

u8 power

Definition at line 33 of file clk-pll.c.

unsigned long rate

Definition at line 34 of file clk-pll.c.

void __iomem* reg

Definition at line 47 of file clk-vt8500.c.

unsigned short regofs

Definition at line 66 of file clk-prima2.c.

int type

Definition at line 49 of file clk-vt8500.c.

struct clk_vco* vco

Definition at line 104 of file clk.h.

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The documentation for this struct was generated from the following files:

• drivers/clk/clk-prima2.c
• drivers/clk/clk-vt8500.c
• drivers/clk/mxs/clk-pll.c
• drivers/clk/spear/clk.h