pch_gbe_regs Struct Reference

#include <pch_gbe.h>

Data Fields
u32	INT_ST
u32	INT_EN
u32	MODE
u32	RESET
u32	TCPIP_ACC
u32	EX_LIST
u32	INT_ST_HOLD
u32	PHY_INT_CTRL
u32	MAC_RX_EN
u32	RX_FCTRL
u32	PAUSE_REQ
u32	RX_MODE
u32	TX_MODE
u32	RX_FIFO_ST
u32	TX_FIFO_ST
u32	TX_FID
u32	TX_RESULT
u32	PAUSE_PKT1
u32	PAUSE_PKT2
u32	PAUSE_PKT3
u32	PAUSE_PKT4
u32	PAUSE_PKT5
u32	reserve [2]
struct pch_gbe_regs_mac_adr	mac_adr [16]
u32	ADDR_MASK
u32	MIIM
u32	MAC_ADDR_LOAD
u32	RGMII_ST
u32	RGMII_CTRL
u32	reserve3 [3]
u32	DMA_CTRL
u32	reserve4 [3]
u32	RX_DSC_BASE
u32	RX_DSC_SIZE
u32	RX_DSC_HW_P
u32	RX_DSC_HW_P_HLD
u32	RX_DSC_SW_P
u32	reserve5 [3]
u32	TX_DSC_BASE
u32	TX_DSC_SIZE
u32	TX_DSC_HW_P
u32	TX_DSC_HW_P_HLD
u32	TX_DSC_SW_P
u32	reserve6 [3]
u32	RX_DMA_ST
u32	TX_DMA_ST
u32	reserve7 [2]
u32	WOL_ST
u32	WOL_CTRL
u32	WOL_ADDR_MASK

Detailed Description

pch_udc_regs - Structure holding values of MAC registers

Definition at line 49 of file pch_gbe.h.

Field Documentation

u32 ADDR_MASK

Definition at line 74 of file pch_gbe.h.

u32 DMA_CTRL

Definition at line 80 of file pch_gbe.h.

u32 EX_LIST

Definition at line 55 of file pch_gbe.h.

u32 INT_EN

Definition at line 51 of file pch_gbe.h.

u32 INT_ST

Definition at line 50 of file pch_gbe.h.

u32 INT_ST_HOLD

Definition at line 56 of file pch_gbe.h.

u32 MAC_ADDR_LOAD

Definition at line 76 of file pch_gbe.h.

struct pch_gbe_regs_mac_adr mac_adr[16]

Definition at line 73 of file pch_gbe.h.

u32 MAC_RX_EN

Definition at line 58 of file pch_gbe.h.

u32 MIIM

Definition at line 75 of file pch_gbe.h.

u32 MODE

Definition at line 52 of file pch_gbe.h.

u32 PAUSE_PKT1

Definition at line 67 of file pch_gbe.h.

u32 PAUSE_PKT2

Definition at line 68 of file pch_gbe.h.

u32 PAUSE_PKT3

Definition at line 69 of file pch_gbe.h.

u32 PAUSE_PKT4

Definition at line 70 of file pch_gbe.h.

u32 PAUSE_PKT5

Definition at line 71 of file pch_gbe.h.

u32 PAUSE_REQ

Definition at line 60 of file pch_gbe.h.

u32 PHY_INT_CTRL

Definition at line 57 of file pch_gbe.h.

u32 reserve[2]

Definition at line 72 of file pch_gbe.h.

u32 reserve3[3]

Definition at line 79 of file pch_gbe.h.

u32 reserve4[3]

Definition at line 81 of file pch_gbe.h.

u32 reserve5[3]

Definition at line 87 of file pch_gbe.h.

u32 reserve6[3]

Definition at line 93 of file pch_gbe.h.

u32 reserve7[2]

Definition at line 96 of file pch_gbe.h.

u32 RESET

Definition at line 53 of file pch_gbe.h.

u32 RGMII_CTRL

Definition at line 78 of file pch_gbe.h.

u32 RGMII_ST

Definition at line 77 of file pch_gbe.h.

u32 RX_DMA_ST

Definition at line 94 of file pch_gbe.h.

u32 RX_DSC_BASE

Definition at line 82 of file pch_gbe.h.

u32 RX_DSC_HW_P

Definition at line 84 of file pch_gbe.h.

u32 RX_DSC_HW_P_HLD

Definition at line 85 of file pch_gbe.h.

u32 RX_DSC_SIZE

Definition at line 83 of file pch_gbe.h.

u32 RX_DSC_SW_P

Definition at line 86 of file pch_gbe.h.

u32 RX_FCTRL

Definition at line 59 of file pch_gbe.h.

u32 RX_FIFO_ST

Definition at line 63 of file pch_gbe.h.

u32 RX_MODE

Definition at line 61 of file pch_gbe.h.

u32 TCPIP_ACC

Definition at line 54 of file pch_gbe.h.

u32 TX_DMA_ST

Definition at line 95 of file pch_gbe.h.

u32 TX_DSC_BASE

Definition at line 88 of file pch_gbe.h.

u32 TX_DSC_HW_P

Definition at line 90 of file pch_gbe.h.

u32 TX_DSC_HW_P_HLD

Definition at line 91 of file pch_gbe.h.

u32 TX_DSC_SIZE

Definition at line 89 of file pch_gbe.h.

u32 TX_DSC_SW_P

Definition at line 92 of file pch_gbe.h.

u32 TX_FID

Definition at line 65 of file pch_gbe.h.

u32 TX_FIFO_ST

Definition at line 64 of file pch_gbe.h.

u32 TX_MODE

Definition at line 62 of file pch_gbe.h.

u32 TX_RESULT

Definition at line 66 of file pch_gbe.h.

u32 WOL_ADDR_MASK

Definition at line 99 of file pch_gbe.h.

u32 WOL_CTRL

Definition at line 98 of file pch_gbe.h.

u32 WOL_ST

Definition at line 97 of file pch_gbe.h.

---

The documentation for this struct was generated from the following file:

• drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h