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nv50.c
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1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 
25 #include <subdev/device.h>
26 #include <subdev/bios.h>
27 #include <subdev/gpio.h>
28 #include <subdev/i2c.h>
29 #include <subdev/clock.h>
30 #include <subdev/therm.h>
31 #include <subdev/mxm.h>
32 #include <subdev/devinit.h>
33 #include <subdev/mc.h>
34 #include <subdev/timer.h>
35 #include <subdev/fb.h>
36 #include <subdev/instmem.h>
37 #include <subdev/vm.h>
38 #include <subdev/bar.h>
39 
40 #include <engine/dmaobj.h>
41 #include <engine/fifo.h>
42 #include <engine/software.h>
43 #include <engine/graph.h>
44 #include <engine/mpeg.h>
45 #include <engine/vp.h>
46 #include <engine/crypt.h>
47 #include <engine/bsp.h>
48 #include <engine/ppp.h>
49 #include <engine/copy.h>
50 #include <engine/disp.h>
51 
52 int
53 nv50_identify(struct nouveau_device *device)
54 {
55  switch (device->chipset) {
56  case 0x50:
57  device->cname = "G80";
58  device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
59  device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
60  device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
61  device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
62  device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
63  device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
64  device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
65  device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
66  device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
67  device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
68  device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
69  device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
70  device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
71  device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
72  device->oclass[NVDEV_ENGINE_FIFO ] = &nv50_fifo_oclass;
73  device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
74  device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
75  device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass;
76  device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
77  break;
78  case 0x84:
79  device->cname = "G84";
80  device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
81  device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
82  device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
83  device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
84  device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
85  device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
86  device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
87  device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
88  device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
89  device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
90  device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
91  device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
92  device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
93  device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
94  device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
95  device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
96  device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
97  device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
98  device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
99  device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
100  device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
101  device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
102  break;
103  case 0x86:
104  device->cname = "G86";
105  device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
106  device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
107  device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
108  device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
109  device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
110  device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
111  device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
112  device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
113  device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
114  device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
115  device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
116  device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
117  device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
118  device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
119  device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
120  device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
121  device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
122  device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
123  device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
124  device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
125  device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
126  device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
127  break;
128  case 0x92:
129  device->cname = "G92";
130  device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
131  device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
132  device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
133  device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
134  device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
135  device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
136  device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
137  device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
138  device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
139  device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
140  device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
141  device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
142  device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
143  device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
144  device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
145  device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
146  device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
147  device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
148  device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
149  device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
150  device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
151  device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
152  break;
153  case 0x94:
154  device->cname = "G94";
155  device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
156  device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
157  device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
158  device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
159  device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
160  device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
161  device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
162  device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
163  device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
164  device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
165  device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
166  device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
167  device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
168  device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
169  device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
170  device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
171  device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
172  device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
173  device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
174  device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
175  device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
176  device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
177  break;
178  case 0x96:
179  device->cname = "G96";
180  device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
181  device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
182  device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
183  device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
184  device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
185  device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
186  device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
187  device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
188  device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
189  device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
190  device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
191  device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
192  device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
193  device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
194  device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
195  device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
196  device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
197  device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
198  device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
199  device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
200  device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
201  device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
202  break;
203  case 0x98:
204  device->cname = "G98";
205  device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
206  device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
207  device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
208  device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
209  device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
210  device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
211  device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
212  device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
213  device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
214  device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
215  device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
216  device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
217  device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
218  device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
219  device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
220  device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
221  device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
222  device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
223  device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
224  device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
225  device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
226  device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
227  break;
228  case 0xa0:
229  device->cname = "G200";
230  device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
231  device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
232  device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
233  device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
234  device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
235  device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
236  device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
237  device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
238  device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
239  device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
240  device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
241  device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
242  device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
243  device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
244  device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
245  device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
246  device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
247  device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
248  device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
249  device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
250  device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
251  device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
252  break;
253  case 0xaa:
254  device->cname = "MCP77/MCP78";
255  device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
256  device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
257  device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
258  device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
259  device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
260  device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
261  device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
262  device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
263  device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
264  device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
265  device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
266  device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
267  device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
268  device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
269  device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
270  device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
271  device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
272  device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
273  device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
274  device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
275  device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
276  device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
277  break;
278  case 0xac:
279  device->cname = "MCP79/MCP7A";
280  device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
281  device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
282  device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
283  device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
284  device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
285  device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
286  device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
287  device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
288  device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
289  device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
290  device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
291  device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
292  device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
293  device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
294  device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
295  device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
296  device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
297  device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
298  device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
299  device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
300  device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
301  device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
302  break;
303  case 0xa3:
304  device->cname = "GT215";
305  device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
306  device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
307  device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
308  device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
309  device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
310  device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
311  device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
312  device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
313  device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
314  device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
315  device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
316  device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
317  device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
318  device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
319  device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
320  device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
321  device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
322  device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
323  device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
324  device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
325  device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
326  device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
327  device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
328  break;
329  case 0xa5:
330  device->cname = "GT216";
331  device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
332  device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
333  device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
334  device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
335  device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
336  device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
337  device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
338  device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
339  device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
340  device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
341  device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
342  device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
343  device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
344  device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
345  device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
346  device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
347  device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
348  device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
349  device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
350  device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
351  device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
352  device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
353  break;
354  case 0xa8:
355  device->cname = "GT218";
356  device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
357  device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
358  device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
359  device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
360  device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
361  device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
362  device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
363  device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
364  device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
365  device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
366  device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
367  device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
368  device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
369  device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
370  device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
371  device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
372  device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
373  device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
374  device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
375  device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
376  device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
377  device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
378  break;
379  case 0xaf:
380  device->cname = "MCP89";
381  device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
382  device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
383  device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
384  device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
385  device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
386  device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
387  device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
388  device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
389  device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
390  device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
391  device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
392  device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
393  device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
394  device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
395  device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
396  device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
397  device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
398  device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
399  device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
400  device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
401  device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
402  device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
403  break;
404  default:
405  nv_fatal(device, "unknown Tesla chipset\n");
406  return -EINVAL;
407  }
408 
409  return 0;
410 }
Generated on Thu Jan 10 2013 13:32:21 for Linux Kernel by   doxygen 1.8.2