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nvc0.c
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1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 
25 #include <subdev/device.h>
26 #include <subdev/bios.h>
27 #include <subdev/gpio.h>
28 #include <subdev/i2c.h>
29 #include <subdev/clock.h>
30 #include <subdev/therm.h>
31 #include <subdev/mxm.h>
32 #include <subdev/devinit.h>
33 #include <subdev/mc.h>
34 #include <subdev/timer.h>
35 #include <subdev/fb.h>
36 #include <subdev/ltcg.h>
37 #include <subdev/ibus.h>
38 #include <subdev/instmem.h>
39 #include <subdev/vm.h>
40 #include <subdev/bar.h>
41 
42 #include <engine/dmaobj.h>
43 #include <engine/fifo.h>
44 #include <engine/software.h>
45 #include <engine/graph.h>
46 #include <engine/vp.h>
47 #include <engine/bsp.h>
48 #include <engine/ppp.h>
49 #include <engine/copy.h>
50 #include <engine/disp.h>
51 
52 int
53 nvc0_identify(struct nouveau_device *device)
54 {
55  switch (device->chipset) {
56  case 0xc0:
57  device->cname = "GF100";
58  device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
59  device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
60  device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
61  device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
62  device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
63  device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
64  device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
65  device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
66  device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
67  device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
68  device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
69  device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
70  device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
71  device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
72  device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
73  device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
74  device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
75  device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
76  device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
77  device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
78  device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
79  device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
80  device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
81  device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
82  device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
83  break;
84  case 0xc4:
85  device->cname = "GF104";
86  device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
87  device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
88  device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
89  device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
90  device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
91  device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
92  device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
93  device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
94  device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
95  device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
96  device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
97  device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
98  device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
99  device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
100  device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
101  device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
102  device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
103  device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
104  device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
105  device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
106  device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
107  device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
108  device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
109  device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
110  device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
111  break;
112  case 0xc3:
113  device->cname = "GF106";
114  device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
115  device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
116  device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
117  device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
118  device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
119  device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
120  device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
121  device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
122  device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
123  device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
124  device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
125  device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
126  device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
127  device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
128  device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
129  device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
130  device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
131  device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
132  device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
133  device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
134  device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
135  device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
136  device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
137  device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
138  device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
139  break;
140  case 0xce:
141  device->cname = "GF114";
142  device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
143  device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
144  device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
145  device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
146  device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
147  device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
148  device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
149  device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
150  device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
151  device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
152  device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
153  device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
154  device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
155  device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
156  device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
157  device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
158  device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
159  device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
160  device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
161  device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
162  device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
163  device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
164  device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
165  device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
166  device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
167  break;
168  case 0xcf:
169  device->cname = "GF116";
170  device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
171  device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
172  device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
173  device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
174  device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
175  device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
176  device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
177  device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
178  device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
179  device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
180  device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
181  device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
182  device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
183  device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
184  device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
185  device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
186  device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
187  device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
188  device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
189  device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
190  device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
191  device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
192  device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
193  device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
194  device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
195  break;
196  case 0xc1:
197  device->cname = "GF108";
198  device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
199  device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
200  device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
201  device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
202  device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
203  device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
204  device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
205  device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
206  device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
207  device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
208  device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
209  device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
210  device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
211  device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
212  device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
213  device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
214  device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
215  device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
216  device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
217  device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
218  device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
219  device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
220  device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
221  device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
222  device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
223  break;
224  case 0xc8:
225  device->cname = "GF110";
226  device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
227  device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
228  device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
229  device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
230  device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
231  device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
232  device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
233  device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
234  device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
235  device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
236  device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
237  device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
238  device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
239  device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
240  device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
241  device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
242  device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
243  device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
244  device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
245  device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
246  device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
247  device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
248  device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
249  device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
250  device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
251  break;
252  case 0xd9:
253  device->cname = "GF119";
254  device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
255  device->oclass[NVDEV_SUBDEV_GPIO ] = &nvd0_gpio_oclass;
256  device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
257  device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
258  device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
259  device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
260  device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
261  device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
262  device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
263  device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
264  device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
265  device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
266  device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
267  device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
268  device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
269  device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
270  device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
271  device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
272  device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
273  device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
274  device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
275  device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
276  device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
277  device->oclass[NVDEV_ENGINE_DISP ] = &nvd0_disp_oclass;
278  break;
279  default:
280  nv_fatal(device, "unknown Fermi chipset\n");
281  return -EINVAL;
282  }
283 
284  return 0;
285 }
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