ti_hdmi_4xxx_ip.h File Reference

#include <linux/string.h>
#include <video/omapdss.h>
#include "ti_hdmi.h"

Go to the source code of this file.

Data Structures
struct	hdmi_core_video_config
struct	hdmi_core_packet_enable_repeat
struct	hdmi_video_format
struct	hdmi_audio_format
struct	hdmi_audio_dma
struct	hdmi_core_audio_i2s_config
struct	hdmi_core_audio_config

Macros
#define	HDMI_WP_REVISION   0x0
#define	HDMI_WP_SYSCONFIG   0x10
#define	HDMI_WP_IRQSTATUS_RAW   0x24
#define	HDMI_WP_IRQSTATUS   0x28
#define	HDMI_WP_PWR_CTRL   0x40
#define	HDMI_WP_IRQENABLE_SET   0x2C
#define	HDMI_WP_VIDEO_CFG   0x50
#define	HDMI_WP_VIDEO_SIZE   0x60
#define	HDMI_WP_VIDEO_TIMING_H   0x68
#define	HDMI_WP_VIDEO_TIMING_V   0x6C
#define	HDMI_WP_WP_CLK   0x70
#define	HDMI_WP_AUDIO_CFG   0x80
#define	HDMI_WP_AUDIO_CFG2   0x84
#define	HDMI_WP_AUDIO_CTRL   0x88
#define	HDMI_WP_AUDIO_DATA   0x8C
#define	HDMI_CORE_SYS_VND_IDL   0x0
#define	HDMI_CORE_SYS_DEV_IDL   0x8
#define	HDMI_CORE_SYS_DEV_IDH   0xC
#define	HDMI_CORE_SYS_DEV_REV   0x10
#define	HDMI_CORE_SYS_SRST   0x14
#define	HDMI_CORE_CTRL1   0x20
#define	HDMI_CORE_SYS_SYS_STAT   0x24
#define	HDMI_CORE_SYS_DE_DLY   0xC8
#define	HDMI_CORE_SYS_DE_CTRL   0xCC
#define	HDMI_CORE_SYS_DE_TOP   0xD0
#define	HDMI_CORE_SYS_DE_CNTL   0xD8
#define	HDMI_CORE_SYS_DE_CNTH   0xDC
#define	HDMI_CORE_SYS_DE_LINL   0xE0
#define	HDMI_CORE_SYS_DE_LINH_1   0xE4
#define	HDMI_CORE_SYS_VID_ACEN   0x124
#define	HDMI_CORE_SYS_VID_MODE   0x128
#define	HDMI_CORE_SYS_INTR_STATE   0x1C0
#define	HDMI_CORE_SYS_INTR1   0x1C4
#define	HDMI_CORE_SYS_INTR2   0x1C8
#define	HDMI_CORE_SYS_INTR3   0x1CC
#define	HDMI_CORE_SYS_INTR4   0x1D0
#define	HDMI_CORE_SYS_UMASK1   0x1D4
#define	HDMI_CORE_SYS_TMDS_CTRL   0x208
#define	HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC   0x1
#define	HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC   0x1
#define	HDMI_CORE_CTRL1_BSEL_24BITBUS   0x1
#define	HDMI_CORE_CTRL1_EDGE_RISINGEDGE   0x1
#define	HDMI_CORE_DDC_ADDR   0x3B4
#define	HDMI_CORE_DDC_SEGM   0x3B8
#define	HDMI_CORE_DDC_OFFSET   0x3BC
#define	HDMI_CORE_DDC_COUNT1   0x3C0
#define	HDMI_CORE_DDC_COUNT2   0x3C4
#define	HDMI_CORE_DDC_STATUS   0x3C8
#define	HDMI_CORE_DDC_CMD   0x3CC
#define	HDMI_CORE_DDC_DATA   0x3D0
#define	HDMI_CORE_AV_ACR_CTRL   0x4
#define	HDMI_CORE_AV_FREQ_SVAL   0x8
#define	HDMI_CORE_AV_N_SVAL1   0xC
#define	HDMI_CORE_AV_N_SVAL2   0x10
#define	HDMI_CORE_AV_N_SVAL3   0x14
#define	HDMI_CORE_AV_CTS_SVAL1   0x18
#define	HDMI_CORE_AV_CTS_SVAL2   0x1C
#define	HDMI_CORE_AV_CTS_SVAL3   0x20
#define	HDMI_CORE_AV_CTS_HVAL1   0x24
#define	HDMI_CORE_AV_CTS_HVAL2   0x28
#define	HDMI_CORE_AV_CTS_HVAL3   0x2C
#define	HDMI_CORE_AV_AUD_MODE   0x50
#define	HDMI_CORE_AV_SPDIF_CTRL   0x54
#define	HDMI_CORE_AV_HW_SPDIF_FS   0x60
#define	HDMI_CORE_AV_SWAP_I2S   0x64
#define	HDMI_CORE_AV_SPDIF_ERTH   0x6C
#define	HDMI_CORE_AV_I2S_IN_MAP   0x70
#define	HDMI_CORE_AV_I2S_IN_CTRL   0x74
#define	HDMI_CORE_AV_I2S_CHST0   0x78
#define	HDMI_CORE_AV_I2S_CHST1   0x7C
#define	HDMI_CORE_AV_I2S_CHST2   0x80
#define	HDMI_CORE_AV_I2S_CHST4   0x84
#define	HDMI_CORE_AV_I2S_CHST5   0x88
#define	HDMI_CORE_AV_ASRC   0x8C
#define	HDMI_CORE_AV_I2S_IN_LEN   0x90
#define	HDMI_CORE_AV_HDMI_CTRL   0xBC
#define	HDMI_CORE_AV_AUDO_TXSTAT   0xC0
#define	HDMI_CORE_AV_AUD_PAR_BUSCLK_1   0xCC
#define	HDMI_CORE_AV_AUD_PAR_BUSCLK_2   0xD0
#define	HDMI_CORE_AV_AUD_PAR_BUSCLK_3   0xD4
#define	HDMI_CORE_AV_TEST_TXCTRL   0xF0
#define	HDMI_CORE_AV_DPD   0xF4
#define	HDMI_CORE_AV_PB_CTRL1   0xF8
#define	HDMI_CORE_AV_PB_CTRL2   0xFC
#define	HDMI_CORE_AV_AVI_TYPE   0x100
#define	HDMI_CORE_AV_AVI_VERS   0x104
#define	HDMI_CORE_AV_AVI_LEN   0x108
#define	HDMI_CORE_AV_AVI_CHSUM   0x10C
#define	HDMI_CORE_AV_AVI_DBYTE(n)   (n * 4 + 0x110)
#define	HDMI_CORE_AV_SPD_TYPE   0x180
#define	HDMI_CORE_AV_SPD_VERS   0x184
#define	HDMI_CORE_AV_SPD_LEN   0x188
#define	HDMI_CORE_AV_SPD_CHSUM   0x18C
#define	HDMI_CORE_AV_SPD_DBYTE(n)   (n * 4 + 0x190)
#define	HDMI_CORE_AV_AUDIO_TYPE   0x200
#define	HDMI_CORE_AV_AUDIO_VERS   0x204
#define	HDMI_CORE_AV_AUDIO_LEN   0x208
#define	HDMI_CORE_AV_AUDIO_CHSUM   0x20C
#define	HDMI_CORE_AV_AUD_DBYTE(n)   (n * 4 + 0x210)
#define	HDMI_CORE_AV_MPEG_TYPE   0x280
#define	HDMI_CORE_AV_MPEG_VERS   0x284
#define	HDMI_CORE_AV_MPEG_LEN   0x288
#define	HDMI_CORE_AV_MPEG_CHSUM   0x28C
#define	HDMI_CORE_AV_MPEG_DBYTE(n)   (n * 4 + 0x290)
#define	HDMI_CORE_AV_GEN_DBYTE(n)   (n * 4 + 0x300)
#define	HDMI_CORE_AV_CP_BYTE1   0x37C
#define	HDMI_CORE_AV_GEN2_DBYTE(n)   (n * 4 + 0x380)
#define	HDMI_CORE_AV_CEC_ADDR_ID   0x3FC
#define	HDMI_CORE_AV_SPD_DBYTE_ELSIZE   0x4
#define	HDMI_CORE_AV_GEN2_DBYTE_ELSIZE   0x4
#define	HDMI_CORE_AV_MPEG_DBYTE_ELSIZE   0x4
#define	HDMI_CORE_AV_GEN_DBYTE_ELSIZE   0x4
#define	HDMI_CORE_AV_AVI_DBYTE_NELEMS   15
#define	HDMI_CORE_AV_SPD_DBYTE_NELEMS   27
#define	HDMI_CORE_AV_AUD_DBYTE_NELEMS   10
#define	HDMI_CORE_AV_MPEG_DBYTE_NELEMS   27
#define	HDMI_CORE_AV_GEN_DBYTE_NELEMS   31
#define	HDMI_CORE_AV_GEN2_DBYTE_NELEMS   31
#define	PLLCTRL_PLL_CONTROL   0x0
#define	PLLCTRL_PLL_STATUS   0x4
#define	PLLCTRL_PLL_GO   0x8
#define	PLLCTRL_CFG1   0xC
#define	PLLCTRL_CFG2   0x10
#define	PLLCTRL_CFG3   0x14
#define	PLLCTRL_CFG4   0x20
#define	HDMI_TXPHY_TX_CTRL   0x0
#define	HDMI_TXPHY_DIGITAL_CTRL   0x4
#define	HDMI_TXPHY_POWER_CTRL   0x8
#define	HDMI_TXPHY_PAD_CFG_CTRL   0xC
#define	REG_FLD_MOD(base, idx, val, start, end)
#define	REG_GET(base, idx, start, end)   FLD_GET(hdmi_read_reg(base, idx), start, end)

Enumerations
enum	hdmi_phy_pwr { HDMI_PHYPWRCMD_OFF = 0, HDMI_PHYPWRCMD_LDOON = 1, HDMI_PHYPWRCMD_TXON = 2 }
enum	hdmi_core_inputbus_width { HDMI_INPUT_8BIT = 0, HDMI_INPUT_10BIT = 1, HDMI_INPUT_12BIT = 2 }
enum	hdmi_core_dither_trunc {   HDMI_OUTPUTTRUNCATION_8BIT = 0, HDMI_OUTPUTTRUNCATION_10BIT = 1, HDMI_OUTPUTTRUNCATION_12BIT = 2, HDMI_OUTPUTDITHER_8BIT = 3,   HDMI_OUTPUTDITHER_10BIT = 4, HDMI_OUTPUTDITHER_12BIT = 5 }
enum	hdmi_core_deepcolor_ed { HDMI_DEEPCOLORPACKECTDISABLE = 0, HDMI_DEEPCOLORPACKECTENABLE = 1 }
enum	hdmi_core_packet_mode {   HDMI_PACKETMODERESERVEDVALUE = 0, HDMI_PACKETMODE24BITPERPIXEL = 4, HDMI_PACKETMODE30BITPERPIXEL = 5, HDMI_PACKETMODE36BITPERPIXEL = 6,   HDMI_PACKETMODE48BITPERPIXEL = 7 }
enum	hdmi_core_tclkselclkmult { HDMI_FPLL05IDCK = 0, HDMI_FPLL10IDCK = 1, HDMI_FPLL20IDCK = 2, HDMI_FPLL40IDCK = 3 }
enum	hdmi_core_packet_ctrl { HDMI_PACKETENABLE = 1, HDMI_PACKETDISABLE = 0, HDMI_PACKETREPEATON = 1, HDMI_PACKETREPEATOFF = 0 }
enum	hdmi_core_infoframe {   HDMI_INFOFRAME_AVI_DB1Y_RGB = 0, HDMI_INFOFRAME_AVI_DB1Y_YUV422 = 1, HDMI_INFOFRAME_AVI_DB1Y_YUV444 = 2, HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF = 0,   HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_ON = 1, HDMI_INFOFRAME_AVI_DB1B_NO = 0, HDMI_INFOFRAME_AVI_DB1B_VERT = 1, HDMI_INFOFRAME_AVI_DB1B_HORI = 2,   HDMI_INFOFRAME_AVI_DB1B_VERTHORI = 3, HDMI_INFOFRAME_AVI_DB1S_0 = 0, HDMI_INFOFRAME_AVI_DB1S_1 = 1, HDMI_INFOFRAME_AVI_DB1S_2 = 2,   HDMI_INFOFRAME_AVI_DB2C_NO = 0, HDMI_INFOFRAME_AVI_DB2C_ITU601 = 1, HDMI_INFOFRAME_AVI_DB2C_ITU709 = 2, HDMI_INFOFRAME_AVI_DB2C_EC_EXTENDED = 3,   HDMI_INFOFRAME_AVI_DB2M_NO = 0, HDMI_INFOFRAME_AVI_DB2M_43 = 1, HDMI_INFOFRAME_AVI_DB2M_169 = 2, HDMI_INFOFRAME_AVI_DB2R_SAME = 8,   HDMI_INFOFRAME_AVI_DB2R_43 = 9, HDMI_INFOFRAME_AVI_DB2R_169 = 10, HDMI_INFOFRAME_AVI_DB2R_149 = 11, HDMI_INFOFRAME_AVI_DB3ITC_NO = 0,   HDMI_INFOFRAME_AVI_DB3ITC_YES = 1, HDMI_INFOFRAME_AVI_DB3EC_XVYUV601 = 0, HDMI_INFOFRAME_AVI_DB3EC_XVYUV709 = 1, HDMI_INFOFRAME_AVI_DB3Q_DEFAULT = 0,   HDMI_INFOFRAME_AVI_DB3Q_LR = 1, HDMI_INFOFRAME_AVI_DB3Q_FR = 2, HDMI_INFOFRAME_AVI_DB3SC_NO = 0, HDMI_INFOFRAME_AVI_DB3SC_HORI = 1,   HDMI_INFOFRAME_AVI_DB3SC_VERT = 2, HDMI_INFOFRAME_AVI_DB3SC_HORIVERT = 3, HDMI_INFOFRAME_AVI_DB5PR_NO = 0, HDMI_INFOFRAME_AVI_DB5PR_2 = 1,   HDMI_INFOFRAME_AVI_DB5PR_3 = 2, HDMI_INFOFRAME_AVI_DB5PR_4 = 3, HDMI_INFOFRAME_AVI_DB5PR_5 = 4, HDMI_INFOFRAME_AVI_DB5PR_6 = 5,   HDMI_INFOFRAME_AVI_DB5PR_7 = 6, HDMI_INFOFRAME_AVI_DB5PR_8 = 7, HDMI_INFOFRAME_AVI_DB5PR_9 = 8, HDMI_INFOFRAME_AVI_DB5PR_10 = 9 }
enum	hdmi_packing_mode { HDMI_PACK_10b_RGB_YUV444 = 0, HDMI_PACK_24b_RGB_YUV444_YUV422 = 1, HDMI_PACK_20b_YUV422 = 2, HDMI_PACK_ALREADYPACKED = 7 }
enum	hdmi_core_audio_layout { HDMI_AUDIO_LAYOUT_2CH = 0, HDMI_AUDIO_LAYOUT_8CH = 1 }
enum	hdmi_core_cts_mode { HDMI_AUDIO_CTS_MODE_HW = 0, HDMI_AUDIO_CTS_MODE_SW = 1 }
enum	hdmi_stereo_channels {   HDMI_AUDIO_STEREO_NOCHANNELS = 0, HDMI_AUDIO_STEREO_ONECHANNEL = 1, HDMI_AUDIO_STEREO_TWOCHANNELS = 2, HDMI_AUDIO_STEREO_THREECHANNELS = 3,   HDMI_AUDIO_STEREO_FOURCHANNELS = 4 }
enum	hdmi_audio_type { HDMI_AUDIO_TYPE_LPCM = 0, HDMI_AUDIO_TYPE_IEC = 1 }
enum	hdmi_audio_justify { HDMI_AUDIO_JUSTIFY_LEFT = 0, HDMI_AUDIO_JUSTIFY_RIGHT = 1 }
enum	hdmi_audio_sample_order { HDMI_AUDIO_SAMPLE_RIGHT_FIRST = 0, HDMI_AUDIO_SAMPLE_LEFT_FIRST = 1 }
enum	hdmi_audio_samples_perword { HDMI_AUDIO_ONEWORD_ONESAMPLE = 0, HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1 }
enum	hdmi_audio_sample_size { HDMI_AUDIO_SAMPLE_16BITS = 0, HDMI_AUDIO_SAMPLE_24BITS = 1 }
enum	hdmi_audio_transf_mode { HDMI_AUDIO_TRANSF_DMA = 0, HDMI_AUDIO_TRANSF_IRQ = 1 }
enum	hdmi_audio_blk_strt_end_sig { HDMI_AUDIO_BLOCK_SIG_STARTEND_ON = 0, HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1 }
enum	hdmi_audio_i2s_config {   HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST = 0, HDMI_AUDIO_I2S_LSB_SHIFTED_FIRST = 1, HDMI_AUDIO_I2S_SCK_EDGE_FALLING = 0, HDMI_AUDIO_I2S_SCK_EDGE_RISING = 1,   HDMI_AUDIO_I2S_VBIT_FOR_PCM = 0, HDMI_AUDIO_I2S_VBIT_FOR_COMPRESSED = 1, HDMI_AUDIO_I2S_FIRST_BIT_SHIFT = 0, HDMI_AUDIO_I2S_FIRST_BIT_NO_SHIFT = 1,   HDMI_AUDIO_I2S_SD0_EN = 1, HDMI_AUDIO_I2S_SD1_EN = 1 << 1, HDMI_AUDIO_I2S_SD2_EN = 1 << 2, HDMI_AUDIO_I2S_SD3_EN = 1 << 3 }
enum	hdmi_audio_mclk_mode {   HDMI_AUDIO_MCLK_128FS = 0, HDMI_AUDIO_MCLK_256FS = 1, HDMI_AUDIO_MCLK_384FS = 2, HDMI_AUDIO_MCLK_512FS = 3,   HDMI_AUDIO_MCLK_768FS = 4, HDMI_AUDIO_MCLK_1024FS = 5, HDMI_AUDIO_MCLK_1152FS = 6, HDMI_AUDIO_MCLK_192FS = 7 }

Macro Definition Documentation

#define HDMI_CORE_AV_ACR_CTRL   0x4

Definition at line 89 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_ASRC   0x8C

Definition at line 112 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_AUD_DBYTE

(

n

)

(n * 4 + 0x210)

Definition at line 137 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_AUD_DBYTE_NELEMS   10

Definition at line 155 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_AUD_MODE   0x50

Definition at line 100 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_AUD_PAR_BUSCLK_1   0xCC

Definition at line 116 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_AUD_PAR_BUSCLK_2   0xD0

Definition at line 117 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_AUD_PAR_BUSCLK_3   0xD4

Definition at line 118 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_AUDIO_CHSUM   0x20C

Definition at line 136 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_AUDIO_LEN   0x208

Definition at line 135 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_AUDIO_TYPE   0x200

Definition at line 133 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_AUDIO_VERS   0x204

Definition at line 134 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_AUDO_TXSTAT   0xC0

Definition at line 115 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_AVI_CHSUM   0x10C

Definition at line 126 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_AVI_DBYTE

(

n

)

(n * 4 + 0x110)

Definition at line 127 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_AVI_DBYTE_NELEMS   15

Definition at line 153 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_AVI_LEN   0x108

Definition at line 125 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_AVI_TYPE   0x100

Definition at line 123 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_AVI_VERS   0x104

Definition at line 124 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_CEC_ADDR_ID   0x3FC

Definition at line 146 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_CP_BYTE1   0x37C

Definition at line 144 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_CTS_HVAL1   0x24

Definition at line 97 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_CTS_HVAL2   0x28

Definition at line 98 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_CTS_HVAL3   0x2C

Definition at line 99 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_CTS_SVAL1   0x18

Definition at line 94 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_CTS_SVAL2   0x1C

Definition at line 95 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_CTS_SVAL3   0x20

Definition at line 96 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_DPD   0xF4

Definition at line 120 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_FREQ_SVAL   0x8

Definition at line 90 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_GEN2_DBYTE

(

n

)

(n * 4 + 0x380)

Definition at line 145 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_GEN2_DBYTE_ELSIZE   0x4

Definition at line 149 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_GEN2_DBYTE_NELEMS   31

Definition at line 158 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_GEN_DBYTE

(

n

)

(n * 4 + 0x300)

Definition at line 143 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_GEN_DBYTE_ELSIZE   0x4

Definition at line 151 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_GEN_DBYTE_NELEMS   31

Definition at line 157 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_HDMI_CTRL   0xBC

Definition at line 114 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_HW_SPDIF_FS   0x60

Definition at line 102 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_I2S_CHST0   0x78

Definition at line 107 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_I2S_CHST1   0x7C

Definition at line 108 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_I2S_CHST2   0x80

Definition at line 109 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_I2S_CHST4   0x84

Definition at line 110 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_I2S_CHST5   0x88

Definition at line 111 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_I2S_IN_CTRL   0x74

Definition at line 106 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_I2S_IN_LEN   0x90

Definition at line 113 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_I2S_IN_MAP   0x70

Definition at line 105 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_MPEG_CHSUM   0x28C

Definition at line 141 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_MPEG_DBYTE

(

n

)

(n * 4 + 0x290)

Definition at line 142 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_MPEG_DBYTE_ELSIZE   0x4

Definition at line 150 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_MPEG_DBYTE_NELEMS   27

Definition at line 156 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_MPEG_LEN   0x288

Definition at line 140 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_MPEG_TYPE   0x280

Definition at line 138 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_MPEG_VERS   0x284

Definition at line 139 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_N_SVAL1   0xC

Definition at line 91 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_N_SVAL2   0x10

Definition at line 92 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_N_SVAL3   0x14

Definition at line 93 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_PB_CTRL1   0xF8

Definition at line 121 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_PB_CTRL2   0xFC

Definition at line 122 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_SPD_CHSUM   0x18C

Definition at line 131 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_SPD_DBYTE

(

n

)

(n * 4 + 0x190)

Definition at line 132 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_SPD_DBYTE_ELSIZE   0x4

Definition at line 148 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_SPD_DBYTE_NELEMS   27

Definition at line 154 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_SPD_LEN   0x188

Definition at line 130 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_SPD_TYPE   0x180

Definition at line 128 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_SPD_VERS   0x184

Definition at line 129 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_SPDIF_CTRL   0x54

Definition at line 101 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_SPDIF_ERTH   0x6C

Definition at line 104 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_SWAP_I2S   0x64

Definition at line 103 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_AV_TEST_TXCTRL   0xF0

Definition at line 119 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_CTRL1   0x20

Definition at line 53 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_CTRL1_BSEL_24BITBUS   0x1

Definition at line 74 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_CTRL1_EDGE_RISINGEDGE   0x1

Definition at line 75 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC   0x1

Definition at line 73 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC   0x1

Definition at line 72 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_DDC_ADDR   0x3B4

Definition at line 78 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_DDC_CMD   0x3CC

Definition at line 84 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_DDC_COUNT1   0x3C0

Definition at line 81 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_DDC_COUNT2   0x3C4

Definition at line 82 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_DDC_DATA   0x3D0

Definition at line 85 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_DDC_OFFSET   0x3BC

Definition at line 80 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_DDC_SEGM   0x3B8

Definition at line 79 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_DDC_STATUS   0x3C8

Definition at line 83 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_SYS_DE_CNTH   0xDC

Definition at line 59 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_SYS_DE_CNTL   0xD8

Definition at line 58 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_SYS_DE_CTRL   0xCC

Definition at line 56 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_SYS_DE_DLY   0xC8

Definition at line 55 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_SYS_DE_LINH_1   0xE4

Definition at line 61 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_SYS_DE_LINL   0xE0

Definition at line 60 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_SYS_DE_TOP   0xD0

Definition at line 57 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_SYS_DEV_IDH   0xC

Definition at line 50 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_SYS_DEV_IDL   0x8

Definition at line 49 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_SYS_DEV_REV   0x10

Definition at line 51 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_SYS_INTR1   0x1C4

Definition at line 65 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_SYS_INTR2   0x1C8

Definition at line 66 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_SYS_INTR3   0x1CC

Definition at line 67 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_SYS_INTR4   0x1D0

Definition at line 68 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_SYS_INTR_STATE   0x1C0

Definition at line 64 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_SYS_SRST   0x14

Definition at line 52 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_SYS_SYS_STAT   0x24

Definition at line 54 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_SYS_TMDS_CTRL   0x208

Definition at line 70 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_SYS_UMASK1   0x1D4

Definition at line 69 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_SYS_VID_ACEN   0x124

Definition at line 62 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_SYS_VID_MODE   0x128

Definition at line 63 of file ti_hdmi_4xxx_ip.h.

#define HDMI_CORE_SYS_VND_IDL   0x0

Definition at line 48 of file ti_hdmi_4xxx_ip.h.

#define HDMI_TXPHY_DIGITAL_CTRL   0x4

Definition at line 173 of file ti_hdmi_4xxx_ip.h.

#define HDMI_TXPHY_PAD_CFG_CTRL   0xC

Definition at line 175 of file ti_hdmi_4xxx_ip.h.

#define HDMI_TXPHY_POWER_CTRL   0x8

Definition at line 174 of file ti_hdmi_4xxx_ip.h.

#define HDMI_TXPHY_TX_CTRL   0x0

Definition at line 172 of file ti_hdmi_4xxx_ip.h.

#define HDMI_WP_AUDIO_CFG   0x80

Definition at line 41 of file ti_hdmi_4xxx_ip.h.

#define HDMI_WP_AUDIO_CFG2   0x84

Definition at line 42 of file ti_hdmi_4xxx_ip.h.

#define HDMI_WP_AUDIO_CTRL   0x88

Definition at line 43 of file ti_hdmi_4xxx_ip.h.

#define HDMI_WP_AUDIO_DATA   0x8C

Definition at line 44 of file ti_hdmi_4xxx_ip.h.

#define HDMI_WP_IRQENABLE_SET   0x2C

Definition at line 35 of file ti_hdmi_4xxx_ip.h.

#define HDMI_WP_IRQSTATUS   0x28

Definition at line 33 of file ti_hdmi_4xxx_ip.h.

#define HDMI_WP_IRQSTATUS_RAW   0x24

Definition at line 32 of file ti_hdmi_4xxx_ip.h.

#define HDMI_WP_PWR_CTRL   0x40

Definition at line 34 of file ti_hdmi_4xxx_ip.h.

#define HDMI_WP_REVISION   0x0

Definition at line 30 of file ti_hdmi_4xxx_ip.h.

#define HDMI_WP_SYSCONFIG   0x10

Definition at line 31 of file ti_hdmi_4xxx_ip.h.

#define HDMI_WP_VIDEO_CFG   0x50

Definition at line 36 of file ti_hdmi_4xxx_ip.h.

#define HDMI_WP_VIDEO_SIZE   0x60

Definition at line 37 of file ti_hdmi_4xxx_ip.h.

#define HDMI_WP_VIDEO_TIMING_H   0x68

Definition at line 38 of file ti_hdmi_4xxx_ip.h.

#define HDMI_WP_VIDEO_TIMING_V   0x6C

Definition at line 39 of file ti_hdmi_4xxx_ip.h.

#define HDMI_WP_WP_CLK   0x70

Definition at line 40 of file ti_hdmi_4xxx_ip.h.

#define PLLCTRL_CFG1   0xC

Definition at line 165 of file ti_hdmi_4xxx_ip.h.

#define PLLCTRL_CFG2   0x10

Definition at line 166 of file ti_hdmi_4xxx_ip.h.

#define PLLCTRL_CFG3   0x14

Definition at line 167 of file ti_hdmi_4xxx_ip.h.

#define PLLCTRL_CFG4   0x20

Definition at line 168 of file ti_hdmi_4xxx_ip.h.

#define PLLCTRL_PLL_CONTROL   0x0

Definition at line 162 of file ti_hdmi_4xxx_ip.h.

#define PLLCTRL_PLL_GO   0x8

Definition at line 164 of file ti_hdmi_4xxx_ip.h.

#define PLLCTRL_PLL_STATUS   0x4

Definition at line 163 of file ti_hdmi_4xxx_ip.h.

#define REG_FLD_MOD	(		base,
			idx,
			val,
			start,
			end
	)

Value:

hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
                            val, start, end))

Definition at line 177 of file ti_hdmi_4xxx_ip.h.

#define REG_GET	(		base,
			idx,
			start,
			end
	)		FLD_GET(hdmi_read_reg(base, idx), start, end)

Definition at line 180 of file ti_hdmi_4xxx_ip.h.

Enumeration Type Documentation

enum hdmi_audio_blk_strt_end_sig

Enumerator:

HDMI_AUDIO_BLOCK_SIG_STARTEND_ON
HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF

Definition at line 334 of file ti_hdmi_4xxx_ip.h.

enum hdmi_audio_i2s_config

Enumerator:

HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST
HDMI_AUDIO_I2S_LSB_SHIFTED_FIRST
HDMI_AUDIO_I2S_SCK_EDGE_FALLING
HDMI_AUDIO_I2S_SCK_EDGE_RISING
HDMI_AUDIO_I2S_VBIT_FOR_PCM
HDMI_AUDIO_I2S_VBIT_FOR_COMPRESSED
HDMI_AUDIO_I2S_FIRST_BIT_SHIFT
HDMI_AUDIO_I2S_FIRST_BIT_NO_SHIFT
HDMI_AUDIO_I2S_SD0_EN
HDMI_AUDIO_I2S_SD1_EN
HDMI_AUDIO_I2S_SD2_EN
HDMI_AUDIO_I2S_SD3_EN

Definition at line 339 of file ti_hdmi_4xxx_ip.h.

enum hdmi_audio_justify

Enumerator:

HDMI_AUDIO_JUSTIFY_LEFT
HDMI_AUDIO_JUSTIFY_RIGHT

Definition at line 309 of file ti_hdmi_4xxx_ip.h.

enum hdmi_audio_mclk_mode

Enumerator:

HDMI_AUDIO_MCLK_128FS
HDMI_AUDIO_MCLK_256FS
HDMI_AUDIO_MCLK_384FS
HDMI_AUDIO_MCLK_512FS
HDMI_AUDIO_MCLK_768FS
HDMI_AUDIO_MCLK_1024FS
HDMI_AUDIO_MCLK_1152FS
HDMI_AUDIO_MCLK_192FS

Definition at line 354 of file ti_hdmi_4xxx_ip.h.

enum hdmi_audio_sample_order

Enumerator:

HDMI_AUDIO_SAMPLE_RIGHT_FIRST
HDMI_AUDIO_SAMPLE_LEFT_FIRST

Definition at line 314 of file ti_hdmi_4xxx_ip.h.

enum hdmi_audio_sample_size

Enumerator:

HDMI_AUDIO_SAMPLE_16BITS
HDMI_AUDIO_SAMPLE_24BITS

Definition at line 324 of file ti_hdmi_4xxx_ip.h.

enum hdmi_audio_samples_perword

Enumerator:

HDMI_AUDIO_ONEWORD_ONESAMPLE
HDMI_AUDIO_ONEWORD_TWOSAMPLES

Definition at line 319 of file ti_hdmi_4xxx_ip.h.

enum hdmi_audio_transf_mode

Enumerator:

HDMI_AUDIO_TRANSF_DMA
HDMI_AUDIO_TRANSF_IRQ

Definition at line 329 of file ti_hdmi_4xxx_ip.h.

enum hdmi_audio_type

Enumerator:

HDMI_AUDIO_TYPE_LPCM
HDMI_AUDIO_TYPE_IEC

Definition at line 304 of file ti_hdmi_4xxx_ip.h.

enum hdmi_core_audio_layout

Enumerator:

HDMI_AUDIO_LAYOUT_2CH
HDMI_AUDIO_LAYOUT_8CH

Definition at line 286 of file ti_hdmi_4xxx_ip.h.

enum hdmi_core_cts_mode

Enumerator:

HDMI_AUDIO_CTS_MODE_HW
HDMI_AUDIO_CTS_MODE_SW

Definition at line 291 of file ti_hdmi_4xxx_ip.h.

enum hdmi_core_deepcolor_ed

Enumerator:

HDMI_DEEPCOLORPACKECTDISABLE
HDMI_DEEPCOLORPACKECTENABLE

Definition at line 204 of file ti_hdmi_4xxx_ip.h.

enum hdmi_core_dither_trunc

Enumerator:

HDMI_OUTPUTTRUNCATION_8BIT
HDMI_OUTPUTTRUNCATION_10BIT
HDMI_OUTPUTTRUNCATION_12BIT
HDMI_OUTPUTDITHER_8BIT
HDMI_OUTPUTDITHER_10BIT
HDMI_OUTPUTDITHER_12BIT

Definition at line 195 of file ti_hdmi_4xxx_ip.h.

enum hdmi_core_infoframe

Enumerator:

HDMI_INFOFRAME_AVI_DB1Y_RGB
HDMI_INFOFRAME_AVI_DB1Y_YUV422
HDMI_INFOFRAME_AVI_DB1Y_YUV444
HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF
HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_ON
HDMI_INFOFRAME_AVI_DB1B_NO
HDMI_INFOFRAME_AVI_DB1B_VERT
HDMI_INFOFRAME_AVI_DB1B_HORI
HDMI_INFOFRAME_AVI_DB1B_VERTHORI
HDMI_INFOFRAME_AVI_DB1S_0
HDMI_INFOFRAME_AVI_DB1S_1
HDMI_INFOFRAME_AVI_DB1S_2
HDMI_INFOFRAME_AVI_DB2C_NO
HDMI_INFOFRAME_AVI_DB2C_ITU601
HDMI_INFOFRAME_AVI_DB2C_ITU709
HDMI_INFOFRAME_AVI_DB2C_EC_EXTENDED
HDMI_INFOFRAME_AVI_DB2M_NO
HDMI_INFOFRAME_AVI_DB2M_43
HDMI_INFOFRAME_AVI_DB2M_169
HDMI_INFOFRAME_AVI_DB2R_SAME
HDMI_INFOFRAME_AVI_DB2R_43
HDMI_INFOFRAME_AVI_DB2R_169
HDMI_INFOFRAME_AVI_DB2R_149
HDMI_INFOFRAME_AVI_DB3ITC_NO
HDMI_INFOFRAME_AVI_DB3ITC_YES
HDMI_INFOFRAME_AVI_DB3EC_XVYUV601
HDMI_INFOFRAME_AVI_DB3EC_XVYUV709
HDMI_INFOFRAME_AVI_DB3Q_DEFAULT
HDMI_INFOFRAME_AVI_DB3Q_LR
HDMI_INFOFRAME_AVI_DB3Q_FR
HDMI_INFOFRAME_AVI_DB3SC_NO
HDMI_INFOFRAME_AVI_DB3SC_HORI
HDMI_INFOFRAME_AVI_DB3SC_VERT
HDMI_INFOFRAME_AVI_DB3SC_HORIVERT
HDMI_INFOFRAME_AVI_DB5PR_NO
HDMI_INFOFRAME_AVI_DB5PR_2
HDMI_INFOFRAME_AVI_DB5PR_3
HDMI_INFOFRAME_AVI_DB5PR_4
HDMI_INFOFRAME_AVI_DB5PR_5
HDMI_INFOFRAME_AVI_DB5PR_6
HDMI_INFOFRAME_AVI_DB5PR_7
HDMI_INFOFRAME_AVI_DB5PR_8
HDMI_INFOFRAME_AVI_DB5PR_9
HDMI_INFOFRAME_AVI_DB5PR_10

Definition at line 232 of file ti_hdmi_4xxx_ip.h.

enum hdmi_core_inputbus_width

Enumerator:

HDMI_INPUT_8BIT
HDMI_INPUT_10BIT
HDMI_INPUT_12BIT

Definition at line 189 of file ti_hdmi_4xxx_ip.h.

enum hdmi_core_packet_ctrl

Enumerator:

HDMI_PACKETENABLE
HDMI_PACKETDISABLE
HDMI_PACKETREPEATON
HDMI_PACKETREPEATOFF

Definition at line 224 of file ti_hdmi_4xxx_ip.h.

enum hdmi_core_packet_mode

Enumerator:

HDMI_PACKETMODERESERVEDVALUE
HDMI_PACKETMODE24BITPERPIXEL
HDMI_PACKETMODE30BITPERPIXEL
HDMI_PACKETMODE36BITPERPIXEL
HDMI_PACKETMODE48BITPERPIXEL

Definition at line 209 of file ti_hdmi_4xxx_ip.h.

enum hdmi_core_tclkselclkmult

Enumerator:

HDMI_FPLL05IDCK
HDMI_FPLL10IDCK
HDMI_FPLL20IDCK
HDMI_FPLL40IDCK

Definition at line 217 of file ti_hdmi_4xxx_ip.h.

enum hdmi_packing_mode

Enumerator:

HDMI_PACK_10b_RGB_YUV444
HDMI_PACK_24b_RGB_YUV444_YUV422
HDMI_PACK_20b_YUV422
HDMI_PACK_ALREADYPACKED

Definition at line 279 of file ti_hdmi_4xxx_ip.h.

enum hdmi_phy_pwr

Enumerator:

HDMI_PHYPWRCMD_OFF
HDMI_PHYPWRCMD_LDOON
HDMI_PHYPWRCMD_TXON

Definition at line 183 of file ti_hdmi_4xxx_ip.h.

enum hdmi_stereo_channels

Enumerator:

HDMI_AUDIO_STEREO_NOCHANNELS
HDMI_AUDIO_STEREO_ONECHANNEL
HDMI_AUDIO_STEREO_TWOCHANNELS
HDMI_AUDIO_STEREO_THREECHANNELS
HDMI_AUDIO_STEREO_FOURCHANNELS

Definition at line 296 of file ti_hdmi_4xxx_ip.h.