Go to the documentation of this file.
18 #ifndef __LINUX_MFD_TPS65217_H
19 #define __LINUX_MFD_TPS65217_H
21 #include <linux/i2c.h>
29 #define TPS65217_I2C_ID 0x24
32 #define TPS65217_REG_CHIPID 0X00
33 #define TPS65217_REG_PPATH 0X01
34 #define TPS65217_REG_INT 0X02
35 #define TPS65217_REG_CHGCONFIG0 0X03
36 #define TPS65217_REG_CHGCONFIG1 0X04
37 #define TPS65217_REG_CHGCONFIG2 0X05
38 #define TPS65217_REG_CHGCONFIG3 0X06
39 #define TPS65217_REG_WLEDCTRL1 0X07
40 #define TPS65217_REG_WLEDCTRL2 0X08
41 #define TPS65217_REG_MUXCTRL 0X09
42 #define TPS65217_REG_STATUS 0X0A
43 #define TPS65217_REG_PASSWORD 0X0B
44 #define TPS65217_REG_PGOOD 0X0C
45 #define TPS65217_REG_DEFPG 0X0D
46 #define TPS65217_REG_DEFDCDC1 0X0E
47 #define TPS65217_REG_DEFDCDC2 0X0F
48 #define TPS65217_REG_DEFDCDC3 0X10
49 #define TPS65217_REG_DEFSLEW 0X11
50 #define TPS65217_REG_DEFLDO1 0X12
51 #define TPS65217_REG_DEFLDO2 0X13
52 #define TPS65217_REG_DEFLS1 0X14
53 #define TPS65217_REG_DEFLS2 0X15
54 #define TPS65217_REG_ENABLE 0X16
55 #define TPS65217_REG_DEFUVLO 0X18
56 #define TPS65217_REG_SEQ1 0X19
57 #define TPS65217_REG_SEQ2 0X1A
58 #define TPS65217_REG_SEQ3 0X1B
59 #define TPS65217_REG_SEQ4 0X1C
60 #define TPS65217_REG_SEQ5 0X1D
61 #define TPS65217_REG_SEQ6 0X1E
64 #define TPS65217_CHIPID_CHIP_MASK 0xF0
65 #define TPS65217_CHIPID_REV_MASK 0x0F
67 #define TPS65217_PPATH_ACSINK_ENABLE BIT(7)
68 #define TPS65217_PPATH_USBSINK_ENABLE BIT(6)
69 #define TPS65217_PPATH_AC_PW_ENABLE BIT(5)
70 #define TPS65217_PPATH_USB_PW_ENABLE BIT(4)
71 #define TPS65217_PPATH_AC_CURRENT_MASK 0x0C
72 #define TPS65217_PPATH_USB_CURRENT_MASK 0x03
74 #define TPS65217_INT_PBM BIT(6)
75 #define TPS65217_INT_ACM BIT(5)
76 #define TPS65217_INT_USBM BIT(4)
77 #define TPS65217_INT_PBI BIT(2)
78 #define TPS65217_INT_ACI BIT(1)
79 #define TPS65217_INT_USBI BIT(0)
81 #define TPS65217_CHGCONFIG0_TREG BIT(7)
82 #define TPS65217_CHGCONFIG0_DPPM BIT(6)
83 #define TPS65217_CHGCONFIG0_TSUSP BIT(5)
84 #define TPS65217_CHGCONFIG0_TERMI BIT(4)
85 #define TPS65217_CHGCONFIG0_ACTIVE BIT(3)
86 #define TPS65217_CHGCONFIG0_CHGTOUT BIT(2)
87 #define TPS65217_CHGCONFIG0_PCHGTOUT BIT(1)
88 #define TPS65217_CHGCONFIG0_BATTEMP BIT(0)
90 #define TPS65217_CHGCONFIG1_TMR_MASK 0xC0
91 #define TPS65217_CHGCONFIG1_TMR_ENABLE BIT(5)
92 #define TPS65217_CHGCONFIG1_NTC_TYPE BIT(4)
93 #define TPS65217_CHGCONFIG1_RESET BIT(3)
94 #define TPS65217_CHGCONFIG1_TERM BIT(2)
95 #define TPS65217_CHGCONFIG1_SUSP BIT(1)
96 #define TPS65217_CHGCONFIG1_CHG_EN BIT(0)
98 #define TPS65217_CHGCONFIG2_DYNTMR BIT(7)
99 #define TPS65217_CHGCONFIG2_VPREGHG BIT(6)
100 #define TPS65217_CHGCONFIG2_VOREG_MASK 0x30
102 #define TPS65217_CHGCONFIG3_ICHRG_MASK 0xC0
103 #define TPS65217_CHGCONFIG3_DPPMTH_MASK 0x30
104 #define TPS65217_CHGCONFIG2_PCHRGT BIT(3)
105 #define TPS65217_CHGCONFIG2_TERMIF 0x06
106 #define TPS65217_CHGCONFIG2_TRANGE BIT(0)
108 #define TPS65217_WLEDCTRL1_ISINK_ENABLE BIT(3)
109 #define TPS65217_WLEDCTRL1_ISEL BIT(2)
110 #define TPS65217_WLEDCTRL1_FDIM_MASK 0x03
112 #define TPS65217_WLEDCTRL2_DUTY_MASK 0x7F
114 #define TPS65217_MUXCTRL_MUX_MASK 0x07
116 #define TPS65217_STATUS_OFF BIT(7)
117 #define TPS65217_STATUS_ACPWR BIT(3)
118 #define TPS65217_STATUS_USBPWR BIT(2)
119 #define TPS65217_STATUS_PB BIT(0)
121 #define TPS65217_PASSWORD_REGS_UNLOCK 0x7D
123 #define TPS65217_PGOOD_LDO3_PG BIT(6)
124 #define TPS65217_PGOOD_LDO4_PG BIT(5)
125 #define TPS65217_PGOOD_DC1_PG BIT(4)
126 #define TPS65217_PGOOD_DC2_PG BIT(3)
127 #define TPS65217_PGOOD_DC3_PG BIT(2)
128 #define TPS65217_PGOOD_LDO1_PG BIT(1)
129 #define TPS65217_PGOOD_LDO2_PG BIT(0)
131 #define TPS65217_DEFPG_LDO1PGM BIT(3)
132 #define TPS65217_DEFPG_LDO2PGM BIT(2)
133 #define TPS65217_DEFPG_PGDLY_MASK 0x03
135 #define TPS65217_DEFDCDCX_XADJX BIT(7)
136 #define TPS65217_DEFDCDCX_DCDC_MASK 0x3F
138 #define TPS65217_DEFSLEW_GO BIT(7)
139 #define TPS65217_DEFSLEW_GODSBL BIT(6)
140 #define TPS65217_DEFSLEW_PFM_EN1 BIT(5)
141 #define TPS65217_DEFSLEW_PFM_EN2 BIT(4)
142 #define TPS65217_DEFSLEW_PFM_EN3 BIT(3)
143 #define TPS65217_DEFSLEW_SLEW_MASK 0x07
145 #define TPS65217_DEFLDO1_LDO1_MASK 0x0F
147 #define TPS65217_DEFLDO2_TRACK BIT(6)
148 #define TPS65217_DEFLDO2_LDO2_MASK 0x3F
150 #define TPS65217_DEFLDO3_LDO3_EN BIT(5)
151 #define TPS65217_DEFLDO3_LDO3_MASK 0x1F
153 #define TPS65217_DEFLDO4_LDO4_EN BIT(5)
154 #define TPS65217_DEFLDO4_LDO4_MASK 0x1F
156 #define TPS65217_ENABLE_LS1_EN BIT(6)
157 #define TPS65217_ENABLE_LS2_EN BIT(5)
158 #define TPS65217_ENABLE_DC1_EN BIT(4)
159 #define TPS65217_ENABLE_DC2_EN BIT(3)
160 #define TPS65217_ENABLE_DC3_EN BIT(2)
161 #define TPS65217_ENABLE_LDO1_EN BIT(1)
162 #define TPS65217_ENABLE_LDO2_EN BIT(0)
164 #define TPS65217_DEFUVLO_UVLOHYS BIT(2)
165 #define TPS65217_DEFUVLO_UVLO_MASK 0x03
167 #define TPS65217_SEQ1_DC1_SEQ_MASK 0xF0
168 #define TPS65217_SEQ1_DC2_SEQ_MASK 0x0F
170 #define TPS65217_SEQ2_DC3_SEQ_MASK 0xF0
171 #define TPS65217_SEQ2_LDO1_SEQ_MASK 0x0F
173 #define TPS65217_SEQ3_LDO2_SEQ_MASK 0xF0
174 #define TPS65217_SEQ3_LDO3_SEQ_MASK 0x0F
176 #define TPS65217_SEQ4_LDO4_SEQ_MASK 0xF0
178 #define TPS65217_SEQ5_DLY1_MASK 0xC0
179 #define TPS65217_SEQ5_DLY2_MASK 0x30
180 #define TPS65217_SEQ5_DLY3_MASK 0x0C
181 #define TPS65217_SEQ5_DLY4_MASK 0x03
183 #define TPS65217_SEQ6_DLY5_MASK 0xC0
184 #define TPS65217_SEQ6_DLY6_MASK 0x30
185 #define TPS65217_SEQ6_SEQUP BIT(2)
186 #define TPS65217_SEQ6_SEQDWN BIT(1)
187 #define TPS65217_SEQ6_INSTDWN BIT(0)
189 #define TPS65217_MAX_REGISTER 0x1E
190 #define TPS65217_PROTECT_NONE 0
191 #define TPS65217_PROTECT_L1 1
192 #define TPS65217_PROTECT_L2 2
207 #define TPS65217_MAX_REG_ID TPS65217_LDO_4
210 #define TPS65217_NUM_DCDC 3
212 #define TPS65217_NUM_LDO 4
214 #define TPS65217_NUM_REGULATOR (TPS65217_NUM_DCDC + TPS65217_NUM_LDO)
292 unsigned int val,
unsigned int level);
294 unsigned int mask,
unsigned int val,
unsigned int level);