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tsi721.h
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1 /*
2  * Tsi721 PCIExpress-to-SRIO bridge definitions
3  *
4  * Copyright 2011, Integrated Device Technology, Inc.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms of the GNU General Public License as published by the Free
8  * Software Foundation; either version 2 of the License, or (at your option)
9  * any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along with
17  * this program; if not, write to the Free Software Foundation, Inc., 59
18  * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  */
20 
21 #ifndef __TSI721_H
22 #define __TSI721_H
23 
24 #define DRV_NAME "tsi721"
25 
26 #define DEFAULT_HOPCOUNT 0xff
27 #define DEFAULT_DESTID 0xff
28 
29 /* PCI device ID */
30 #define PCI_DEVICE_ID_TSI721 0x80ab
31 
32 #define BAR_0 0
33 #define BAR_1 1
34 #define BAR_2 2
35 #define BAR_4 4
36 
37 #define TSI721_PC2SR_BARS 2
38 #define TSI721_PC2SR_WINS 8
39 #define TSI721_PC2SR_ZONES 8
40 #define TSI721_MAINT_WIN 0 /* Window for outbound maintenance requests */
41 #define IDB_QUEUE 0 /* Inbound Doorbell Queue to use */
42 #define IDB_QSIZE 512 /* Inbound Doorbell Queue size */
43 
44 /* Memory space sizes */
45 #define TSI721_REG_SPACE_SIZE (512 * 1024) /* 512K */
46 #define TSI721_DB_WIN_SIZE (16 * 1024 * 1024) /* 16MB */
47 
48 #define RIO_TT_CODE_8 0x00000000
49 #define RIO_TT_CODE_16 0x00000001
50 
51 #define TSI721_DMA_MAXCH 8
52 #define TSI721_DMA_MINSTSSZ 32
53 #define TSI721_DMA_STSBLKSZ 8
54 
55 #define TSI721_SRIO_MAXCH 8
56 
57 #define DBELL_SID(buf) (((u8)buf[2] << 8) | (u8)buf[3])
58 #define DBELL_TID(buf) (((u8)buf[4] << 8) | (u8)buf[5])
59 #define DBELL_INF(buf) (((u8)buf[0] << 8) | (u8)buf[1])
60 
61 #define TSI721_RIO_PW_MSG_SIZE 16 /* Tsi721 saves only 16 bytes of PW msg */
62 
63 /* Register definitions */
64 
65 /*
66  * Registers in PCIe configuration space
67  */
68 
69 #define TSI721_PCIECFG_MSIXTBL 0x0a4
70 #define TSI721_MSIXTBL_OFFSET 0x2c000
71 #define TSI721_PCIECFG_MSIXPBA 0x0a8
72 #define TSI721_MSIXPBA_OFFSET 0x2a000
73 #define TSI721_PCIECFG_EPCTL 0x400
74 
75 #define MAX_READ_REQUEST_SZ_SHIFT 12
76 
77 /*
78  * Event Management Registers
79  */
80 
81 #define TSI721_RIO_EM_INT_STAT 0x10910
82 #define TSI721_RIO_EM_INT_STAT_PW_RX 0x00010000
83 
84 #define TSI721_RIO_EM_INT_ENABLE 0x10914
85 #define TSI721_RIO_EM_INT_ENABLE_PW_RX 0x00010000
86 
87 #define TSI721_RIO_EM_DEV_INT_EN 0x10930
88 #define TSI721_RIO_EM_DEV_INT_EN_INT 0x00000001
89 
90 /*
91  * Port-Write Block Registers
92  */
93 
94 #define TSI721_RIO_PW_CTL 0x10a04
95 #define TSI721_RIO_PW_CTL_PW_TIMER 0xf0000000
96 #define TSI721_RIO_PW_CTL_PWT_DIS (0 << 28)
97 #define TSI721_RIO_PW_CTL_PWT_103 (1 << 28)
98 #define TSI721_RIO_PW_CTL_PWT_205 (1 << 29)
99 #define TSI721_RIO_PW_CTL_PWT_410 (1 << 30)
100 #define TSI721_RIO_PW_CTL_PWT_820 (1 << 31)
101 #define TSI721_RIO_PW_CTL_PWC_MODE 0x01000000
102 #define TSI721_RIO_PW_CTL_PWC_CONT 0x00000000
103 #define TSI721_RIO_PW_CTL_PWC_REL 0x01000000
104 
105 #define TSI721_RIO_PW_RX_STAT 0x10a10
106 #define TSI721_RIO_PW_RX_STAT_WR_SIZE 0x0000f000
107 #define TSI_RIO_PW_RX_STAT_WDPTR 0x00000100
108 #define TSI721_RIO_PW_RX_STAT_PW_SHORT 0x00000008
109 #define TSI721_RIO_PW_RX_STAT_PW_TRUNC 0x00000004
110 #define TSI721_RIO_PW_RX_STAT_PW_DISC 0x00000002
111 #define TSI721_RIO_PW_RX_STAT_PW_VAL 0x00000001
112 
113 #define TSI721_RIO_PW_RX_CAPT(x) (0x10a20 + (x)*4)
114 
115 /*
116  * Inbound Doorbells
117  */
118 
119 #define TSI721_IDB_ENTRY_SIZE 64
120 
121 #define TSI721_IDQ_CTL(x) (0x20000 + (x) * 0x1000)
122 #define TSI721_IDQ_SUSPEND 0x00000002
123 #define TSI721_IDQ_INIT 0x00000001
124 
125 #define TSI721_IDQ_STS(x) (0x20004 + (x) * 0x1000)
126 #define TSI721_IDQ_RUN 0x00200000
127 
128 #define TSI721_IDQ_MASK(x) (0x20008 + (x) * 0x1000)
129 #define TSI721_IDQ_MASK_MASK 0xffff0000
130 #define TSI721_IDQ_MASK_PATT 0x0000ffff
131 
132 #define TSI721_IDQ_RP(x) (0x2000c + (x) * 0x1000)
133 #define TSI721_IDQ_RP_PTR 0x0007ffff
134 
135 #define TSI721_IDQ_WP(x) (0x20010 + (x) * 0x1000)
136 #define TSI721_IDQ_WP_PTR 0x0007ffff
137 
138 #define TSI721_IDQ_BASEL(x) (0x20014 + (x) * 0x1000)
139 #define TSI721_IDQ_BASEL_ADDR 0xffffffc0
140 #define TSI721_IDQ_BASEU(x) (0x20018 + (x) * 0x1000)
141 #define TSI721_IDQ_SIZE(x) (0x2001c + (x) * 0x1000)
142 #define TSI721_IDQ_SIZE_VAL(size) (__fls(size) - 4)
143 #define TSI721_IDQ_SIZE_MIN 512
144 #define TSI721_IDQ_SIZE_MAX (512 * 1024)
145 
146 #define TSI721_SR_CHINT(x) (0x20040 + (x) * 0x1000)
147 #define TSI721_SR_CHINTE(x) (0x20044 + (x) * 0x1000)
148 #define TSI721_SR_CHINTSET(x) (0x20048 + (x) * 0x1000)
149 #define TSI721_SR_CHINT_ODBOK 0x00000020
150 #define TSI721_SR_CHINT_IDBQRCV 0x00000010
151 #define TSI721_SR_CHINT_SUSP 0x00000008
152 #define TSI721_SR_CHINT_ODBTO 0x00000004
153 #define TSI721_SR_CHINT_ODBRTRY 0x00000002
154 #define TSI721_SR_CHINT_ODBERR 0x00000001
155 #define TSI721_SR_CHINT_ALL 0x0000003f
156 
157 #define TSI721_IBWIN_NUM 8
158 
159 #define TSI721_IBWIN_LB(x) (0x29000 + (x) * 0x20)
160 #define TSI721_IBWIN_LB_BA 0xfffff000
161 #define TSI721_IBWIN_LB_WEN 0x00000001
162 
163 #define TSI721_IBWIN_UB(x) (0x29004 + (x) * 0x20)
164 #define TSI721_IBWIN_SZ(x) (0x29008 + (x) * 0x20)
165 #define TSI721_IBWIN_SZ_SIZE 0x00001f00
166 #define TSI721_IBWIN_SIZE(size) (__fls(size) - 12)
167 
168 #define TSI721_IBWIN_TLA(x) (0x2900c + (x) * 0x20)
169 #define TSI721_IBWIN_TLA_ADD 0xfffff000
170 #define TSI721_IBWIN_TUA(x) (0x29010 + (x) * 0x20)
171 
172 #define TSI721_SR2PC_GEN_INTE 0x29800
173 #define TSI721_SR2PC_PWE 0x29804
174 #define TSI721_SR2PC_GEN_INT 0x29808
175 
176 #define TSI721_DEV_INTE 0x29840
177 #define TSI721_DEV_INT 0x29844
178 #define TSI721_DEV_INTSET 0x29848
179 #define TSI721_DEV_INT_BDMA_CH 0x00002000
180 #define TSI721_DEV_INT_BDMA_NCH 0x00001000
181 #define TSI721_DEV_INT_SMSG_CH 0x00000800
182 #define TSI721_DEV_INT_SMSG_NCH 0x00000400
183 #define TSI721_DEV_INT_SR2PC_CH 0x00000200
184 #define TSI721_DEV_INT_SRIO 0x00000020
185 
186 #define TSI721_DEV_CHAN_INTE 0x2984c
187 #define TSI721_DEV_CHAN_INT 0x29850
188 
189 #define TSI721_INT_SR2PC_CHAN_M 0xff000000
190 #define TSI721_INT_SR2PC_CHAN(x) (1 << (24 + (x)))
191 #define TSI721_INT_IMSG_CHAN_M 0x00ff0000
192 #define TSI721_INT_IMSG_CHAN(x) (1 << (16 + (x)))
193 #define TSI721_INT_OMSG_CHAN_M 0x0000ff00
194 #define TSI721_INT_OMSG_CHAN(x) (1 << (8 + (x)))
195 #define TSI721_INT_BDMA_CHAN_M 0x000000ff
196 #define TSI721_INT_BDMA_CHAN(x) (1 << (x))
197 
198 /*
199  * PC2SR block registers
200  */
201 #define TSI721_OBWIN_NUM TSI721_PC2SR_WINS
202 
203 #define TSI721_OBWINLB(x) (0x40000 + (x) * 0x20)
204 #define TSI721_OBWINLB_BA 0xffff8000
205 #define TSI721_OBWINLB_WEN 0x00000001
206 
207 #define TSI721_OBWINUB(x) (0x40004 + (x) * 0x20)
208 
209 #define TSI721_OBWINSZ(x) (0x40008 + (x) * 0x20)
210 #define TSI721_OBWINSZ_SIZE 0x00001f00
211 #define TSI721_OBWIN_SIZE(size) (__fls(size) - 15)
212 
213 #define TSI721_ZONE_SEL 0x41300
214 #define TSI721_ZONE_SEL_RD_WRB 0x00020000
215 #define TSI721_ZONE_SEL_GO 0x00010000
216 #define TSI721_ZONE_SEL_WIN 0x00000038
217 #define TSI721_ZONE_SEL_ZONE 0x00000007
218 
219 #define TSI721_LUT_DATA0 0x41304
220 #define TSI721_LUT_DATA0_ADD 0xfffff000
221 #define TSI721_LUT_DATA0_RDTYPE 0x00000f00
222 #define TSI721_LUT_DATA0_NREAD 0x00000100
223 #define TSI721_LUT_DATA0_MNTRD 0x00000200
224 #define TSI721_LUT_DATA0_RDCRF 0x00000020
225 #define TSI721_LUT_DATA0_WRCRF 0x00000010
226 #define TSI721_LUT_DATA0_WRTYPE 0x0000000f
227 #define TSI721_LUT_DATA0_NWR 0x00000001
228 #define TSI721_LUT_DATA0_MNTWR 0x00000002
229 #define TSI721_LUT_DATA0_NWR_R 0x00000004
230 
231 #define TSI721_LUT_DATA1 0x41308
232 
233 #define TSI721_LUT_DATA2 0x4130c
234 #define TSI721_LUT_DATA2_HC 0xff000000
235 #define TSI721_LUT_DATA2_ADD65 0x000c0000
236 #define TSI721_LUT_DATA2_TT 0x00030000
237 #define TSI721_LUT_DATA2_DSTID 0x0000ffff
238 
239 #define TSI721_PC2SR_INTE 0x41310
240 
241 #define TSI721_DEVCTL 0x48004
242 #define TSI721_DEVCTL_SRBOOT_CMPL 0x00000004
243 
244 #define TSI721_I2C_INT_ENABLE 0x49120
245 
246 /*
247  * Block DMA Engine Registers
248  * x = 0..7
249  */
250 
251 #define TSI721_DMAC_BASE(x) (0x51000 + (x) * 0x1000)
252 
253 #define TSI721_DMAC_DWRCNT 0x000
254 #define TSI721_DMAC_DRDCNT 0x004
255 
256 #define TSI721_DMAC_CTL 0x008
257 #define TSI721_DMAC_CTL_SUSP 0x00000002
258 #define TSI721_DMAC_CTL_INIT 0x00000001
259 
260 #define TSI721_DMAC_INT 0x00c
261 #define TSI721_DMAC_INT_STFULL 0x00000010
262 #define TSI721_DMAC_INT_DONE 0x00000008
263 #define TSI721_DMAC_INT_SUSP 0x00000004
264 #define TSI721_DMAC_INT_ERR 0x00000002
265 #define TSI721_DMAC_INT_IOFDONE 0x00000001
266 #define TSI721_DMAC_INT_ALL 0x0000001f
267 
268 #define TSI721_DMAC_INTSET 0x010
269 
270 #define TSI721_DMAC_STS 0x014
271 #define TSI721_DMAC_STS_ABORT 0x00400000
272 #define TSI721_DMAC_STS_RUN 0x00200000
273 #define TSI721_DMAC_STS_CS 0x001f0000
274 
275 #define TSI721_DMAC_INTE 0x018
276 
277 #define TSI721_DMAC_DPTRL 0x024
278 #define TSI721_DMAC_DPTRL_MASK 0xffffffe0
279 
280 #define TSI721_DMAC_DPTRH 0x028
281 
282 #define TSI721_DMAC_DSBL 0x02c
283 #define TSI721_DMAC_DSBL_MASK 0xffffffc0
284 
285 #define TSI721_DMAC_DSBH 0x030
286 
287 #define TSI721_DMAC_DSSZ 0x034
288 #define TSI721_DMAC_DSSZ_SIZE_M 0x0000000f
289 #define TSI721_DMAC_DSSZ_SIZE(size) (__fls(size) - 4)
290 
291 #define TSI721_DMAC_DSRP 0x038
292 #define TSI721_DMAC_DSRP_MASK 0x0007ffff
293 
294 #define TSI721_DMAC_DSWP 0x03c
295 #define TSI721_DMAC_DSWP_MASK 0x0007ffff
296 
297 #define TSI721_BDMA_INTE 0x5f000
298 
299 /*
300  * Messaging definitions
301  */
302 #define TSI721_MSG_BUFFER_SIZE RIO_MAX_MSG_SIZE
303 #define TSI721_MSG_MAX_SIZE RIO_MAX_MSG_SIZE
304 #define TSI721_IMSG_MAXCH 8
305 #define TSI721_IMSG_CHNUM TSI721_IMSG_MAXCH
306 #define TSI721_IMSGD_MIN_RING_SIZE 32
307 #define TSI721_IMSGD_RING_SIZE 512
308 
309 #define TSI721_OMSG_CHNUM 4 /* One channel per MBOX */
310 #define TSI721_OMSGD_MIN_RING_SIZE 32
311 #define TSI721_OMSGD_RING_SIZE 512
312 
313 /*
314  * Outbound Messaging Engine Registers
315  * x = 0..7
316  */
317 
318 #define TSI721_OBDMAC_DWRCNT(x) (0x61000 + (x) * 0x1000)
319 
320 #define TSI721_OBDMAC_DRDCNT(x) (0x61004 + (x) * 0x1000)
321 
322 #define TSI721_OBDMAC_CTL(x) (0x61008 + (x) * 0x1000)
323 #define TSI721_OBDMAC_CTL_MASK 0x00000007
324 #define TSI721_OBDMAC_CTL_RETRY_THR 0x00000004
325 #define TSI721_OBDMAC_CTL_SUSPEND 0x00000002
326 #define TSI721_OBDMAC_CTL_INIT 0x00000001
327 
328 #define TSI721_OBDMAC_INT(x) (0x6100c + (x) * 0x1000)
329 #define TSI721_OBDMAC_INTSET(x) (0x61010 + (x) * 0x1000)
330 #define TSI721_OBDMAC_INTE(x) (0x61018 + (x) * 0x1000)
331 #define TSI721_OBDMAC_INT_MASK 0x0000001F
332 #define TSI721_OBDMAC_INT_ST_FULL 0x00000010
333 #define TSI721_OBDMAC_INT_DONE 0x00000008
334 #define TSI721_OBDMAC_INT_SUSPENDED 0x00000004
335 #define TSI721_OBDMAC_INT_ERROR 0x00000002
336 #define TSI721_OBDMAC_INT_IOF_DONE 0x00000001
337 #define TSI721_OBDMAC_INT_ALL TSI721_OBDMAC_INT_MASK
338 
339 #define TSI721_OBDMAC_STS(x) (0x61014 + (x) * 0x1000)
340 #define TSI721_OBDMAC_STS_MASK 0x007f0000
341 #define TSI721_OBDMAC_STS_ABORT 0x00400000
342 #define TSI721_OBDMAC_STS_RUN 0x00200000
343 #define TSI721_OBDMAC_STS_CS 0x001f0000
344 
345 #define TSI721_OBDMAC_PWE(x) (0x6101c + (x) * 0x1000)
346 #define TSI721_OBDMAC_PWE_MASK 0x00000002
347 #define TSI721_OBDMAC_PWE_ERROR_EN 0x00000002
348 
349 #define TSI721_OBDMAC_DPTRL(x) (0x61020 + (x) * 0x1000)
350 #define TSI721_OBDMAC_DPTRL_MASK 0xfffffff0
351 
352 #define TSI721_OBDMAC_DPTRH(x) (0x61024 + (x) * 0x1000)
353 #define TSI721_OBDMAC_DPTRH_MASK 0xffffffff
354 
355 #define TSI721_OBDMAC_DSBL(x) (0x61040 + (x) * 0x1000)
356 #define TSI721_OBDMAC_DSBL_MASK 0xffffffc0
357 
358 #define TSI721_OBDMAC_DSBH(x) (0x61044 + (x) * 0x1000)
359 #define TSI721_OBDMAC_DSBH_MASK 0xffffffff
360 
361 #define TSI721_OBDMAC_DSSZ(x) (0x61048 + (x) * 0x1000)
362 #define TSI721_OBDMAC_DSSZ_MASK 0x0000000f
363 
364 #define TSI721_OBDMAC_DSRP(x) (0x6104c + (x) * 0x1000)
365 #define TSI721_OBDMAC_DSRP_MASK 0x0007ffff
366 
367 #define TSI721_OBDMAC_DSWP(x) (0x61050 + (x) * 0x1000)
368 #define TSI721_OBDMAC_DSWP_MASK 0x0007ffff
369 
370 #define TSI721_RQRPTO 0x60010
371 #define TSI721_RQRPTO_MASK 0x00ffffff
372 #define TSI721_RQRPTO_VAL 400 /* Response TO value */
373 
374 /*
375  * Inbound Messaging Engine Registers
376  * x = 0..7
377  */
378 
379 #define TSI721_IB_DEVID_GLOBAL 0xffff
380 #define TSI721_IBDMAC_FQBL(x) (0x61200 + (x) * 0x1000)
381 #define TSI721_IBDMAC_FQBL_MASK 0xffffffc0
382 
383 #define TSI721_IBDMAC_FQBH(x) (0x61204 + (x) * 0x1000)
384 #define TSI721_IBDMAC_FQBH_MASK 0xffffffff
385 
386 #define TSI721_IBDMAC_FQSZ_ENTRY_INX TSI721_IMSGD_RING_SIZE
387 #define TSI721_IBDMAC_FQSZ(x) (0x61208 + (x) * 0x1000)
388 #define TSI721_IBDMAC_FQSZ_MASK 0x0000000f
389 
390 #define TSI721_IBDMAC_FQRP(x) (0x6120c + (x) * 0x1000)
391 #define TSI721_IBDMAC_FQRP_MASK 0x0007ffff
392 
393 #define TSI721_IBDMAC_FQWP(x) (0x61210 + (x) * 0x1000)
394 #define TSI721_IBDMAC_FQWP_MASK 0x0007ffff
395 
396 #define TSI721_IBDMAC_FQTH(x) (0x61214 + (x) * 0x1000)
397 #define TSI721_IBDMAC_FQTH_MASK 0x0007ffff
398 
399 #define TSI721_IB_DEVID 0x60020
400 #define TSI721_IB_DEVID_MASK 0x0000ffff
401 
402 #define TSI721_IBDMAC_CTL(x) (0x61240 + (x) * 0x1000)
403 #define TSI721_IBDMAC_CTL_MASK 0x00000003
404 #define TSI721_IBDMAC_CTL_SUSPEND 0x00000002
405 #define TSI721_IBDMAC_CTL_INIT 0x00000001
406 
407 #define TSI721_IBDMAC_STS(x) (0x61244 + (x) * 0x1000)
408 #define TSI721_IBDMAC_STS_MASK 0x007f0000
409 #define TSI721_IBSMAC_STS_ABORT 0x00400000
410 #define TSI721_IBSMAC_STS_RUN 0x00200000
411 #define TSI721_IBSMAC_STS_CS 0x001f0000
412 
413 #define TSI721_IBDMAC_INT(x) (0x61248 + (x) * 0x1000)
414 #define TSI721_IBDMAC_INTSET(x) (0x6124c + (x) * 0x1000)
415 #define TSI721_IBDMAC_INTE(x) (0x61250 + (x) * 0x1000)
416 #define TSI721_IBDMAC_INT_MASK 0x0000100f
417 #define TSI721_IBDMAC_INT_SRTO 0x00001000
418 #define TSI721_IBDMAC_INT_SUSPENDED 0x00000008
419 #define TSI721_IBDMAC_INT_PC_ERROR 0x00000004
420 #define TSI721_IBDMAC_INT_FQ_LOW 0x00000002
421 #define TSI721_IBDMAC_INT_DQ_RCV 0x00000001
422 #define TSI721_IBDMAC_INT_ALL TSI721_IBDMAC_INT_MASK
423 
424 #define TSI721_IBDMAC_PWE(x) (0x61254 + (x) * 0x1000)
425 #define TSI721_IBDMAC_PWE_MASK 0x00001700
426 #define TSI721_IBDMAC_PWE_SRTO 0x00001000
427 #define TSI721_IBDMAC_PWE_ILL_FMT 0x00000400
428 #define TSI721_IBDMAC_PWE_ILL_DEC 0x00000200
429 #define TSI721_IBDMAC_PWE_IMP_SP 0x00000100
430 
431 #define TSI721_IBDMAC_DQBL(x) (0x61300 + (x) * 0x1000)
432 #define TSI721_IBDMAC_DQBL_MASK 0xffffffc0
433 #define TSI721_IBDMAC_DQBL_ADDR 0xffffffc0
434 
435 #define TSI721_IBDMAC_DQBH(x) (0x61304 + (x) * 0x1000)
436 #define TSI721_IBDMAC_DQBH_MASK 0xffffffff
437 
438 #define TSI721_IBDMAC_DQRP(x) (0x61308 + (x) * 0x1000)
439 #define TSI721_IBDMAC_DQRP_MASK 0x0007ffff
440 
441 #define TSI721_IBDMAC_DQWR(x) (0x6130c + (x) * 0x1000)
442 #define TSI721_IBDMAC_DQWR_MASK 0x0007ffff
443 
444 #define TSI721_IBDMAC_DQSZ(x) (0x61314 + (x) * 0x1000)
445 #define TSI721_IBDMAC_DQSZ_MASK 0x0000000f
446 
447 /*
448  * Messaging Engine Interrupts
449  */
450 
451 #define TSI721_SMSG_PWE 0x6a004
452 
453 #define TSI721_SMSG_INTE 0x6a000
454 #define TSI721_SMSG_INT 0x6a008
455 #define TSI721_SMSG_INTSET 0x6a010
456 #define TSI721_SMSG_INT_MASK 0x0086ffff
457 #define TSI721_SMSG_INT_UNS_RSP 0x00800000
458 #define TSI721_SMSG_INT_ECC_NCOR 0x00040000
459 #define TSI721_SMSG_INT_ECC_COR 0x00020000
460 #define TSI721_SMSG_INT_ECC_NCOR_CH 0x0000ff00
461 #define TSI721_SMSG_INT_ECC_COR_CH 0x000000ff
462 
463 #define TSI721_SMSG_ECC_LOG 0x6a014
464 #define TSI721_SMSG_ECC_LOG_MASK 0x00070007
465 #define TSI721_SMSG_ECC_LOG_ECC_NCOR_M 0x00070000
466 #define TSI721_SMSG_ECC_LOG_ECC_COR_M 0x00000007
467 
468 #define TSI721_RETRY_GEN_CNT 0x6a100
469 #define TSI721_RETRY_GEN_CNT_MASK 0xffffffff
470 
471 #define TSI721_RETRY_RX_CNT 0x6a104
472 #define TSI721_RETRY_RX_CNT_MASK 0xffffffff
473 
474 #define TSI721_SMSG_ECC_COR_LOG(x) (0x6a300 + (x) * 4)
475 #define TSI721_SMSG_ECC_COR_LOG_MASK 0x000000ff
476 
477 #define TSI721_SMSG_ECC_NCOR(x) (0x6a340 + (x) * 4)
478 #define TSI721_SMSG_ECC_NCOR_MASK 0x000000ff
479 
480 /*
481  * Block DMA Descriptors
482  */
483 
486 
487 #define TSI721_DMAD_DEVID 0x0000ffff
488 #define TSI721_DMAD_CRF 0x00010000
489 #define TSI721_DMAD_PRIO 0x00060000
490 #define TSI721_DMAD_RTYPE 0x00780000
491 #define TSI721_DMAD_IOF 0x08000000
492 #define TSI721_DMAD_DTYPE 0xe0000000
493 
495 
496 #define TSI721_DMAD_BCOUNT1 0x03ffffff /* if DTYPE == 1 */
497 #define TSI721_DMAD_BCOUNT2 0x0000000f /* if DTYPE == 2 */
498 #define TSI721_DMAD_TT 0x0c000000
499 #define TSI721_DMAD_RADDR0 0xc0000000
500 
501  union {
502  __le32 raddr_lo; /* if DTYPE == (1 || 2) */
503  __le32 next_lo; /* if DTYPE == 3 */
504  };
505 
506 #define TSI721_DMAD_CFGOFF 0x00ffffff
507 #define TSI721_DMAD_HOPCNT 0xff000000
508 
509  union {
510  __le32 raddr_hi; /* if DTYPE == (1 || 2) */
511  __le32 next_hi; /* if DTYPE == 3 */
512  };
513 
514  union {
515  struct { /* if DTYPE == 1 */
520  } t1;
521  __le32 data[4]; /* if DTYPE == 2 */
522  u32 reserved[4]; /* if DTYPE == 3 */
523  };
524 } __aligned(32);
526 /*
527  * Inbound Messaging Descriptor
528  */
532 #define TSI721_IMD_DEVID 0x0000ffff
533 #define TSI721_IMD_CRF 0x00010000
534 #define TSI721_IMD_PRIO 0x00060000
535 #define TSI721_IMD_TT 0x00180000
536 #define TSI721_IMD_DTYPE 0xe0000000
540 #define TSI721_IMD_BCOUNT 0x00000ff8
541 #define TSI721_IMD_SSIZE 0x0000f000
542 #define TSI721_IMD_LETER 0x00030000
543 #define TSI721_IMD_XMBOX 0x003c0000
544 #define TSI721_IMD_MBOX 0x00c00000
545 #define TSI721_IMD_CS 0x78000000
546 #define TSI721_IMD_HO 0x80000000
552 } __aligned(64);
553 
554 /*
555  * Outbound Messaging Descriptor
556  */
560 #define TSI721_OMD_DEVID 0x0000ffff
561 #define TSI721_OMD_CRF 0x00010000
562 #define TSI721_OMD_PRIO 0x00060000
563 #define TSI721_OMD_IOF 0x08000000
564 #define TSI721_OMD_DTYPE 0xe0000000
565 #define TSI721_OMD_RSRVD 0x17f80000
569 #define TSI721_OMD_BCOUNT 0x00000ff8
570 #define TSI721_OMD_SSIZE 0x0000f000
571 #define TSI721_OMD_LETER 0x00030000
572 #define TSI721_OMD_XMBOX 0x003c0000
573 #define TSI721_OMD_MBOX 0x00c00000
574 #define TSI721_OMD_TT 0x0c000000
575 
576  union {
577  __le32 bufptr_lo; /* if DTYPE == 4 */
578  __le32 next_lo; /* if DTYPE == 5 */
579  };
580 
581  union {
582  __le32 bufptr_hi; /* if DTYPE == 4 */
583  __le32 next_hi; /* if DTYPE == 5 */
584  };
585 
586 } __aligned(16);
587 
590 } __aligned(64);
593  union {
595  struct {
598  } da32;
599  } stat[8];
600 } __aligned(64);
602 /* Descriptor types for BDMA and Messaging blocks */
603 enum dma_dtype {
604  DTYPE1 = 1, /* Data Transfer DMA Descriptor */
605  DTYPE2 = 2, /* Immediate Data Transfer DMA Descriptor */
606  DTYPE3 = 3, /* Block Pointer DMA Descriptor */
607  DTYPE4 = 4, /* Outbound Msg DMA Descriptor */
608  DTYPE5 = 5, /* OB Messaging Block Pointer Descriptor */
609  DTYPE6 = 6 /* Inbound Messaging Descriptor */
610 };
611 
612 enum dma_rtype {
613  NREAD = 0,
617  MAINT_RD = 4,
619 };
620 
621 /*
622  * mport Driver Definitions
623  */
624 #define TSI721_DMA_CHNUM TSI721_DMA_MAXCH
625 
626 #define TSI721_DMACH_MAINT 0 /* DMA channel for maint requests */
627 #define TSI721_DMACH_MAINT_NBD 32 /* Number of BDs for maint requests */
628 
629 #define TSI721_DMACH_DMA 1 /* DMA channel for data transfers */
630 
631 #define MSG_DMA_ENTRY_INX_TO_SIZE(x) ((0x10 << (x)) & 0xFFFF0)
632 
634  SMSG_INT_NONE = 0x00000000,
635  SMSG_INT_ECC_COR_CH = 0x000000ff,
636  SMSG_INT_ECC_NCOR_CH = 0x0000ff00,
637  SMSG_INT_ECC_COR = 0x00020000,
638  SMSG_INT_ECC_NCOR = 0x00040000,
639  SMSG_INT_UNS_RSP = 0x00800000,
640  SMSG_INT_ALL = 0x0006ffff
641 };
642 
643 /* Structures */
644 
645 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
646 
647 struct tsi721_tx_desc {
648  struct dma_async_tx_descriptor txd;
649  struct tsi721_dma_desc *hw_desc;
650  u16 destid;
651  /* low 64-bits of 66-bit RIO address */
652  u64 rio_addr;
653  /* upper 2-bits of 66-bit RIO address */
654  u8 rio_addr_u;
655  bool interrupt;
656  struct list_head desc_node;
657  struct list_head tx_list;
658 };
659 
660 struct tsi721_bdma_chan {
661  int id;
662  void __iomem *regs;
663  int bd_num; /* number of buffer descriptors */
664  void *bd_base; /* start of DMA descriptors */
665  dma_addr_t bd_phys;
666  void *sts_base; /* start of DMA BD status FIFO */
667  dma_addr_t sts_phys;
668  int sts_size;
669  u32 sts_rdptr;
670  u32 wr_count;
671  u32 wr_count_next;
672 
673  struct dma_chan dchan;
674  struct tsi721_tx_desc *tx_desc;
676  struct list_head active_list;
677  struct list_head queue;
678  struct list_head free_list;
679  dma_cookie_t completed_cookie;
680  struct tasklet_struct tasklet;
681 };
682 
683 #endif /* CONFIG_RAPIDIO_DMA_ENGINE */
684 
686  int ch_id; /* BDMA channel number */
687  int bd_num; /* number of buffer descriptors */
688  void *bd_base; /* start of DMA descriptors */
690  void *sts_base; /* start of DMA BD status FIFO */
692  int sts_size;
693 };
694 
697  /* VA/PA of data buffers for incoming messages */
698  void *buf_base;
700  /* VA/PA of circular free buffer list */
701  void *imfq_base;
703  /* VA/PA of Inbound message descriptors */
704  void *imd_base;
706  /* Inbound Queue buffer pointers */
708 
710  void *dev_id;
714 };
715 
718  /* VA/PA of OB Msg descriptors */
719  void *omd_base;
721  /* VA/PA of OB Msg data buffers */
724  /* VA/PA of OB Msg descriptor status FIFO */
725  void *sts_base;
727  u32 sts_size; /* # of allocated status entries */
729 
731  void *dev_id;
734 };
735 
737  TSI721_USING_MSI = (1 << 0),
738  TSI721_USING_MSIX = (1 << 1),
739  TSI721_IMSGID_SET = (1 << 2),
740 };
741 
742 #ifdef CONFIG_PCI_MSI
743 /*
744  * MSI-X Table Entries (0 ... 69)
745  */
746 #define TSI721_MSIX_DMACH_DONE(x) (0 + (x))
747 #define TSI721_MSIX_DMACH_INT(x) (8 + (x))
748 #define TSI721_MSIX_BDMA_INT 16
749 #define TSI721_MSIX_OMSG_DONE(x) (17 + (x))
750 #define TSI721_MSIX_OMSG_INT(x) (25 + (x))
751 #define TSI721_MSIX_IMSG_DQ_RCV(x) (33 + (x))
752 #define TSI721_MSIX_IMSG_INT(x) (41 + (x))
753 #define TSI721_MSIX_MSG_INT 49
754 #define TSI721_MSIX_SR2PC_IDBQ_RCV(x) (50 + (x))
755 #define TSI721_MSIX_SR2PC_CH_INT(x) (58 + (x))
756 #define TSI721_MSIX_SR2PC_INT 66
757 #define TSI721_MSIX_PC2SR_INT 67
758 #define TSI721_MSIX_SRIO_MAC_INT 68
759 #define TSI721_MSIX_I2C_INT 69
760 
761 /* MSI-X vector and init table entry indexes */
762 enum tsi721_msix_vect {
763  TSI721_VECT_IDB,
764  TSI721_VECT_PWRX, /* PW_RX is part of SRIO MAC Interrupt reporting */
765  TSI721_VECT_OMB0_DONE,
766  TSI721_VECT_OMB1_DONE,
767  TSI721_VECT_OMB2_DONE,
768  TSI721_VECT_OMB3_DONE,
769  TSI721_VECT_OMB0_INT,
770  TSI721_VECT_OMB1_INT,
771  TSI721_VECT_OMB2_INT,
772  TSI721_VECT_OMB3_INT,
773  TSI721_VECT_IMB0_RCV,
774  TSI721_VECT_IMB1_RCV,
775  TSI721_VECT_IMB2_RCV,
776  TSI721_VECT_IMB3_RCV,
777  TSI721_VECT_IMB0_INT,
778  TSI721_VECT_IMB1_INT,
779  TSI721_VECT_IMB2_INT,
780  TSI721_VECT_IMB3_INT,
781 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
782  TSI721_VECT_DMA0_DONE,
783  TSI721_VECT_DMA1_DONE,
784  TSI721_VECT_DMA2_DONE,
785  TSI721_VECT_DMA3_DONE,
786  TSI721_VECT_DMA4_DONE,
787  TSI721_VECT_DMA5_DONE,
788  TSI721_VECT_DMA6_DONE,
789  TSI721_VECT_DMA7_DONE,
790  TSI721_VECT_DMA0_INT,
791  TSI721_VECT_DMA1_INT,
792  TSI721_VECT_DMA2_INT,
793  TSI721_VECT_DMA3_INT,
794  TSI721_VECT_DMA4_INT,
795  TSI721_VECT_DMA5_INT,
796  TSI721_VECT_DMA6_INT,
797  TSI721_VECT_DMA7_INT,
798 #endif /* CONFIG_RAPIDIO_DMA_ENGINE */
799  TSI721_VECT_MAX
800 };
801 
802 #define IRQ_DEVICE_NAME_MAX 64
803 
804 struct msix_irq {
805  u16 vector;
806  char irq_name[IRQ_DEVICE_NAME_MAX];
807 };
808 #endif /* CONFIG_PCI_MSI */
809 
811  struct pci_dev *pdev;
812  struct rio_mport *mport;
814  void __iomem *regs;
815 #ifdef CONFIG_PCI_MSI
816  struct msix_irq msix[TSI721_VECT_MAX];
817 #endif
818  /* Doorbells */
820  void *idb_base;
824 
825  /* Inbound Port-Write */
827  struct kfifo pw_fifo;
830 
831  /* BDMA Engine */
832  struct tsi721_bdma_maint mdma; /* Maintenance rd/wr request channel */
833 
834 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
835  struct tsi721_bdma_chan bdma[TSI721_DMA_CHNUM];
836 #endif
837 
838  /* Inbound Messaging */
841 
842  /* Outbound Messaging */
845 };
846 
847 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
848 extern void tsi721_bdma_handler(struct tsi721_bdma_chan *bdma_chan);
849 extern int __devinit tsi721_register_dma(struct tsi721_device *priv);
850 #endif
851 
852 #endif