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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Data Structures | |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | gdth_pci_str |
| struct | gdth_ha_str |
| struct | gdth_ha_str::gdth_cmndinfo |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
| struct | __attribute__ |
Macros | |
| #define | TRUE 1 |
| #define | FALSE 0 |
| #define | GDTH_VERSION_STR "3.05" |
| #define | GDTH_VERSION 3 |
| #define | GDTH_SUBVERSION 5 |
| #define | PROTOCOL_VERSION 1 |
| #define | OEM_ID_ICP 0x941c |
| #define | OEM_ID_INTEL 0x8000 |
| #define | GDT_ISA 0x01 /* ISA controller */ |
| #define | GDT_EISA 0x02 /* EISA controller */ |
| #define | GDT_PCI 0x03 /* PCI controller */ |
| #define | GDT_PCINEW 0x04 /* new PCI controller */ |
| #define | GDT_PCIMPR 0x05 /* PCI MPR controller */ |
| #define | GDT3_ID 0x0130941c /* GDT3000/3020 */ |
| #define | GDT3A_ID 0x0230941c /* GDT3000A/3020A/3050A */ |
| #define | GDT3B_ID 0x0330941c /* GDT3000B/3010A */ |
| #define | GDT2_ID 0x0120941c /* GDT2000/2020 */ |
| #define | PCI_DEVICE_ID_VORTEX_GDT60x0 0 /* GDT6000/6020/6050 */ |
| #define | PCI_DEVICE_ID_VORTEX_GDT6000B 1 /* GDT6000B/6010 */ |
| #define | PCI_DEVICE_ID_VORTEX_GDT6x10 2 /* GDT6110/6510 */ |
| #define | PCI_DEVICE_ID_VORTEX_GDT6x20 3 /* GDT6120/6520 */ |
| #define | PCI_DEVICE_ID_VORTEX_GDT6530 4 /* GDT6530 */ |
| #define | PCI_DEVICE_ID_VORTEX_GDT6550 5 /* GDT6550 */ |
| #define | PCI_DEVICE_ID_VORTEX_GDT6x17 6 /* GDT6117/6517 */ |
| #define | PCI_DEVICE_ID_VORTEX_GDT6x27 7 /* GDT6127/6527 */ |
| #define | PCI_DEVICE_ID_VORTEX_GDT6537 8 /* GDT6537 */ |
| #define | PCI_DEVICE_ID_VORTEX_GDT6557 9 /* GDT6557/6557-ECC */ |
| #define | PCI_DEVICE_ID_VORTEX_GDT6x15 10 /* GDT6115/6515 */ |
| #define | PCI_DEVICE_ID_VORTEX_GDT6x25 11 /* GDT6125/6525 */ |
| #define | PCI_DEVICE_ID_VORTEX_GDT6535 12 /* GDT6535 */ |
| #define | PCI_DEVICE_ID_VORTEX_GDT6555 13 /* GDT6555/6555-ECC */ |
| #define | PCI_DEVICE_ID_VORTEX_GDT6x17RP 0x100 /* GDT6117RP/GDT6517RP */ |
| #define | PCI_DEVICE_ID_VORTEX_GDT6x27RP 0x101 /* GDT6127RP/GDT6527RP */ |
| #define | PCI_DEVICE_ID_VORTEX_GDT6537RP 0x102 /* GDT6537RP */ |
| #define | PCI_DEVICE_ID_VORTEX_GDT6557RP 0x103 /* GDT6557RP */ |
| #define | PCI_DEVICE_ID_VORTEX_GDT6x11RP 0x104 /* GDT6111RP/GDT6511RP */ |
| #define | PCI_DEVICE_ID_VORTEX_GDT6x21RP 0x105 /* GDT6121RP/GDT6521RP */ |
| #define | PCI_DEVICE_ID_VORTEX_GDT6x17RD 0x110 /* GDT6117RD/GDT6517RD */ |
| #define | PCI_DEVICE_ID_VORTEX_GDT6x27RD 0x111 /* GDT6127RD/GDT6527RD */ |
| #define | PCI_DEVICE_ID_VORTEX_GDT6537RD 0x112 /* GDT6537RD */ |
| #define | PCI_DEVICE_ID_VORTEX_GDT6557RD 0x113 /* GDT6557RD */ |
| #define | PCI_DEVICE_ID_VORTEX_GDT6x11RD 0x114 /* GDT6111RD/GDT6511RD */ |
| #define | PCI_DEVICE_ID_VORTEX_GDT6x21RD 0x115 /* GDT6121RD/GDT6521RD */ |
| #define | PCI_DEVICE_ID_VORTEX_GDT6x18RD |
| #define | PCI_DEVICE_ID_VORTEX_GDT6x28RD |
| #define | PCI_DEVICE_ID_VORTEX_GDT6x38RD 0x11A /* GDT6538RD/GDT6638RD */ |
| #define | PCI_DEVICE_ID_VORTEX_GDT6x58RD 0x11B /* GDT6558RD/GDT6658RD */ |
| #define | PCI_DEVICE_ID_VORTEX_GDT7x18RN |
| #define | PCI_DEVICE_ID_VORTEX_GDT7x28RN |
| #define | PCI_DEVICE_ID_VORTEX_GDT7x38RN 0x16A /* GDT7538RN/GDT7638RN */ |
| #define | PCI_DEVICE_ID_VORTEX_GDT7x58RN 0x16B /* GDT7558RN/GDT7658RN */ |
| #define | PCI_DEVICE_ID_VORTEX_GDT6x19RD 0x210 /* GDT6519RD/GDT6619RD */ |
| #define | PCI_DEVICE_ID_VORTEX_GDT6x29RD 0x211 /* GDT6529RD/GDT6629RD */ |
| #define | PCI_DEVICE_ID_VORTEX_GDT7x19RN 0x260 /* GDT7519RN/GDT7619RN */ |
| #define | PCI_DEVICE_ID_VORTEX_GDT7x29RN 0x261 /* GDT7529RN/GDT7629RN */ |
| #define | PCI_DEVICE_ID_VORTEX_GDTMAXRP 0x2ff |
| #define | PCI_DEVICE_ID_VORTEX_GDTNEWRX 0x300 |
| #define | PCI_DEVICE_ID_VORTEX_GDTNEWRX2 0x301 |
| #define | PCI_DEVICE_ID_INTEL_SRC 0x600 |
| #define | PCI_DEVICE_ID_INTEL_SRC_XSCALE 0x601 |
| #define | GDTH_SCRATCH PAGE_SIZE /* 4KB scratch buffer */ |
| #define | GDTH_MAXCMDS 120 |
| #define | GDTH_MAXC_P_L 16 /* max. cmds per lun */ |
| #define | GDTH_MAX_RAW 2 /* max. cmds per raw device */ |
| #define | MAXOFFSETS 128 |
| #define | MAXHA 16 |
| #define | MAXID 127 |
| #define | MAXLUN 8 |
| #define | MAXBUS 6 |
| #define | MAX_EVENTS 100 /* event buffer count */ |
| #define | MAX_RES_ARGS |
| #define | MAXCYLS 1024 |
| #define | HEADS 64 |
| #define | SECS 32 /* mapping 64*32 */ |
| #define | MEDHEADS 127 |
| #define | MEDSECS 63 /* mapping 127*63 */ |
| #define | BIGHEADS 255 |
| #define | BIGSECS 63 /* mapping 255*63 */ |
| #define | UNUSED_CMND ((Scsi_Cmnd *)-1) |
| #define | INTERNAL_CMND ((Scsi_Cmnd *)-2) |
| #define | SCREEN_CMND ((Scsi_Cmnd *)-3) |
| #define | SPECIAL_SCP(p) (p==UNUSED_CMND || p==INTERNAL_CMND || p==SCREEN_CMND) |
| #define | SCSIRAWSERVICE 3 |
| #define | CACHESERVICE 9 |
| #define | SCREENSERVICE 11 |
| #define | MSG_INV_HANDLE -1 /* special message handle */ |
| #define | MSGLEN 16 /* size of message text */ |
| #define | MSG_SIZE 34 /* size of message structure */ |
| #define | MSG_REQUEST 0 /* async. event: message */ |
| #define | SECTOR_SIZE 0x200 /* always 512 bytes per sec. */ |
| #define | DPMEM_MAGIC 0xC0FFEE11 |
| #define | IC_HEADER_BYTES 48 |
| #define | IC_QUEUE_BYTES 4 |
| #define | DPMEM_COMMAND_OFFSET IC_HEADER_BYTES+IC_QUEUE_BYTES*MAXOFFSETS |
| #define | CLUSTER_DRIVE 1 |
| #define | CLUSTER_MOUNTED 2 |
| #define | CLUSTER_RESERVED 4 |
| #define | CLUSTER_RESERVE_STATE (CLUSTER_DRIVE|CLUSTER_MOUNTED|CLUSTER_RESERVED) |
| #define | GDT_INIT 0 /* service initialization */ |
| #define | GDT_READ 1 /* read command */ |
| #define | GDT_WRITE 2 /* write command */ |
| #define | GDT_INFO 3 /* information about devices */ |
| #define | GDT_FLUSH 4 /* flush dirty cache buffers */ |
| #define | GDT_IOCTL 5 /* ioctl command */ |
| #define | GDT_DEVTYPE 9 /* additional information */ |
| #define | GDT_MOUNT 10 /* mount cache device */ |
| #define | GDT_UNMOUNT 11 /* unmount cache device */ |
| #define | GDT_SET_FEAT 12 /* set feat. (scatter/gather) */ |
| #define | GDT_GET_FEAT 13 /* get features */ |
| #define | GDT_WRITE_THR 16 /* write through */ |
| #define | GDT_READ_THR 17 /* read through */ |
| #define | GDT_EXT_INFO 18 /* extended info */ |
| #define | GDT_RESET 19 /* controller reset */ |
| #define | GDT_RESERVE_DRV 20 /* reserve host drive */ |
| #define | GDT_RELEASE_DRV 21 /* release host drive */ |
| #define | GDT_CLUST_INFO 22 /* cluster info */ |
| #define | GDT_RW_ATTRIBS 23 /* R/W attribs (write thru,..)*/ |
| #define | GDT_CLUST_RESET 24 /* releases the cluster drives*/ |
| #define | GDT_FREEZE_IO 25 /* freezes all IOs */ |
| #define | GDT_UNFREEZE_IO 26 /* unfreezes all IOs */ |
| #define | GDT_X_INIT_HOST 29 /* ext. init: 64 bit support */ |
| #define | GDT_X_INFO 30 /* ext. info for drives>2TB */ |
| #define | GDT_RESERVE 14 /* reserve dev. to raw serv. */ |
| #define | GDT_RELEASE 15 /* release device */ |
| #define | GDT_RESERVE_ALL 16 /* reserve all devices */ |
| #define | GDT_RELEASE_ALL 17 /* release all devices */ |
| #define | GDT_RESET_BUS 18 /* reset bus */ |
| #define | GDT_SCAN_START 19 /* start device scan */ |
| #define | GDT_SCAN_END 20 /* stop device scan */ |
| #define | GDT_X_INIT_RAW 21 /* ext. init: 64 bit support */ |
| #define | GDT_REALTIME 3 /* realtime clock to screens. */ |
| #define | GDT_X_INIT_SCR 4 /* ext. init: 64 bit support */ |
| #define | SCSI_DR_INFO 0x00 /* SCSI drive info */ |
| #define | SCSI_CHAN_CNT 0x05 /* SCSI channel count */ |
| #define | SCSI_DR_LIST 0x06 /* SCSI drive list */ |
| #define | SCSI_DEF_CNT 0x15 /* grown/primary defects */ |
| #define | DSK_STATISTICS 0x4b /* SCSI disk statistics */ |
| #define | IOCHAN_DESC 0x5d /* description of IO channel */ |
| #define | IOCHAN_RAW_DESC 0x5e /* description of raw IO chn. */ |
| #define | L_CTRL_PATTERN 0x20000000L /* SCSI IOCTL mask */ |
| #define | ARRAY_INFO 0x12 /* array drive info */ |
| #define | ARRAY_DRV_LIST 0x0f /* array drive list */ |
| #define | ARRAY_DRV_LIST2 0x34 /* array drive list (new) */ |
| #define | LA_CTRL_PATTERN 0x10000000L /* array IOCTL mask */ |
| #define | CACHE_DRV_CNT 0x01 /* cache drive count */ |
| #define | CACHE_DRV_LIST 0x02 /* cache drive list */ |
| #define | CACHE_INFO 0x04 /* cache info */ |
| #define | CACHE_CONFIG 0x05 /* cache configuration */ |
| #define | CACHE_DRV_INFO 0x07 /* cache drive info */ |
| #define | BOARD_FEATURES 0x15 /* controller features */ |
| #define | BOARD_INFO 0x28 /* controller info */ |
| #define | SET_PERF_MODES 0x82 /* set mode (coalescing,..) */ |
| #define | GET_PERF_MODES 0x83 /* get mode */ |
| #define | CACHE_READ_OEM_STRING_RECORD 0x84 /* read OEM string record */ |
| #define | HOST_GET 0x10001L /* get host drive list */ |
| #define | IO_CHANNEL 0x00020000L /* default IO channel */ |
| #define | INVALID_CHANNEL 0x0000ffffL /* invalid channel */ |
| #define | S_OK 1 /* no error */ |
| #define | S_GENERR 6 /* general error */ |
| #define | S_BSY 7 /* controller busy */ |
| #define | S_CACHE_UNKNOWN 12 /* cache serv.: drive unknown */ |
| #define | S_RAW_SCSI 12 /* raw serv.: target error */ |
| #define | S_RAW_ILL 0xff /* raw serv.: illegal */ |
| #define | S_NOFUNC -2 /* unknown function */ |
| #define | S_CACHE_RESERV -24 /* cache: reserv. conflict */ |
| #define | INIT_RETRIES 100000 /* 100000 * 1ms = 100s */ |
| #define | INIT_TIMEOUT 100000 /* 100000 * 1ms = 100s */ |
| #define | POLL_TIMEOUT 10000 /* 10000 * 1ms = 10s */ |
| #define | DEFAULT_PRI 0x20 |
| #define | IOCTL_PRI 0x10 |
| #define | HIGH_PRI 0x08 |
| #define | GDTH_DATA_IN 0x01000000L /* data from target */ |
| #define | GDTH_DATA_OUT 0x00000000L /* data to target */ |
| #define | ID0REG 0x0c80 /* board ID */ |
| #define | EINTENABREG 0x0c89 /* interrupt enable */ |
| #define | SEMA0REG 0x0c8a /* command semaphore */ |
| #define | SEMA1REG 0x0c8b /* status semaphore */ |
| #define | LDOORREG 0x0c8d /* local doorbell */ |
| #define | EDENABREG 0x0c8e /* EISA system doorbell enab. */ |
| #define | EDOORREG 0x0c8f /* EISA system doorbell */ |
| #define | MAILBOXREG 0x0c90 /* mailbox reg. (16 bytes) */ |
| #define | EISAREG 0x0cc0 /* EISA configuration */ |
| #define | LINUX_OS 8 /* used for cache optim. */ |
| #define | SECS32 0x1f /* round capacity */ |
| #define | BIOS_ID_OFFS 0x10 /* offset contr-ID in ISABIOS */ |
| #define | LOCALBOARD 0 /* board node always 0 */ |
| #define | ASYNCINDEX 0 /* cmd index async. event */ |
| #define | SPEZINDEX 1 /* cmd index unknown service */ |
| #define | COALINDEX (GDTH_MAXCMDS + 2) |
| #define | SCATTER_GATHER 1 /* s/g feature */ |
| #define | GDT_WR_THROUGH 0x100 /* WRITE_THROUGH supported */ |
| #define | GDT_64BIT 0x200 /* 64bit / drv>2TB support */ |
Functions | |
| int | gdth_proc_info (struct Scsi_Host *, char *, char **, off_t, int, int) |
Variables | |
| u8 | tid |
| u8 | lun |
| u8 | res [2] |
| u32 | blk_size |
| u32 | rd_count |
| u32 | wr_count |
| u32 | rd_blk_count |
| u32 | wr_blk_count |
| u32 | retries |
| u32 | reassigns |
| u32 | address |
| u8 | type |
| u8 | local_no |
| u16 | features |
| u8 | proc_id |
| u8 | proc_defect |
| u8 | reserved [2] |
| u16 | offset |
| u16 | serv_id |
| u8 | bios_used [0x3c00-32] |
| u32 | magic |
| u16 | need_deinit |
| u8 | switch_support |
| u8 | padding [9] |
| u8 | os_used [16] |
| u8 | memlock |
| u8 | event |
| u8 | irqen |
| u8 | irqdel |
| u8 volatile | Sema1 |
| u8 | rq |
| u8 | unused0 [1] |
| u8 | unused1 [3] |
| u8 | unused2 [2] |
| u8 | unused3 [3] |
| u8 | unused4 [3] |
| u8 | data_length |
| u8 | med_type |
| u8 | dev_par |
| u8 | bd_length |
| u8 | dens_code |
| u8 | block_count [3] |
| u8 | block_length [3] |
| #define CACHE_READ_OEM_STRING_RECORD 0x84 /* read OEM string record */ |
| #define CLUSTER_RESERVE_STATE (CLUSTER_DRIVE|CLUSTER_MOUNTED|CLUSTER_RESERVED) |
| #define COALINDEX (GDTH_MAXCMDS + 2) |
| #define DPMEM_COMMAND_OFFSET IC_HEADER_BYTES+IC_QUEUE_BYTES*MAXOFFSETS |
| #define GDT_RESET 19 /* controller reset */ |
| #define IOCHAN_RAW_DESC 0x5e /* description of raw IO chn. */ |
| #define MAX_RES_ARGS |
| #define PCI_DEVICE_ID_VORTEX_GDT60x0 0 /* GDT6000/6020/6050 */ |
| #define PCI_DEVICE_ID_VORTEX_GDT6555 13 /* GDT6555/6555-ECC */ |
| #define PCI_DEVICE_ID_VORTEX_GDT6x11RD 0x114 /* GDT6111RD/GDT6511RD */ |
| #define PCI_DEVICE_ID_VORTEX_GDT6x11RP 0x104 /* GDT6111RP/GDT6511RP */ |
| #define PCI_DEVICE_ID_VORTEX_GDT6x17RD 0x110 /* GDT6117RD/GDT6517RD */ |
| #define PCI_DEVICE_ID_VORTEX_GDT6x17RP 0x100 /* GDT6117RP/GDT6517RP */ |
| #define PCI_DEVICE_ID_VORTEX_GDT6x18RD |
| #define PCI_DEVICE_ID_VORTEX_GDT6x19RD 0x210 /* GDT6519RD/GDT6619RD */ |
| #define PCI_DEVICE_ID_VORTEX_GDT6x21RD 0x115 /* GDT6121RD/GDT6521RD */ |
| #define PCI_DEVICE_ID_VORTEX_GDT6x21RP 0x105 /* GDT6121RP/GDT6521RP */ |
| #define PCI_DEVICE_ID_VORTEX_GDT6x27RD 0x111 /* GDT6127RD/GDT6527RD */ |
| #define PCI_DEVICE_ID_VORTEX_GDT6x27RP 0x101 /* GDT6127RP/GDT6527RP */ |
| #define PCI_DEVICE_ID_VORTEX_GDT6x28RD |
| #define PCI_DEVICE_ID_VORTEX_GDT6x29RD 0x211 /* GDT6529RD/GDT6629RD */ |
| #define PCI_DEVICE_ID_VORTEX_GDT6x38RD 0x11A /* GDT6538RD/GDT6638RD */ |
| #define PCI_DEVICE_ID_VORTEX_GDT6x58RD 0x11B /* GDT6558RD/GDT6658RD */ |
| #define PCI_DEVICE_ID_VORTEX_GDT7x18RN |
| #define PCI_DEVICE_ID_VORTEX_GDT7x19RN 0x260 /* GDT7519RN/GDT7619RN */ |
| #define PCI_DEVICE_ID_VORTEX_GDT7x28RN |
| #define PCI_DEVICE_ID_VORTEX_GDT7x29RN 0x261 /* GDT7529RN/GDT7629RN */ |
| #define PCI_DEVICE_ID_VORTEX_GDT7x38RN 0x16A /* GDT7538RN/GDT7638RN */ |
| #define PCI_DEVICE_ID_VORTEX_GDT7x58RN 0x16B /* GDT7558RN/GDT7658RN */ |
| #define S_BSY 7 /* controller busy */ |
| #define SPECIAL_SCP | ( | p | ) | (p==UNUSED_CMND || p==INTERNAL_CMND || p==SCREEN_CMND) |
Definition at line 8 of file gdth_proc.c.
1.8.2