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tx3927.h
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1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License. See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 2000 Toshiba Corporation
7  */
8 #ifndef __ASM_TXX9_TX3927_H
9 #define __ASM_TXX9_TX3927_H
10 
11 #define TX3927_REG_BASE 0xfffe0000UL
12 #define TX3927_REG_SIZE 0x00010000
13 #define TX3927_SDRAMC_REG (TX3927_REG_BASE + 0x8000)
14 #define TX3927_ROMC_REG (TX3927_REG_BASE + 0x9000)
15 #define TX3927_DMA_REG (TX3927_REG_BASE + 0xb000)
16 #define TX3927_IRC_REG (TX3927_REG_BASE + 0xc000)
17 #define TX3927_PCIC_REG (TX3927_REG_BASE + 0xd000)
18 #define TX3927_CCFG_REG (TX3927_REG_BASE + 0xe000)
19 #define TX3927_NR_TMR 3
20 #define TX3927_TMR_REG(ch) (TX3927_REG_BASE + 0xf000 + (ch) * 0x100)
21 #define TX3927_NR_SIO 2
22 #define TX3927_SIO_REG(ch) (TX3927_REG_BASE + 0xf300 + (ch) * 0x100)
23 #define TX3927_PIO_REG (TX3927_REG_BASE + 0xf500)
24 
25 struct tx3927_sdramc_reg {
26  volatile unsigned long cr[8];
27  volatile unsigned long tr[3];
28  volatile unsigned long cmd;
29  volatile unsigned long smrs[2];
30 };
31 
32 struct tx3927_romc_reg {
33  volatile unsigned long cr[8];
34 };
35 
36 struct tx3927_dma_reg {
37  struct tx3927_dma_ch_reg {
38  volatile unsigned long cha;
39  volatile unsigned long sar;
40  volatile unsigned long dar;
41  volatile unsigned long cntr;
42  volatile unsigned long sair;
43  volatile unsigned long dair;
44  volatile unsigned long ccr;
45  volatile unsigned long csr;
46  } ch[4];
47  volatile unsigned long dbr[8];
48  volatile unsigned long tdhr;
49  volatile unsigned long mcr;
50  volatile unsigned long unused0;
51 };
52 
53 #include <asm/byteorder.h>
54 
55 #ifdef __BIG_ENDIAN
56 #define endian_def_s2(e1, e2) \
57  volatile unsigned short e1, e2
58 #define endian_def_sb2(e1, e2, e3) \
59  volatile unsigned short e1;volatile unsigned char e2, e3
60 #define endian_def_b2s(e1, e2, e3) \
61  volatile unsigned char e1, e2;volatile unsigned short e3
62 #define endian_def_b4(e1, e2, e3, e4) \
63  volatile unsigned char e1, e2, e3, e4
64 #else
65 #define endian_def_s2(e1, e2) \
66  volatile unsigned short e2, e1
67 #define endian_def_sb2(e1, e2, e3) \
68  volatile unsigned char e3, e2;volatile unsigned short e1
69 #define endian_def_b2s(e1, e2, e3) \
70  volatile unsigned short e3;volatile unsigned char e2, e1
71 #define endian_def_b4(e1, e2, e3, e4) \
72  volatile unsigned char e4, e3, e2, e1
73 #endif
74 
75 struct tx3927_pcic_reg {
76  endian_def_s2(did, vid);
77  endian_def_s2(pcistat, pcicmd);
78  endian_def_b4(cc, scc, rpli, rid);
79  endian_def_b4(unused0, ht, mlt, cls);
80  volatile unsigned long ioba; /* +10 */
81  volatile unsigned long mba;
82  volatile unsigned long unused1[5];
83  endian_def_s2(svid, ssvid);
84  volatile unsigned long unused2; /* +30 */
85  endian_def_sb2(unused3, unused4, capptr);
86  volatile unsigned long unused5;
87  endian_def_b4(ml, mg, ip, il);
88  volatile unsigned long unused6; /* +40 */
89  volatile unsigned long istat;
90  volatile unsigned long iim;
91  volatile unsigned long rrt;
92  volatile unsigned long unused7[3]; /* +50 */
93  volatile unsigned long ipbmma;
94  volatile unsigned long ipbioma; /* +60 */
95  volatile unsigned long ilbmma;
96  volatile unsigned long ilbioma;
97  volatile unsigned long unused8[9];
98  volatile unsigned long tc; /* +90 */
99  volatile unsigned long tstat;
100  volatile unsigned long tim;
101  volatile unsigned long tccmd;
102  volatile unsigned long pcirrt; /* +a0 */
103  volatile unsigned long pcirrt_cmd;
104  volatile unsigned long pcirrdt;
105  volatile unsigned long unused9[3];
106  volatile unsigned long tlboap;
107  volatile unsigned long tlbiap;
108  volatile unsigned long tlbmma; /* +c0 */
109  volatile unsigned long tlbioma;
110  volatile unsigned long sc_msg;
111  volatile unsigned long sc_be;
112  volatile unsigned long tbl; /* +d0 */
113  volatile unsigned long unused10[3];
114  volatile unsigned long pwmng; /* +e0 */
115  volatile unsigned long pwmngs;
116  volatile unsigned long unused11[6];
117  volatile unsigned long req_trace; /* +100 */
118  volatile unsigned long pbapmc;
119  volatile unsigned long pbapms;
120  volatile unsigned long pbapmim;
121  volatile unsigned long bm; /* +110 */
122  volatile unsigned long cpcibrs;
123  volatile unsigned long cpcibgs;
124  volatile unsigned long pbacs;
125  volatile unsigned long iobas; /* +120 */
126  volatile unsigned long mbas;
127  volatile unsigned long lbc;
128  volatile unsigned long lbstat;
129  volatile unsigned long lbim; /* +130 */
130  volatile unsigned long pcistatim;
131  volatile unsigned long ica;
132  volatile unsigned long icd;
133  volatile unsigned long iiadp; /* +140 */
134  volatile unsigned long iscdp;
135  volatile unsigned long mmas;
136  volatile unsigned long iomas;
137  volatile unsigned long ipciaddr; /* +150 */
138  volatile unsigned long ipcidata;
139  volatile unsigned long ipcibe;
140 };
141 
142 struct tx3927_ccfg_reg {
143  volatile unsigned long ccfg;
144  volatile unsigned long crir;
145  volatile unsigned long pcfg;
146  volatile unsigned long tear;
147  volatile unsigned long pdcr;
148 };
149 
150 /*
151  * SDRAMC
152  */
153 
154 /*
155  * ROMC
156  */
157 
158 /*
159  * DMA
160  */
161 /* bits for MCR */
162 #define TX3927_DMA_MCR_EIS(ch) (0x10000000<<(ch))
163 #define TX3927_DMA_MCR_DIS(ch) (0x01000000<<(ch))
164 #define TX3927_DMA_MCR_RSFIF 0x00000080
165 #define TX3927_DMA_MCR_FIFUM(ch) (0x00000008<<(ch))
166 #define TX3927_DMA_MCR_LE 0x00000004
167 #define TX3927_DMA_MCR_RPRT 0x00000002
168 #define TX3927_DMA_MCR_MSTEN 0x00000001
169 
170 /* bits for CCRn */
171 #define TX3927_DMA_CCR_DBINH 0x04000000
172 #define TX3927_DMA_CCR_SBINH 0x02000000
173 #define TX3927_DMA_CCR_CHRST 0x01000000
174 #define TX3927_DMA_CCR_RVBYTE 0x00800000
175 #define TX3927_DMA_CCR_ACKPOL 0x00400000
176 #define TX3927_DMA_CCR_REQPL 0x00200000
177 #define TX3927_DMA_CCR_EGREQ 0x00100000
178 #define TX3927_DMA_CCR_CHDN 0x00080000
179 #define TX3927_DMA_CCR_DNCTL 0x00060000
180 #define TX3927_DMA_CCR_EXTRQ 0x00010000
181 #define TX3927_DMA_CCR_INTRQD 0x0000e000
182 #define TX3927_DMA_CCR_INTENE 0x00001000
183 #define TX3927_DMA_CCR_INTENC 0x00000800
184 #define TX3927_DMA_CCR_INTENT 0x00000400
185 #define TX3927_DMA_CCR_CHNEN 0x00000200
186 #define TX3927_DMA_CCR_XFACT 0x00000100
187 #define TX3927_DMA_CCR_SNOP 0x00000080
188 #define TX3927_DMA_CCR_DSTINC 0x00000040
189 #define TX3927_DMA_CCR_SRCINC 0x00000020
190 #define TX3927_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c)
191 #define TX3927_DMA_CCR_XFSZ_1W TX3927_DMA_CCR_XFSZ(2)
192 #define TX3927_DMA_CCR_XFSZ_4W TX3927_DMA_CCR_XFSZ(4)
193 #define TX3927_DMA_CCR_XFSZ_8W TX3927_DMA_CCR_XFSZ(5)
194 #define TX3927_DMA_CCR_XFSZ_16W TX3927_DMA_CCR_XFSZ(6)
195 #define TX3927_DMA_CCR_XFSZ_32W TX3927_DMA_CCR_XFSZ(7)
196 #define TX3927_DMA_CCR_MEMIO 0x00000002
197 #define TX3927_DMA_CCR_ONEAD 0x00000001
198 
199 /* bits for CSRn */
200 #define TX3927_DMA_CSR_CHNACT 0x00000100
201 #define TX3927_DMA_CSR_ABCHC 0x00000080
202 #define TX3927_DMA_CSR_NCHNC 0x00000040
203 #define TX3927_DMA_CSR_NTRNFC 0x00000020
204 #define TX3927_DMA_CSR_EXTDN 0x00000010
205 #define TX3927_DMA_CSR_CFERR 0x00000008
206 #define TX3927_DMA_CSR_CHERR 0x00000004
207 #define TX3927_DMA_CSR_DESERR 0x00000002
208 #define TX3927_DMA_CSR_SORERR 0x00000001
209 
210 /*
211  * IRC
212  */
213 #define TX3927_IR_INT0 0
214 #define TX3927_IR_INT1 1
215 #define TX3927_IR_INT2 2
216 #define TX3927_IR_INT3 3
217 #define TX3927_IR_INT4 4
218 #define TX3927_IR_INT5 5
219 #define TX3927_IR_SIO0 6
220 #define TX3927_IR_SIO1 7
221 #define TX3927_IR_SIO(ch) (6 + (ch))
222 #define TX3927_IR_DMA 8
223 #define TX3927_IR_PIO 9
224 #define TX3927_IR_PCI 10
225 #define TX3927_IR_TMR(ch) (13 + (ch))
226 #define TX3927_NUM_IR 16
227 
228 /*
229  * PCIC
230  */
231 /* bits for PCICMD */
232 /* see PCI_COMMAND_XXX in linux/pci.h */
233 
234 /* bits for PCISTAT */
235 /* see PCI_STATUS_XXX in linux/pci.h */
236 #define PCI_STATUS_NEW_CAP 0x0010
237 
238 /* bits for ISTAT/IIM */
239 #define TX3927_PCIC_IIM_ALL 0x00001600
240 
241 /* bits for TC */
242 #define TX3927_PCIC_TC_OF16E 0x00000020
243 #define TX3927_PCIC_TC_IF8E 0x00000010
244 #define TX3927_PCIC_TC_OF8E 0x00000008
245 
246 /* bits for TSTAT/TIM */
247 #define TX3927_PCIC_TIM_ALL 0x0003ffff
248 
249 /* bits for IOBA/MBA */
250 /* see PCI_BASE_ADDRESS_XXX in linux/pci.h */
251 
252 /* bits for PBAPMC */
253 #define TX3927_PCIC_PBAPMC_RPBA 0x00000004
254 #define TX3927_PCIC_PBAPMC_PBAEN 0x00000002
255 #define TX3927_PCIC_PBAPMC_BMCEN 0x00000001
256 
257 /* bits for LBSTAT/LBIM */
258 #define TX3927_PCIC_LBIM_ALL 0x0000003e
259 
260 /* bits for PCISTATIM (see also PCI_STATUS_XXX in linux/pci.h */
261 #define TX3927_PCIC_PCISTATIM_ALL 0x0000f900
262 
263 /* bits for LBC */
264 #define TX3927_PCIC_LBC_IBSE 0x00004000
265 #define TX3927_PCIC_LBC_TIBSE 0x00002000
266 #define TX3927_PCIC_LBC_TMFBSE 0x00001000
267 #define TX3927_PCIC_LBC_HRST 0x00000800
268 #define TX3927_PCIC_LBC_SRST 0x00000400
269 #define TX3927_PCIC_LBC_EPCAD 0x00000200
270 #define TX3927_PCIC_LBC_MSDSE 0x00000100
271 #define TX3927_PCIC_LBC_CRR 0x00000080
272 #define TX3927_PCIC_LBC_ILMDE 0x00000040
273 #define TX3927_PCIC_LBC_ILIDE 0x00000020
274 
275 #define TX3927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
276 #define TX3927_PCIC_MAX_DEVNU TX3927_PCIC_IDSEL_AD_TO_SLOT(32)
277 
278 /*
279  * CCFG
280  */
281 /* CCFG : Chip Configuration */
282 #define TX3927_CCFG_TLBOFF 0x00020000
283 #define TX3927_CCFG_BEOW 0x00010000
284 #define TX3927_CCFG_WR 0x00008000
285 #define TX3927_CCFG_TOE 0x00004000
286 #define TX3927_CCFG_PCIXARB 0x00002000
287 #define TX3927_CCFG_PCI3 0x00001000
288 #define TX3927_CCFG_PSNP 0x00000800
289 #define TX3927_CCFG_PPRI 0x00000400
290 #define TX3927_CCFG_PLLM 0x00000030
291 #define TX3927_CCFG_ENDIAN 0x00000004
292 #define TX3927_CCFG_HALT 0x00000002
293 #define TX3927_CCFG_ACEHOLD 0x00000001
294 
295 /* PCFG : Pin Configuration */
296 #define TX3927_PCFG_SYSCLKEN 0x08000000
297 #define TX3927_PCFG_SDRCLKEN_ALL 0x07c00000
298 #define TX3927_PCFG_SDRCLKEN(ch) (0x00400000<<(ch))
299 #define TX3927_PCFG_PCICLKEN_ALL 0x003c0000
300 #define TX3927_PCFG_PCICLKEN(ch) (0x00040000<<(ch))
301 #define TX3927_PCFG_SELALL 0x0003ffff
302 #define TX3927_PCFG_SELCS 0x00020000
303 #define TX3927_PCFG_SELDSF 0x00010000
304 #define TX3927_PCFG_SELSIOC_ALL 0x0000c000
305 #define TX3927_PCFG_SELSIOC(ch) (0x00004000<<(ch))
306 #define TX3927_PCFG_SELSIO_ALL 0x00003000
307 #define TX3927_PCFG_SELSIO(ch) (0x00001000<<(ch))
308 #define TX3927_PCFG_SELTMR_ALL 0x00000e00
309 #define TX3927_PCFG_SELTMR(ch) (0x00000200<<(ch))
310 #define TX3927_PCFG_SELDONE 0x00000100
311 #define TX3927_PCFG_INTDMA_ALL 0x000000f0
312 #define TX3927_PCFG_INTDMA(ch) (0x00000010<<(ch))
313 #define TX3927_PCFG_SELDMA_ALL 0x0000000f
314 #define TX3927_PCFG_SELDMA(ch) (0x00000001<<(ch))
315 
316 #define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG)
317 #define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG)
318 #define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG)
319 #define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG)
320 #define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG)
321 #define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch))
322 #define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG)
323 
324 #define TX3927_REV_PCODE() (tx3927_ccfgptr->crir >> 16)
325 #define TX3927_ROMC_BA(ch) (tx3927_romcptr->cr[(ch)] & 0xfff00000)
326 #define TX3927_ROMC_SIZE(ch) \
327  (0x00100000 << ((tx3927_romcptr->cr[(ch)] >> 8) & 0xf))
328 #define TX3927_ROMC_WIDTH(ch) (32 >> ((tx3927_romcptr->cr[(ch)] >> 7) & 0x1))
329 
330 void tx3927_wdt_init(void);
331 void tx3927_setup(void);
332 void tx3927_time_init(unsigned int evt_tmrnr, unsigned int src_tmrnr);
333 void tx3927_sio_init(unsigned int sclk, unsigned int cts_mask);
334 struct pci_controller;
335 void tx3927_pcic_setup(struct pci_controller *channel,
336  unsigned long sdram_size, int extarb);
337 void tx3927_setup_pcierr_irq(void);
338 void tx3927_irq_init(void);
339 void tx3927_mtd_init(int ch);
340 
341 #endif /* __ASM_TXX9_TX3927_H */
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