#include <linux/kernel.h>
#include <plat/clock.h>

Macros
#define	CORE_CLK_SRC_32K 0x0

#define	CORE_CLK_SRC_DPLL 0x1

#define	CORE_CLK_SRC_DPLL_X2 0x2

#define	OMAP2XXX_EN_DPLL_LPBYPASS 0x1

#define	OMAP2XXX_EN_DPLL_FRBYPASS 0x2

#define	OMAP2XXX_EN_DPLL_LOCKED 0x3

#define	OMAP3XXX_EN_DPLL_LPBYPASS 0x5

#define	OMAP3XXX_EN_DPLL_FRBYPASS 0x6

#define	OMAP3XXX_EN_DPLL_LOCKED 0x7

#define	OMAP4XXX_EN_DPLL_MNBYPASS 0x4

#define	OMAP4XXX_EN_DPLL_LPBYPASS 0x5

#define	OMAP4XXX_EN_DPLL_FRBYPASS 0x6

#define	OMAP4XXX_EN_DPLL_LOCKED 0x7

#define	DPLL_LOW_POWER_STOP 0x1

#define	DPLL_LOW_POWER_BYPASS 0x5

#define	DPLL_LOCKED 0x7

#define	DPLL_J_TYPE 0x1

#define	omap2_clk_disable_unused NULL

Functions
int	omap2_clk_enable (struct clk *clk)

void	omap2_clk_disable (struct clk *clk)

long	omap2_clk_round_rate (struct clk *clk, unsigned long rate)

int	omap2_clk_set_rate (struct clk *clk, unsigned long rate)

int	omap2_clk_set_parent (struct clk clk, struct clk new_parent)

long	omap2_dpll_round_rate (struct clk *clk, unsigned long target_rate)

unsigned long	omap3_dpll_recalc (struct clk *clk)

unsigned long	omap3_clkoutx2_recalc (struct clk *clk)

void	omap3_dpll_allow_idle (struct clk *clk)

void	omap3_dpll_deny_idle (struct clk *clk)

u32	omap3_dpll_autoidle_read (struct clk *clk)

int	omap3_noncore_dpll_set_rate (struct clk *clk, unsigned long rate)

int	omap3_noncore_dpll_enable (struct clk *clk)

void	omap3_noncore_dpll_disable (struct clk *clk)

int	omap4_dpllmx_gatectrl_read (struct clk *clk)

void	omap4_dpllmx_allow_gatectrl (struct clk *clk)

void	omap4_dpllmx_deny_gatectrl (struct clk *clk)

long	omap4_dpll_regm4xen_round_rate (struct clk *clk, unsigned long target_rate)

unsigned long	omap4_dpll_regm4xen_recalc (struct clk *clk)

void	omap2_init_clk_clkdm (struct clk *clk)

void __init	omap2_clk_disable_clkdm_control (void)

u32	omap2_clksel_round_rate_div (struct clk clk, unsigned long target_rate, u32 new_div)

void	omap2_init_clksel_parent (struct clk *clk)

unsigned long	omap2_clksel_recalc (struct clk *clk)

long	omap2_clksel_round_rate (struct clk *clk, unsigned long target_rate)

int	omap2_clksel_set_rate (struct clk *clk, unsigned long rate)

int	omap2_clksel_set_parent (struct clk clk, struct clk new_parent)

void	omap2_clkt_iclk_allow_idle (struct clk *clk)

void	omap2_clkt_iclk_deny_idle (struct clk *clk)

u32	omap2_get_dpll_rate (struct clk *clk)

void	omap2_init_dpll_parent (struct clk *clk)

int	omap2_wait_clock_ready (void __iomem reg, u32 cval, const char name)

int	omap2_dflt_clk_enable (struct clk *clk)

void	omap2_dflt_clk_disable (struct clk *clk)

void	omap2_clk_dflt_find_companion (struct clk clk, void __iomem other_reg, u8 other_bit)

void	omap2_clk_dflt_find_idlest (struct clk clk, void __iomem idlest_reg, u8 idlest_bit, u8 *idlest_val)

int	omap2_clk_switch_mpurate_at_boot (const char *mpurate_ck_name)

void	omap2_clk_print_new_rates (const char hfclkin_ck_name, const char core_ck_name, const char *mpu_ck_name)

int	am33xx_clk_init (void)

Variables
u16	cpu_mask

struct clkops	clkops_omap2_dflt_wait

struct clkops	clkops_dummy

struct clkops	clkops_omap2_dflt

struct clk_functions	omap2_clk_functions

struct clk *	vclk

struct clk *	sclk

struct clksel_rate	gpt_32k_rates []

struct clksel_rate	gpt_sys_rates []

struct clksel_rate	gfx_l3_rates []

struct clksel_rate	dsp_ick_rates []

struct clkops	clkops_omap2_iclk_dflt_wait

struct clkops	clkops_omap2_iclk_dflt

struct clkops	clkops_omap2_iclk_idle_only

struct clkops	clkops_omap2_mdmclk_dflt_wait

struct clkops	clkops_omap2xxx_dpll_ops

struct clkops	clkops_omap3_noncore_dpll_ops

struct clkops	clkops_omap3_core_dpll_ops

struct clkops	clkops_omap4_dpllmx_ops

struct clksel_rate	div_1_0_rates []

struct clksel_rate	div_1_1_rates []

struct clksel_rate	div_1_2_rates []

struct clksel_rate	div_1_3_rates []

struct clksel_rate	div_1_4_rates []

struct clksel_rate	div31_1to31_rates []

struct clk	virt_19200000_ck

struct clk	virt_26000000_ck

Macro Definition Documentation

#define CORE_CLK_SRC_32K 0x0

Definition at line 24 of file clock.h.

#define CORE_CLK_SRC_DPLL 0x1

Definition at line 25 of file clock.h.

#define CORE_CLK_SRC_DPLL_X2 0x2

Definition at line 26 of file clock.h.

#define DPLL_J_TYPE 0x1

Definition at line 50 of file clock.h.

#define DPLL_LOCKED 0x7

Definition at line 47 of file clock.h.

#define DPLL_LOW_POWER_BYPASS 0x5

Definition at line 46 of file clock.h.

#define DPLL_LOW_POWER_STOP 0x1

Definition at line 45 of file clock.h.

#define omap2_clk_disable_unused NULL

Definition at line 75 of file clock.h.

#define OMAP2XXX_EN_DPLL_FRBYPASS 0x2

Definition at line 30 of file clock.h.

#define OMAP2XXX_EN_DPLL_LOCKED 0x3

Definition at line 31 of file clock.h.

#define OMAP2XXX_EN_DPLL_LPBYPASS 0x1

Definition at line 29 of file clock.h.

#define OMAP3XXX_EN_DPLL_FRBYPASS 0x6

Definition at line 35 of file clock.h.

#define OMAP3XXX_EN_DPLL_LOCKED 0x7

Definition at line 36 of file clock.h.

#define OMAP3XXX_EN_DPLL_LPBYPASS 0x5

Definition at line 34 of file clock.h.

#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6

Definition at line 41 of file clock.h.

#define OMAP4XXX_EN_DPLL_LOCKED 0x7

Definition at line 42 of file clock.h.

#define OMAP4XXX_EN_DPLL_LPBYPASS 0x5

Definition at line 40 of file clock.h.

#define OMAP4XXX_EN_DPLL_MNBYPASS 0x4

Definition at line 39 of file clock.h.

Function Documentation

int am33xx_clk_init ( void )

Definition at line 1080 of file clock33xx_data.c.

void omap2_clk_dflt_find_companion	(	struct clk *	clk,
		void __iomem **	other_reg,
		u8 *	other_bit
	)

omap2_clk_dflt_find_companion - find companion clock to : struct clk * to find the companion clock of : void __iomem ** to return the companion clock CM_*CLKEN va in : u8 ** to return the companion clock bit shift in

Note: We don't need special code here for INVERT_ENABLE for the time being since INVERT_ENABLE only applies to clocks enabled by CM_CLKEN_PLL

Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's just a matter of XORing the bits.

Some clocks don't have companion clocks. For example, modules with only an interface clock (such as MAILBOXES) don't have a companion clock. Right now, this code relies on the hardware exporting a bit in the correct companion register that indicates that the nonexistent 'companion clock' is active. Future patches will associate this type of code with per-module data structures to avoid this issue, and remove the casts. No return value.

Definition at line 149 of file clock.c.

void omap2_clk_dflt_find_idlest	(	struct clk *	clk,
		void __iomem **	idlest_reg,
		u8 *	idlest_bit,
		u8 *	idlest_val
	)

omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for : struct clk * to find IDLEST info for : void __iomem ** to return the CM_IDLEST va in : u8 * to return the CM_IDLEST bit shift in : u8 * to return the idle status indicator

Return the CM_IDLEST register address and bit shift corresponding to the module that "owns" this clock. This default code assumes that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that the IDLEST register address ID corresponds to the CM_*CLKEN register address ID (e.g., that CM_FCLKEN2 corresponds to CM_IDLEST2). This is not true for all modules. No return value.

Definition at line 178 of file clock.c.

void omap2_clk_disable ( struct clk * clk )

omap2_clk_disable - disable a clock, if the system is not using it : struct clk * to disable

Decrements the usecount on struct clk . If there are no users left, call the clkops-specific clock disable function to disable it in hardware. If the clock is part of a clockdomain (which they all should be), request that the clockdomain be disabled. (It too has a usecount, and so will not be disabled in the hardware until it no longer has any users.) If the clock has a parent clock (most of them do), then call ourselves, recursing on the parent clock. This can cause an entire branch of the clock tree to be powered off by simply disabling one clock. Intended to be called with the clockfw_lock spinlock held. No return value.

Definition at line 274 of file clock.c.

void __init omap2_clk_disable_clkdm_control ( void )

omap2_clk_disable_clkdm_control - disable clkdm control on clk enable/disable

Prevent the OMAP clock code from calling into the clockdomain code when a hardware clock in that clockdomain is enabled or disabled. Intended to be called at init time from omap*_clk_init(). No return value.

Definition at line 123 of file clock.c.

int omap2_clk_enable ( struct clk * clk )

omap2_clk_enable - request that the system enable a clock : struct clk * to enable

Increments the usecount on struct clk . If there were no users previously, then recurse up the clock tree, enabling all of the clock's parents and all of the parent clockdomains, and finally, enabling 's clockdomain, and itself. Intended to be called with the clockfw_lock spinlock held. Returns 0 upon success or a negative error code upon failure.

Definition at line 313 of file clock.c.

void omap2_clk_print_new_rates	(	const char *	hfclkin_ck_name,
		const char *	core_ck_name,
		const char *	mpu_ck_name
	)

omap2_clk_print_new_rates - print summary of current clock tree rates : clk name for the off-chip HF oscillator : clk name for the on-chip CORE_CLK : clk name for the ARM MPU clock

Prints a short message to the console with the HFCLKIN oscillator rate, the rate of the CORE clock, and the rate of the ARM MPU clock. Called by the boot-time MPU rate switching code. XXX This is intended to be handled by the OPP layer code in the near future and should be removed from the clock code. No return value.

Definition at line 486 of file clock.c.

long omap2_clk_round_rate	(	struct clk *	clk,
		unsigned long	rate
	)

Definition at line 369 of file clock.c.

int omap2_clk_set_parent	(	struct clk *	clk,
		struct clk *	new_parent
	)

Definition at line 393 of file clock.c.

int omap2_clk_set_rate	(	struct clk *	clk,
		unsigned long	rate
	)

Definition at line 378 of file clock.c.

int omap2_clk_switch_mpurate_at_boot ( const char * mpurate_ck_name )

omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument : clk name of the clock to change rate

Change the ARM MPU clock rate to the rate specified on the command line, if one was specified. should be "virt_prcm_set" on OMAP2xxx and "dpll1_ck" on OMAP34xx/OMAP36xx. XXX Does not handle voltage scaling - on OMAP2xxx this is currently handled by the virt_prcm_set clock, but this should be handled by the OPP layer. XXX This is intended to be handled by the OPP layer code in the near future and should be removed from the clock code. Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects the rate, -ENOENT if the struct clk referred to by cannot be found, or 0 upon success.

Definition at line 446 of file clock.c.

unsigned long omap2_clksel_recalc ( struct clk * clk )

omap2_clksel_recalc() - function ptr to pass via struct clk .recalc field : struct clk *

This function is intended to be called only by the clock framework. Each clksel clock should have its struct clk .recalc field set to this function. Returns the clock's current rate, based on its parent's rate and its current divisor setting in the hardware.

Definition at line 407 of file clkt_clksel.c.

long omap2_clksel_round_rate	(	struct clk *	clk,
		unsigned long	target_rate
	)

omap2_clksel_round_rate() - find rounded rate for the given clock and rate : OMAP struct clk to use : desired clock rate

This function is intended to be called only by the clock framework. Finds best target rate based on the source clock and possible dividers. rates. The divider array must be sorted with smallest divider first.

Returns the rounded clock rate or returns 0xffffffff on error.

Definition at line 437 of file clkt_clksel.c.

u32 omap2_clksel_round_rate_div	(	struct clk *	clk,
		unsigned long	target_rate,
		u32 *	new_div
	)

omap2_clksel_round_rate_div() - find divisor for the given clock and rate : OMAP struct clk to use : desired clock rate : ptr to where we should store the divisor

Finds 'best' divider value in an array based on the source and target rates. The divider array must be sorted with smallest divider first. This function is also used by the DPLL3 M2 divider code.

Returns the rounded clock rate or returns 0xffffffff on error.

Definition at line 282 of file clkt_clksel.c.

int omap2_clksel_set_parent	(	struct clk *	clk,
		struct clk *	new_parent
	)

omap2_clksel_set_parent() - change a clock's parent clock : struct clk * of the child clock : struct clk * of the new parent clock

This function is intended to be called only by the clock framework. Change the parent clock of clock to . This is intended to be used while is disabled. This function does not currently check the usecount of the clock, so if multiple drivers are using the clock, and the parent is changed, they will all be affected without any notification. Returns -EINVAL upon error, or 0 upon success.

Definition at line 504 of file clkt_clksel.c.

int omap2_clksel_set_rate	(	struct clk *	clk,
		unsigned long	rate
	)

omap2_clksel_set_rate() - program clock rate in hardware : struct clk * to program rate : target rate to program

This function is intended to be called only by the clock framework. Program 's rate to in the hardware. The clock can be either enabled or disabled when this happens, although if the clock is enabled, some downstream devices may glitch or behave unpredictably when the clock rate is changed - this depends on the hardware. This function does not currently check the usecount of the clock, so if multiple drivers are using the clock, and the rate is changed, they will all be affected without any notification. Returns -EINVAL upon error, or 0 upon success.

Definition at line 459 of file clkt_clksel.c.

void omap2_clkt_iclk_allow_idle ( struct clk * clk )

Definition at line 28 of file clkt_iclk.c.

void omap2_clkt_iclk_deny_idle ( struct clk * clk )

Definition at line 40 of file clkt_iclk.c.

void omap2_dflt_clk_disable ( struct clk * clk )

Definition at line 225 of file clock.c.

int omap2_dflt_clk_enable ( struct clk * clk )

Definition at line 201 of file clock.c.

long omap2_dpll_round_rate	(	struct clk *	clk,
		unsigned long	target_rate
	)

omap2_dpll_round_rate - round a target rate for an OMAP DPLL : struct clk * for a DPLL : desired DPLL clock rate

Given a DPLL and a desired target rate, round the target rate to a possible, programmable rate for this DPLL. Attempts to select the minimum possible n. Stores the computed (m, n) in the DPLL's dpll_data structure so set_rate() will not need to call this (expensive) function again. Returns ~0 if the target rate cannot be rounded, or the rounded rate upon success.

Definition at line 293 of file clkt_dpll.c.

u32 omap2_get_dpll_rate ( struct clk * clk )

omap2_get_dpll_rate - returns the current DPLL CLKOUT rate : struct clk * of a DPLL

DPLLs can be locked or bypassed - basically, enabled or disabled. When locked, the DPLL output depends on the M and N values. When bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and 2 are bypassed with dpll1_fclk and dpll2_fclk respectively (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk. Returns the current DPLL CLKOUT rate (not CLKOUTX2) if the DPLL is locked, or the appropriate bypass rate if the DPLL is bypassed, or 0 if the clock is not a DPLL.

Definition at line 237 of file clkt_dpll.c.

void omap2_init_clk_clkdm ( struct clk * clk )

omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk : OMAP clock struct ptr to use

Convert a clockdomain name stored in a struct clk 'clk' into a clockdomain pointer, and save it into the struct clk. Intended to be called during clk_register(). No return value.

Definition at line 94 of file clock.c.

void omap2_init_clksel_parent ( struct clk * clk )

omap2_init_clksel_parent() - set a clksel clk's parent field from the hdwr : OMAP clock struct ptr to use

Given a pointer to a source-selectable struct clk, read the hardware register and determine what its parent is currently set to. Update 's .parent field with the appropriate clk ptr. No return value.

Definition at line 354 of file clkt_clksel.c.

void omap2_init_dpll_parent ( struct clk * clk )

Definition at line 192 of file clkt_dpll.c.

int omap2_wait_clock_ready	(	void __iomem *	reg,
		u32	cval,
		const char *	name
	)

unsigned long omap3_clkoutx2_recalc ( struct clk * clk )

omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate : DPLL output struct clk

Using parent clock DPLL data, look up DPLL state. If locked, set our rate to the dpll_clk * 2; otherwise, just use dpll_clk.

Definition at line 620 of file dpll3xxx.c.

void omap3_dpll_allow_idle ( struct clk * clk )

omap3_dpll_allow_idle - enable DPLL autoidle bits : struct clk * of the DPLL to operate on

Enable DPLL automatic idle control. This automatic idle mode switching takes effect only when the DPLL is locked, at least on OMAP3430. The DPLL will enter low-power stop when its downstream clocks are gated. No return value.

Definition at line 554 of file dpll3xxx.c.

u32 omap3_dpll_autoidle_read ( struct clk * clk )

omap3_dpll_autoidle_read - read a DPLL's autoidle bits : struct clk * of the DPLL to read

Return the DPLL's autoidle bits, shifted down to bit 0. Returns -EINVAL if passed a null pointer or if the struct clk does not appear to refer to a DPLL.

Definition at line 525 of file dpll3xxx.c.

void omap3_dpll_deny_idle ( struct clk * clk )

omap3_dpll_deny_idle - prevent DPLL from automatically idling : struct clk * of the DPLL to operate on

Disable DPLL automatic idle control. No return value.

Definition at line 588 of file dpll3xxx.c.

unsigned long omap3_dpll_recalc ( struct clk * clk )

omap3_dpll_recalc - recalculate DPLL rate : DPLL struct clk

Recalculate and propagate the DPLL rate.

Definition at line 360 of file dpll3xxx.c.

void omap3_noncore_dpll_disable ( struct clk * clk )

omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop : pointer to a DPLL struct clk

Instructs a non-CORE DPLL to enter low-power stop. This function is intended for use in struct clkops. No return value.

Definition at line 418 of file dpll3xxx.c.

int omap3_noncore_dpll_enable ( struct clk * clk )

omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode : pointer to a DPLL struct clk

Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock. The choice of modes depends on the DPLL's programmed rate: if it is the same as the DPLL's parent clock, it will enter bypass; otherwise, it will enter lock. This code will wait for the DPLL to indicate readiness before returning, unless the DPLL takes too long to enter the target state. Intended to be used as the struct clk's enable function. If DPLL3 was passed in, or the DPLL does not support low-power stop, or if the DPLL took too long to enter bypass or lock, return -EINVAL; otherwise, return 0.

Definition at line 381 of file dpll3xxx.c.

int omap3_noncore_dpll_set_rate	(	struct clk *	clk,
		unsigned long	rate
	)

omap3_noncore_dpll_set_rate - set non-core DPLL rate : struct clk * of DPLL to set : rounded target rate

Set the DPLL CLKOUT to the target rate. If the DPLL can enter low-power bypass, and the target rate is the bypass source clock rate, then configure the DPLL for bypass. Otherwise, round the target rate if it hasn't been done already, then program and lock the DPLL. Returns -EINVAL upon error, or 0 upon success.

Definition at line 437 of file dpll3xxx.c.

unsigned long omap4_dpll_regm4xen_recalc ( struct clk * clk )

omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit : struct clk * of the DPLL to compute the rate for

Compute the output rate for the OMAP4 DPLL represented by . Takes the REGM4XEN bit into consideration, which is needed for the OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers) upon success, or 0 upon error.

Definition at line 95 of file dpll44xx.c.

long omap4_dpll_regm4xen_round_rate	(	struct clk *	clk,
		unsigned long	target_rate
	)

omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit : struct clk * of the DPLL to round a rate for : the desired rate of the DPLL

Compute the rate that would be programmed into the DPLL hardware for if set_rate() were to be provided with the rate . Takes the REGM4XEN bit into consideration, which is needed for the OMAP4 ABE DPLL. Returns the rounded rate (before M-dividers) upon success, -EINVAL if is null or not a DPLL, or ~0 if an error occurred in omap2_dpll_round_rate().

Definition at line 128 of file dpll44xx.c.

void omap4_dpllmx_allow_gatectrl ( struct clk * clk )

Definition at line 45 of file dpll44xx.c.

void omap4_dpllmx_deny_gatectrl ( struct clk * clk )

Definition at line 63 of file dpll44xx.c.

int omap4_dpllmx_gatectrl_read ( struct clk * clk )

Definition at line 26 of file dpll44xx.c.

Variable Documentation

struct clkops clkops_dummy

struct clkops clkops_omap2_dflt

Definition at line 254 of file clock.c.

struct clkops clkops_omap2_dflt_wait

Definition at line 247 of file clock.c.

struct clkops clkops_omap2_iclk_dflt

Definition at line 62 of file clkt_iclk.c.

struct clkops clkops_omap2_iclk_dflt_wait

Definition at line 53 of file clkt_iclk.c.

struct clkops clkops_omap2_iclk_idle_only

Definition at line 69 of file clkt_iclk.c.

struct clkops clkops_omap2_mdmclk_dflt_wait

Definition at line 74 of file clkt_iclk.c.

struct clkops clkops_omap2xxx_dpll_ops

Definition at line 59 of file clkt2xxx_dpll.c.

struct clkops clkops_omap3_core_dpll_ops

Definition at line 662 of file dpll3xxx.c.

struct clkops clkops_omap3_noncore_dpll_ops

Definition at line 655 of file dpll3xxx.c.

struct clkops clkops_omap4_dpllmx_ops

Definition at line 81 of file dpll44xx.c.

u16 cpu_mask

Definition at line 784 of file clock_data.c.

struct clksel_rate div31_1to31_rates[]

Definition at line 75 of file clock_common_data.c.

struct clksel_rate div_1_0_rates[]

Definition at line 50 of file clock_common_data.c.

struct clksel_rate div_1_1_rates[]

Definition at line 55 of file clock_common_data.c.

struct clksel_rate div_1_2_rates[]

Definition at line 60 of file clock_common_data.c.

struct clksel_rate div_1_3_rates[]

Definition at line 65 of file clock_common_data.c.

struct clksel_rate div_1_4_rates[]

Definition at line 70 of file clock_common_data.c.

struct clksel_rate dsp_ick_rates[]

Definition at line 40 of file clock_common_data.c.

struct clksel_rate gfx_l3_rates[]

Definition at line 32 of file clock_common_data.c.

struct clksel_rate gpt_32k_rates[]

Definition at line 22 of file clock_common_data.c.

struct clksel_rate gpt_sys_rates[]

Definition at line 27 of file clock_common_data.c.

struct clk_functions omap2_clk_functions

Definition at line 515 of file clock.c.

struct clk * sclk

Definition at line 33 of file clock2xxx.c.

struct clk* vclk

Definition at line 33 of file clock2xxx.c.

struct clk virt_19200000_ck

Definition at line 112 of file clock_common_data.c.

struct clk virt_26000000_ck

Definition at line 118 of file clock_common_data.c.

Macros

Functions

Variables

Macro Definition Documentation

Function Documentation

Variable Documentation