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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Data Structures | |
| struct | basic_ring |
| struct | transmit_ring |
| struct | typhoon_indexes |
| struct | typhoon_interface |
| struct | tx_desc |
| struct | tcpopt_desc |
| struct | ipsec_desc |
| struct | rx_desc |
| struct | rx_free |
| struct | cmd_desc |
| struct | resp_desc |
| struct | stats_resp |
| struct | sa_descriptor |
| struct | typhoon_file_header |
| struct | typhoon_section_header |
Variables | |
| struct typhoon_indexes | __packed |
| #define TYPHOON_CMD_CREATE_SA cpu_to_le16(0x0034) |
| #define TYPHOON_CMD_DELETE_SA cpu_to_le16(0x0035) |
| #define TYPHOON_CMD_ENABLE_WAKE_EVENTS cpu_to_le16(0x0049) |
| #define TYPHOON_CMD_GET_CMD_LVL cpu_to_le16(0x0069) |
| #define TYPHOON_CMD_GET_IPSEC_ENABLE cpu_to_le16(0x0067) |
| #define TYPHOON_CMD_GOTO_SLEEP cpu_to_le16(0x0023) |
| #define TYPHOON_CMD_HALT cpu_to_le16(0x005d) |
| #define TYPHOON_CMD_HELLO_RESP cpu_to_le16(0x0057) |
| #define TYPHOON_CMD_IRQ_COALESCE_CTRL cpu_to_le16(0x0045) |
| #define TYPHOON_CMD_READ_IPSEC_INFO cpu_to_le16(0x005e) |
| #define TYPHOON_CMD_READ_MAC_ADDRESS cpu_to_le16(0x0027) |
| #define TYPHOON_CMD_READ_MEDIA_STATUS cpu_to_le16(0x001b) |
| #define TYPHOON_CMD_READ_STATS cpu_to_le16(0x0007) |
| #define TYPHOON_CMD_READ_VERSIONS cpu_to_le16(0x0043) |
| #define TYPHOON_CMD_RX_DISABLE cpu_to_le16(0x0004) |
| #define TYPHOON_CMD_RX_ENABLE cpu_to_le16(0x0003) |
| #define TYPHOON_CMD_SET_MAC_ADDRESS cpu_to_le16(0x0026) |
| #define TYPHOON_CMD_SET_MAX_PKT_SIZE cpu_to_le16(0x001a) |
| #define TYPHOON_CMD_SET_MULTICAST_HASH cpu_to_le16(0x0025) |
| #define TYPHOON_CMD_SET_OFFLOAD_TASKS cpu_to_le16(0x004f) |
| #define TYPHOON_CMD_SET_RX_FILTER cpu_to_le16(0x0005) |
| #define TYPHOON_CMD_TX_DISABLE cpu_to_le16(0x0002) |
| #define TYPHOON_CMD_TX_ENABLE cpu_to_le16(0x0001) |
| #define TYPHOON_CMD_VLAN_TYPE_WRITE cpu_to_le16(0x002b) |
| #define TYPHOON_CMD_XCVR_SELECT cpu_to_le16(0x0013) |
| #define TYPHOON_INTR_BOOTCMD TYPHOON_INTR_ARM2HOST0 |
| #define TYPHOON_IPSEC_GEN_IV cpu_to_le16(0x0000) |
| #define TYPHOON_IPSEC_USE_IV cpu_to_le16(0x0001) |
| #define TYPHOON_LINK_100MBPS cpu_to_le32(0x00000002) |
| #define TYPHOON_LINK_10MBPS cpu_to_le32(0x00000000) |
| #define TYPHOON_LINK_BAD cpu_to_le32(0x00000000) |
| #define TYPHOON_LINK_DUPLEX_MASK cpu_to_le32(0x00000004) |
| #define TYPHOON_LINK_FULL_DUPLEX cpu_to_le32(0x00000004) |
| #define TYPHOON_LINK_GOOD cpu_to_le32(0x00000001) |
| #define TYPHOON_LINK_HALF_DUPLEX cpu_to_le32(0x00000000) |
| #define TYPHOON_LINK_SPEED_MASK cpu_to_le32(0x00000002) |
| #define TYPHOON_LINK_STAT_MASK cpu_to_le32(0x00000001) |
| #define TYPHOON_MCAST_HASH_DISABLE cpu_to_le16(0x0000) |
| #define TYPHOON_MCAST_HASH_ENABLE cpu_to_le16(0x0001) |
| #define TYPHOON_MCAST_HASH_SET cpu_to_le16(0x0002) |
| #define TYPHOON_MEDIA_STAT_CARRIER_SENSE cpu_to_le16(0x0020) |
| #define TYPHOON_MEDIA_STAT_COLLISION_DETECT cpu_to_le16(0x0010) |
| #define TYPHOON_MEDIA_STAT_CRC_STRIP_DISABLE cpu_to_le16(0x0004) |
| #define TYPHOON_MEDIA_STAT_NO_LINK cpu_to_le16(0x0800) |
| #define TYPHOON_MEDIA_STAT_POLARITY_REV cpu_to_le16(0x0400) |
| #define TYPHOON_OFFLOAD_BCAST_THROTTLE cpu_to_le32(0x00000020) |
| #define TYPHOON_OFFLOAD_DHCP_PREVENT cpu_to_le32(0x00000040) |
| #define TYPHOON_OFFLOAD_FILTERING cpu_to_le32(0x00000100) |
| #define TYPHOON_OFFLOAD_IP_CHKSUM cpu_to_le32(0x00000008) |
| #define TYPHOON_OFFLOAD_IPSEC cpu_to_le32(0x00000010) |
| #define TYPHOON_OFFLOAD_TCP_CHKSUM cpu_to_le32(0x00000002) |
| #define TYPHOON_OFFLOAD_TCP_SEGMENT cpu_to_le32(0x00000200) |
| #define TYPHOON_OFFLOAD_UDP_CHKSUM cpu_to_le32(0x00000004) |
| #define TYPHOON_OFFLOAD_VLAN cpu_to_le32(0x00000080) |
| #define TYPHOON_REG_BOOT_CHECKSUM TYPHOON_REG_HOST2ARM2 |
| #define TYPHOON_REG_BOOT_DATA_HI TYPHOON_REG_HOST2ARM4 |
| #define TYPHOON_REG_BOOT_DATA_LO TYPHOON_REG_HOST2ARM5 |
| #define TYPHOON_REG_BOOT_DEST_ADDR TYPHOON_REG_HOST2ARM3 |
| #define TYPHOON_REG_BOOT_LENGTH TYPHOON_REG_HOST2ARM1 |
| #define TYPHOON_REG_BOOT_RECORD_ADDR_HI TYPHOON_REG_HOST2ARM2 |
| #define TYPHOON_REG_BOOT_RECORD_ADDR_LO TYPHOON_REG_HOST2ARM1 |
| #define TYPHOON_REG_CMD_READY TYPHOON_REG_HOST2ARM2 |
| #define TYPHOON_REG_COMMAND TYPHOON_REG_HOST2ARM0 |
| #define TYPHOON_REG_DOWNLOAD_BOOT_ADDR TYPHOON_REG_HOST2ARM1 |
| #define TYPHOON_REG_DOWNLOAD_HMAC_0 TYPHOON_REG_HOST2ARM2 |
| #define TYPHOON_REG_DOWNLOAD_HMAC_1 TYPHOON_REG_HOST2ARM3 |
| #define TYPHOON_REG_DOWNLOAD_HMAC_2 TYPHOON_REG_HOST2ARM4 |
| #define TYPHOON_REG_DOWNLOAD_HMAC_3 TYPHOON_REG_HOST2ARM5 |
| #define TYPHOON_REG_DOWNLOAD_HMAC_4 TYPHOON_REG_HOST2ARM6 |
| #define TYPHOON_REG_HEARTBEAT TYPHOON_REG_ARM2HOST3 |
| #define TYPHOON_REG_STATUS TYPHOON_REG_ARM2HOST0 |
| #define TYPHOON_REG_TX_HI_READY TYPHOON_REG_HOST2ARM1 |
| #define TYPHOON_REG_TX_LO_READY TYPHOON_REG_HOST2ARM3 |
| #define TYPHOON_RX_ERR_ALIGN cpu_to_le32(0x00000006) |
| #define TYPHOON_RX_ERR_BAD_SSD cpu_to_le32(0x00000002) |
| #define TYPHOON_RX_ERR_CRC cpu_to_le32(0x00000004) |
| #define TYPHOON_RX_ERR_DRIBBLE cpu_to_le32(0x00000007) |
| #define TYPHOON_RX_ERR_FIFO_UNDERRUN cpu_to_le32(0x00000001) |
| #define TYPHOON_RX_ERR_INTERNAL cpu_to_le32(0x00000000) |
| #define TYPHOON_RX_ERR_OVERSIZE cpu_to_le32(0x00000005) |
| #define TYPHOON_RX_ERR_RUNT cpu_to_le32(0x00000003) |
| #define TYPHOON_RX_ESP_FORMAT_ERR cpu_to_le16(0x0200) |
| #define TYPHOON_RX_FILTER_ALL_MCAST cpu_to_le16(0x0002) |
| #define TYPHOON_RX_FILTER_BROADCAST cpu_to_le16(0x0004) |
| #define TYPHOON_RX_FILTER_DIRECTED cpu_to_le16(0x0001) |
| #define TYPHOON_RX_FILTER_MASK cpu_to_le16(0x7fff) |
| #define TYPHOON_RX_FILTER_MCAST_HASH cpu_to_le16(0x0010) |
| #define TYPHOON_RX_FILTER_PROMISCOUS cpu_to_le16(0x0008) |
| #define TYPHOON_RX_FILTERED cpu_to_le16(0x8000) |
| #define TYPHOON_RX_INNER_AH_FAIL cpu_to_le16(0x0040) |
| #define TYPHOON_RX_INNER_AH_GOOD cpu_to_le16(0x0004) |
| #define TYPHOON_RX_INNER_ESP_FAIL cpu_to_le16(0x0080) |
| #define TYPHOON_RX_INNER_ESP_GOOD cpu_to_le16(0x0008) |
| #define TYPHOON_RX_IP_CHK_FAIL cpu_to_le32(0x00000020) |
| #define TYPHOON_RX_IP_CHK_GOOD cpu_to_le32(0x00000100) |
| #define TYPHOON_RX_IP_FRAG cpu_to_le32(0x00000008) |
| #define TYPHOON_RX_IPSEC cpu_to_le32(0x00000010) |
| #define TYPHOON_RX_OUTER_AH_FAIL cpu_to_le16(0x0010) |
| #define TYPHOON_RX_OUTER_AH_GOOD cpu_to_le16(0x0001) |
| #define TYPHOON_RX_OUTER_ESP_FAIL cpu_to_le16(0x0020) |
| #define TYPHOON_RX_OUTER_ESP_GOOD cpu_to_le16(0x0002) |
| #define TYPHOON_RX_PROTO_IP cpu_to_le32(0x00000001) |
| #define TYPHOON_RX_PROTO_IPX cpu_to_le32(0x00000002) |
| #define TYPHOON_RX_PROTO_MASK cpu_to_le32(0x00000003) |
| #define TYPHOON_RX_PROTO_UNKNOWN cpu_to_le32(0x00000000) |
| #define TYPHOON_RX_TCP_CHK_FAIL cpu_to_le32(0x00000040) |
| #define TYPHOON_RX_TCP_CHK_GOOD cpu_to_le32(0x00000200) |
| #define TYPHOON_RX_UDP_CHK_FAIL cpu_to_le32(0x00000080) |
| #define TYPHOON_RX_UDP_CHK_GOOD cpu_to_le32(0x00000400) |
| #define TYPHOON_RX_UNKNOWN_SA cpu_to_le16(0x0100) |
| #define TYPHOON_RX_VLAN cpu_to_le32(0x00000004) |
| #define TYPHOON_SA_MODE_AH cpu_to_le16(0x0001) |
| #define TYPHOON_SA_MODE_ESP cpu_to_le16(0x0002) |
| #define TYPHOON_SA_MODE_NULL cpu_to_le16(0x0000) |
| #define TYPHOON_TSO_FIRST cpu_to_le16(0x1000) |
| #define TYPHOON_TSO_LAST cpu_to_le16(0x2000) |
| #define TYPHOON_TX_PF_INSERT_VLAN cpu_to_le32(0x00000010) |
| #define TYPHOON_TX_PF_INTERNAL cpu_to_le32(0xf0000000) |
| #define TYPHOON_TX_PF_IP_CHKSUM cpu_to_le32(0x00000002) |
| #define TYPHOON_TX_PF_IPSEC cpu_to_le32(0x00000020) |
| #define TYPHOON_TX_PF_NO_CRC cpu_to_le32(0x00000001) |
| #define TYPHOON_TX_PF_PAD_FRAME cpu_to_le32(0x00000100) |
| #define TYPHOON_TX_PF_RESERVED cpu_to_le32(0x00000e00) |
| #define TYPHOON_TX_PF_TCP_CHKSUM cpu_to_le32(0x00000004) |
| #define TYPHOON_TX_PF_TCP_SEGMENT cpu_to_le32(0x00000008) |
| #define TYPHOON_TX_PF_UDP_CHKSUM cpu_to_le32(0x00000080) |
| #define TYPHOON_TX_PF_VLAN_MASK cpu_to_le32(0x0ffff000) |
| #define TYPHOON_TX_PF_VLAN_PRIORITY cpu_to_le32(0x00000040) |
| #define TYPHOON_WAKE_ARP cpu_to_le16(0x08) |
| #define TYPHOON_WAKE_ICMP_ECHO cpu_to_le16(0x04) |
| #define TYPHOON_WAKE_LINK_EVENT cpu_to_le16(0x02) |
| #define TYPHOON_WAKE_MAGIC_PKT cpu_to_le16(0x01) |
| #define TYPHOON_XCVR_100FULL cpu_to_le16(0x0003) |
| #define TYPHOON_XCVR_100HALF cpu_to_le16(0x0002) |
| #define TYPHOON_XCVR_10FULL cpu_to_le16(0x0001) |
| #define TYPHOON_XCVR_10HALF cpu_to_le16(0x0000) |
| #define TYPHOON_XCVR_AUTONEG cpu_to_le16(0x0004) |
1.8.2