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usb-host.c
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1 /*
2  * usb-host.c - OMAP USB Host
3  *
4  * This file will contain the board specific details for the
5  * Synopsys EHCI/OHCI host controller on OMAP3430 and onwards
6  *
7  * Copyright (C) 2007-2011 Texas Instruments
8  * Author: Vikram Pandita <[email protected]>
9  * Author: Keshava Munegowda <[email protected]>
10  *
11  * Generalization by:
12  * Felipe Balbi <[email protected]>
13  *
14  * This program is free software; you can redistribute it and/or modify
15  * it under the terms of the GNU General Public License version 2 as
16  * published by the Free Software Foundation.
17  */
18 
19 #include <linux/types.h>
20 #include <linux/errno.h>
21 #include <linux/delay.h>
22 #include <linux/platform_device.h>
23 #include <linux/slab.h>
24 #include <linux/dma-mapping.h>
25 
26 #include <asm/io.h>
27 
28 #include <plat/usb.h>
29 #include <plat/omap_device.h>
30 
31 #include "mux.h"
32 
33 #ifdef CONFIG_MFD_OMAP_USB_HOST
34 
35 #define OMAP_USBHS_DEVICE "usbhs_omap"
36 #define OMAP_USBTLL_DEVICE "usbhs_tll"
37 #define USBHS_UHH_HWMODNAME "usb_host_hs"
38 #define USBHS_TLL_HWMODNAME "usb_tll_hs"
39 
40 static struct usbhs_omap_platform_data usbhs_data;
41 static struct usbtll_omap_platform_data usbtll_data;
42 static struct ehci_hcd_omap_platform_data ehci_data;
43 static struct ohci_hcd_omap_platform_data ohci_data;
44 
45 static struct omap_device_pm_latency omap_uhhtll_latency[] = {
46  {
48  .activate_func = omap_device_enable_hwmods,
50  },
51 };
52 
53 /* MUX settings for EHCI pins */
54 /*
55  * setup_ehci_io_mux - initialize IO pad mux for USBHOST
56  */
57 static void __init setup_ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
58 {
59  switch (port_mode[0]) {
61  omap_mux_init_signal("hsusb1_stp", OMAP_PIN_OUTPUT);
62  omap_mux_init_signal("hsusb1_clk", OMAP_PIN_OUTPUT);
63  omap_mux_init_signal("hsusb1_dir", OMAP_PIN_INPUT_PULLDOWN);
64  omap_mux_init_signal("hsusb1_nxt", OMAP_PIN_INPUT_PULLDOWN);
65  omap_mux_init_signal("hsusb1_data0", OMAP_PIN_INPUT_PULLDOWN);
66  omap_mux_init_signal("hsusb1_data1", OMAP_PIN_INPUT_PULLDOWN);
67  omap_mux_init_signal("hsusb1_data2", OMAP_PIN_INPUT_PULLDOWN);
68  omap_mux_init_signal("hsusb1_data3", OMAP_PIN_INPUT_PULLDOWN);
69  omap_mux_init_signal("hsusb1_data4", OMAP_PIN_INPUT_PULLDOWN);
70  omap_mux_init_signal("hsusb1_data5", OMAP_PIN_INPUT_PULLDOWN);
71  omap_mux_init_signal("hsusb1_data6", OMAP_PIN_INPUT_PULLDOWN);
72  omap_mux_init_signal("hsusb1_data7", OMAP_PIN_INPUT_PULLDOWN);
73  break;
75  omap_mux_init_signal("hsusb1_tll_stp",
77  omap_mux_init_signal("hsusb1_tll_clk",
79  omap_mux_init_signal("hsusb1_tll_dir",
81  omap_mux_init_signal("hsusb1_tll_nxt",
83  omap_mux_init_signal("hsusb1_tll_data0",
85  omap_mux_init_signal("hsusb1_tll_data1",
87  omap_mux_init_signal("hsusb1_tll_data2",
89  omap_mux_init_signal("hsusb1_tll_data3",
91  omap_mux_init_signal("hsusb1_tll_data4",
93  omap_mux_init_signal("hsusb1_tll_data5",
95  omap_mux_init_signal("hsusb1_tll_data6",
97  omap_mux_init_signal("hsusb1_tll_data7",
99  break;
101  /* FALLTHROUGH */
102  default:
103  break;
104  }
105 
106  switch (port_mode[1]) {
108  omap_mux_init_signal("hsusb2_stp", OMAP_PIN_OUTPUT);
109  omap_mux_init_signal("hsusb2_clk", OMAP_PIN_OUTPUT);
110  omap_mux_init_signal("hsusb2_dir", OMAP_PIN_INPUT_PULLDOWN);
111  omap_mux_init_signal("hsusb2_nxt", OMAP_PIN_INPUT_PULLDOWN);
112  omap_mux_init_signal("hsusb2_data0",
114  omap_mux_init_signal("hsusb2_data1",
116  omap_mux_init_signal("hsusb2_data2",
118  omap_mux_init_signal("hsusb2_data3",
120  omap_mux_init_signal("hsusb2_data4",
122  omap_mux_init_signal("hsusb2_data5",
124  omap_mux_init_signal("hsusb2_data6",
126  omap_mux_init_signal("hsusb2_data7",
128  break;
130  omap_mux_init_signal("hsusb2_tll_stp",
132  omap_mux_init_signal("hsusb2_tll_clk",
134  omap_mux_init_signal("hsusb2_tll_dir",
136  omap_mux_init_signal("hsusb2_tll_nxt",
138  omap_mux_init_signal("hsusb2_tll_data0",
140  omap_mux_init_signal("hsusb2_tll_data1",
142  omap_mux_init_signal("hsusb2_tll_data2",
144  omap_mux_init_signal("hsusb2_tll_data3",
146  omap_mux_init_signal("hsusb2_tll_data4",
148  omap_mux_init_signal("hsusb2_tll_data5",
150  omap_mux_init_signal("hsusb2_tll_data6",
152  omap_mux_init_signal("hsusb2_tll_data7",
154  break;
156  /* FALLTHROUGH */
157  default:
158  break;
159  }
160 
161  switch (port_mode[2]) {
163  printk(KERN_WARNING "Port3 can't be used in PHY mode\n");
164  break;
166  omap_mux_init_signal("hsusb3_tll_stp",
168  omap_mux_init_signal("hsusb3_tll_clk",
170  omap_mux_init_signal("hsusb3_tll_dir",
172  omap_mux_init_signal("hsusb3_tll_nxt",
174  omap_mux_init_signal("hsusb3_tll_data0",
176  omap_mux_init_signal("hsusb3_tll_data1",
178  omap_mux_init_signal("hsusb3_tll_data2",
180  omap_mux_init_signal("hsusb3_tll_data3",
182  omap_mux_init_signal("hsusb3_tll_data4",
184  omap_mux_init_signal("hsusb3_tll_data5",
186  omap_mux_init_signal("hsusb3_tll_data6",
188  omap_mux_init_signal("hsusb3_tll_data7",
190  break;
192  /* FALLTHROUGH */
193  default:
194  break;
195  }
196 
197  return;
198 }
199 
200 static
201 void __init setup_4430ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
202 {
203  switch (port_mode[0]) {
205  omap_mux_init_signal("usbb1_ulpiphy_stp",
207  omap_mux_init_signal("usbb1_ulpiphy_clk",
209  omap_mux_init_signal("usbb1_ulpiphy_dir",
211  omap_mux_init_signal("usbb1_ulpiphy_nxt",
213  omap_mux_init_signal("usbb1_ulpiphy_dat0",
215  omap_mux_init_signal("usbb1_ulpiphy_dat1",
217  omap_mux_init_signal("usbb1_ulpiphy_dat2",
219  omap_mux_init_signal("usbb1_ulpiphy_dat3",
221  omap_mux_init_signal("usbb1_ulpiphy_dat4",
223  omap_mux_init_signal("usbb1_ulpiphy_dat5",
225  omap_mux_init_signal("usbb1_ulpiphy_dat6",
227  omap_mux_init_signal("usbb1_ulpiphy_dat7",
229  break;
231  omap_mux_init_signal("usbb1_ulpitll_stp",
233  omap_mux_init_signal("usbb1_ulpitll_clk",
235  omap_mux_init_signal("usbb1_ulpitll_dir",
237  omap_mux_init_signal("usbb1_ulpitll_nxt",
239  omap_mux_init_signal("usbb1_ulpitll_dat0",
241  omap_mux_init_signal("usbb1_ulpitll_dat1",
243  omap_mux_init_signal("usbb1_ulpitll_dat2",
245  omap_mux_init_signal("usbb1_ulpitll_dat3",
247  omap_mux_init_signal("usbb1_ulpitll_dat4",
249  omap_mux_init_signal("usbb1_ulpitll_dat5",
251  omap_mux_init_signal("usbb1_ulpitll_dat6",
253  omap_mux_init_signal("usbb1_ulpitll_dat7",
255  break;
257  default:
258  break;
259  }
260  switch (port_mode[1]) {
262  omap_mux_init_signal("usbb2_ulpiphy_stp",
264  omap_mux_init_signal("usbb2_ulpiphy_clk",
266  omap_mux_init_signal("usbb2_ulpiphy_dir",
268  omap_mux_init_signal("usbb2_ulpiphy_nxt",
270  omap_mux_init_signal("usbb2_ulpiphy_dat0",
272  omap_mux_init_signal("usbb2_ulpiphy_dat1",
274  omap_mux_init_signal("usbb2_ulpiphy_dat2",
276  omap_mux_init_signal("usbb2_ulpiphy_dat3",
278  omap_mux_init_signal("usbb2_ulpiphy_dat4",
280  omap_mux_init_signal("usbb2_ulpiphy_dat5",
282  omap_mux_init_signal("usbb2_ulpiphy_dat6",
284  omap_mux_init_signal("usbb2_ulpiphy_dat7",
286  break;
288  omap_mux_init_signal("usbb2_ulpitll_stp",
290  omap_mux_init_signal("usbb2_ulpitll_clk",
292  omap_mux_init_signal("usbb2_ulpitll_dir",
294  omap_mux_init_signal("usbb2_ulpitll_nxt",
296  omap_mux_init_signal("usbb2_ulpitll_dat0",
298  omap_mux_init_signal("usbb2_ulpitll_dat1",
300  omap_mux_init_signal("usbb2_ulpitll_dat2",
302  omap_mux_init_signal("usbb2_ulpitll_dat3",
304  omap_mux_init_signal("usbb2_ulpitll_dat4",
306  omap_mux_init_signal("usbb2_ulpitll_dat5",
308  omap_mux_init_signal("usbb2_ulpitll_dat6",
310  omap_mux_init_signal("usbb2_ulpitll_dat7",
312  break;
314  default:
315  break;
316  }
317 }
318 
319 static void __init setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
320 {
321  switch (port_mode[0]) {
326  omap_mux_init_signal("mm1_rxdp",
328  omap_mux_init_signal("mm1_rxdm",
330  /* FALLTHROUGH */
333  omap_mux_init_signal("mm1_rxrcv",
335  /* FALLTHROUGH */
338  omap_mux_init_signal("mm1_txen_n", OMAP_PIN_OUTPUT);
339  /* FALLTHROUGH */
342  omap_mux_init_signal("mm1_txse0",
344  omap_mux_init_signal("mm1_txdat",
346  break;
348  /* FALLTHROUGH */
349  default:
350  break;
351  }
352  switch (port_mode[1]) {
357  omap_mux_init_signal("mm2_rxdp",
359  omap_mux_init_signal("mm2_rxdm",
361  /* FALLTHROUGH */
364  omap_mux_init_signal("mm2_rxrcv",
366  /* FALLTHROUGH */
369  omap_mux_init_signal("mm2_txen_n", OMAP_PIN_OUTPUT);
370  /* FALLTHROUGH */
373  omap_mux_init_signal("mm2_txse0",
375  omap_mux_init_signal("mm2_txdat",
377  break;
379  /* FALLTHROUGH */
380  default:
381  break;
382  }
383  switch (port_mode[2]) {
388  omap_mux_init_signal("mm3_rxdp",
390  omap_mux_init_signal("mm3_rxdm",
392  /* FALLTHROUGH */
395  omap_mux_init_signal("mm3_rxrcv",
397  /* FALLTHROUGH */
400  omap_mux_init_signal("mm3_txen_n", OMAP_PIN_OUTPUT);
401  /* FALLTHROUGH */
404  omap_mux_init_signal("mm3_txse0",
406  omap_mux_init_signal("mm3_txdat",
408  break;
410  /* FALLTHROUGH */
411  default:
412  break;
413  }
414 }
415 
416 static
417 void __init setup_4430ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
418 {
419  switch (port_mode[0]) {
424  omap_mux_init_signal("usbb1_mm_rxdp",
426  omap_mux_init_signal("usbb1_mm_rxdm",
428 
431  omap_mux_init_signal("usbb1_mm_rxrcv",
433 
436  omap_mux_init_signal("usbb1_mm_txen",
438 
439 
442  omap_mux_init_signal("usbb1_mm_txdat",
444  omap_mux_init_signal("usbb1_mm_txse0",
446  break;
447 
449  default:
450  break;
451  }
452 
453  switch (port_mode[1]) {
458  omap_mux_init_signal("usbb2_mm_rxdp",
460  omap_mux_init_signal("usbb2_mm_rxdm",
462 
465  omap_mux_init_signal("usbb2_mm_rxrcv",
467 
470  omap_mux_init_signal("usbb2_mm_txen",
472 
473 
476  omap_mux_init_signal("usbb2_mm_txdat",
478  omap_mux_init_signal("usbb2_mm_txse0",
480  break;
481 
483  default:
484  break;
485  }
486 }
487 
488 void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
489 {
490  struct omap_hwmod *uhh_hwm, *tll_hwm;
491  struct platform_device *pdev;
492  int bus_id = -1;
493  int i;
494 
495  for (i = 0; i < OMAP3_HS_USB_PORTS; i++) {
496  usbhs_data.port_mode[i] = pdata->port_mode[i];
497  usbtll_data.port_mode[i] = pdata->port_mode[i];
498  ohci_data.port_mode[i] = pdata->port_mode[i];
499  ehci_data.port_mode[i] = pdata->port_mode[i];
500  ehci_data.reset_gpio_port[i] = pdata->reset_gpio_port[i];
501  ehci_data.regulator[i] = pdata->regulator[i];
502  }
503  ehci_data.phy_reset = pdata->phy_reset;
504  ohci_data.es2_compatibility = pdata->es2_compatibility;
505  usbhs_data.ehci_data = &ehci_data;
506  usbhs_data.ohci_data = &ohci_data;
507 
508  if (cpu_is_omap34xx()) {
509  setup_ehci_io_mux(pdata->port_mode);
510  setup_ohci_io_mux(pdata->port_mode);
511  } else if (cpu_is_omap44xx()) {
512  setup_4430ehci_io_mux(pdata->port_mode);
513  setup_4430ohci_io_mux(pdata->port_mode);
514  }
515 
516  uhh_hwm = omap_hwmod_lookup(USBHS_UHH_HWMODNAME);
517  if (!uhh_hwm) {
518  pr_err("Could not look up %s\n", USBHS_UHH_HWMODNAME);
519  return;
520  }
521 
522  tll_hwm = omap_hwmod_lookup(USBHS_TLL_HWMODNAME);
523  if (!tll_hwm) {
524  pr_err("Could not look up %s\n", USBHS_TLL_HWMODNAME);
525  return;
526  }
527 
528  pdev = omap_device_build(OMAP_USBTLL_DEVICE, bus_id, tll_hwm,
529  &usbtll_data, sizeof(usbtll_data),
530  omap_uhhtll_latency,
531  ARRAY_SIZE(omap_uhhtll_latency), false);
532  if (IS_ERR(pdev)) {
533  pr_err("Could not build hwmod device %s\n",
534  USBHS_TLL_HWMODNAME);
535  return;
536  }
537 
538  pdev = omap_device_build(OMAP_USBHS_DEVICE, bus_id, uhh_hwm,
539  &usbhs_data, sizeof(usbhs_data),
540  omap_uhhtll_latency,
541  ARRAY_SIZE(omap_uhhtll_latency), false);
542  if (IS_ERR(pdev)) {
543  pr_err("Could not build hwmod devices %s\n",
544  USBHS_UHH_HWMODNAME);
545  return;
546  }
547 }
548 
549 #else
550 
551 void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
552 {
553 }
554 
555 #endif