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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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#include <linux/dma-mapping.h>Go to the source code of this file.
Data Structures | |
| struct | _drm_via_sg_info |
| struct | _drm_via_blitq |
Macros | |
| #define | VIA_NUM_BLIT_ENGINES 2 |
| #define | VIA_NUM_BLIT_SLOTS 8 |
| #define | VIA_PCI_DMA_MAR0 0xE40 /* Memory Address Register of Channel 0 */ |
| #define | VIA_PCI_DMA_DAR0 0xE44 /* Device Address Register of Channel 0 */ |
| #define | VIA_PCI_DMA_BCR0 0xE48 /* Byte Count Register of Channel 0 */ |
| #define | VIA_PCI_DMA_DPR0 0xE4C /* Descriptor Pointer Register of Channel 0 */ |
| #define | VIA_PCI_DMA_MAR1 0xE50 /* Memory Address Register of Channel 1 */ |
| #define | VIA_PCI_DMA_DAR1 0xE54 /* Device Address Register of Channel 1 */ |
| #define | VIA_PCI_DMA_BCR1 0xE58 /* Byte Count Register of Channel 1 */ |
| #define | VIA_PCI_DMA_DPR1 0xE5C /* Descriptor Pointer Register of Channel 1 */ |
| #define | VIA_PCI_DMA_MAR2 0xE60 /* Memory Address Register of Channel 2 */ |
| #define | VIA_PCI_DMA_DAR2 0xE64 /* Device Address Register of Channel 2 */ |
| #define | VIA_PCI_DMA_BCR2 0xE68 /* Byte Count Register of Channel 2 */ |
| #define | VIA_PCI_DMA_DPR2 0xE6C /* Descriptor Pointer Register of Channel 2 */ |
| #define | VIA_PCI_DMA_MAR3 0xE70 /* Memory Address Register of Channel 3 */ |
| #define | VIA_PCI_DMA_DAR3 0xE74 /* Device Address Register of Channel 3 */ |
| #define | VIA_PCI_DMA_BCR3 0xE78 /* Byte Count Register of Channel 3 */ |
| #define | VIA_PCI_DMA_DPR3 0xE7C /* Descriptor Pointer Register of Channel 3 */ |
| #define | VIA_PCI_DMA_MR0 0xE80 /* Mode Register of Channel 0 */ |
| #define | VIA_PCI_DMA_MR1 0xE84 /* Mode Register of Channel 1 */ |
| #define | VIA_PCI_DMA_MR2 0xE88 /* Mode Register of Channel 2 */ |
| #define | VIA_PCI_DMA_MR3 0xE8C /* Mode Register of Channel 3 */ |
| #define | VIA_PCI_DMA_CSR0 0xE90 /* Command/Status Register of Channel 0 */ |
| #define | VIA_PCI_DMA_CSR1 0xE94 /* Command/Status Register of Channel 1 */ |
| #define | VIA_PCI_DMA_CSR2 0xE98 /* Command/Status Register of Channel 2 */ |
| #define | VIA_PCI_DMA_CSR3 0xE9C /* Command/Status Register of Channel 3 */ |
| #define | VIA_PCI_DMA_PTR 0xEA0 /* Priority Type Register */ |
| #define | VIA_DMA_DPR_EC (1<<1) /* end of chain */ |
| #define | VIA_DMA_DPR_DDIE (1<<2) /* descriptor done interrupt enable */ |
| #define | VIA_DMA_DPR_DT (1<<3) /* direction of transfer (RO) */ |
| #define | VIA_DMA_MR_CM (1<<0) /* chaining mode */ |
| #define | VIA_DMA_MR_TDIE (1<<1) /* transfer done interrupt enable */ |
| #define | VIA_DMA_MR_HENDMACMD (1<<7) /* ? */ |
| #define | VIA_DMA_CSR_DE (1<<0) /* DMA enable */ |
| #define | VIA_DMA_CSR_TS (1<<1) /* transfer start */ |
| #define | VIA_DMA_CSR_TA (1<<2) /* transfer abort */ |
| #define | VIA_DMA_CSR_TD (1<<3) /* transfer done */ |
| #define | VIA_DMA_CSR_DD (1<<4) /* descriptor done */ |
| #define | VIA_DMA_DPR_EC (1<<1) /* end of chain */ |
Typedefs | |
| typedef struct _drm_via_sg_info | drm_via_sg_info_t |
| typedef struct _drm_via_blitq | drm_via_blitq_t |
| #define VIA_DMA_CSR_DD (1<<4) /* descriptor done */ |
Definition at line 135 of file via_dmablit.h.
Definition at line 131 of file via_dmablit.h.
| #define VIA_DMA_CSR_TA (1<<2) /* transfer abort */ |
Definition at line 133 of file via_dmablit.h.
| #define VIA_DMA_CSR_TD (1<<3) /* transfer done */ |
Definition at line 134 of file via_dmablit.h.
| #define VIA_DMA_CSR_TS (1<<1) /* transfer start */ |
Definition at line 132 of file via_dmablit.h.
| #define VIA_DMA_DPR_DDIE (1<<2) /* descriptor done interrupt enable */ |
Definition at line 122 of file via_dmablit.h.
Definition at line 123 of file via_dmablit.h.
Definition at line 136 of file via_dmablit.h.
Definition at line 136 of file via_dmablit.h.
| #define VIA_DMA_MR_CM (1<<0) /* chaining mode */ |
Definition at line 126 of file via_dmablit.h.
| #define VIA_DMA_MR_HENDMACMD (1<<7) /* ? */ |
Definition at line 128 of file via_dmablit.h.
Definition at line 127 of file via_dmablit.h.
| #define VIA_NUM_BLIT_ENGINES 2 |
Definition at line 35 of file via_dmablit.h.
| #define VIA_NUM_BLIT_SLOTS 8 |
Definition at line 36 of file via_dmablit.h.
| #define VIA_PCI_DMA_BCR0 0xE48 /* Byte Count Register of Channel 0 */ |
Definition at line 89 of file via_dmablit.h.
| #define VIA_PCI_DMA_BCR1 0xE58 /* Byte Count Register of Channel 1 */ |
Definition at line 94 of file via_dmablit.h.
| #define VIA_PCI_DMA_BCR2 0xE68 /* Byte Count Register of Channel 2 */ |
Definition at line 99 of file via_dmablit.h.
| #define VIA_PCI_DMA_BCR3 0xE78 /* Byte Count Register of Channel 3 */ |
Definition at line 104 of file via_dmablit.h.
| #define VIA_PCI_DMA_CSR0 0xE90 /* Command/Status Register of Channel 0 */ |
Definition at line 112 of file via_dmablit.h.
| #define VIA_PCI_DMA_CSR1 0xE94 /* Command/Status Register of Channel 1 */ |
Definition at line 113 of file via_dmablit.h.
| #define VIA_PCI_DMA_CSR2 0xE98 /* Command/Status Register of Channel 2 */ |
Definition at line 114 of file via_dmablit.h.
| #define VIA_PCI_DMA_CSR3 0xE9C /* Command/Status Register of Channel 3 */ |
Definition at line 115 of file via_dmablit.h.
| #define VIA_PCI_DMA_DAR0 0xE44 /* Device Address Register of Channel 0 */ |
Definition at line 88 of file via_dmablit.h.
| #define VIA_PCI_DMA_DAR1 0xE54 /* Device Address Register of Channel 1 */ |
Definition at line 93 of file via_dmablit.h.
| #define VIA_PCI_DMA_DAR2 0xE64 /* Device Address Register of Channel 2 */ |
Definition at line 98 of file via_dmablit.h.
| #define VIA_PCI_DMA_DAR3 0xE74 /* Device Address Register of Channel 3 */ |
Definition at line 103 of file via_dmablit.h.
| #define VIA_PCI_DMA_DPR0 0xE4C /* Descriptor Pointer Register of Channel 0 */ |
Definition at line 90 of file via_dmablit.h.
| #define VIA_PCI_DMA_DPR1 0xE5C /* Descriptor Pointer Register of Channel 1 */ |
Definition at line 95 of file via_dmablit.h.
| #define VIA_PCI_DMA_DPR2 0xE6C /* Descriptor Pointer Register of Channel 2 */ |
Definition at line 100 of file via_dmablit.h.
| #define VIA_PCI_DMA_DPR3 0xE7C /* Descriptor Pointer Register of Channel 3 */ |
Definition at line 105 of file via_dmablit.h.
| #define VIA_PCI_DMA_MAR0 0xE40 /* Memory Address Register of Channel 0 */ |
Definition at line 87 of file via_dmablit.h.
| #define VIA_PCI_DMA_MAR1 0xE50 /* Memory Address Register of Channel 1 */ |
Definition at line 92 of file via_dmablit.h.
| #define VIA_PCI_DMA_MAR2 0xE60 /* Memory Address Register of Channel 2 */ |
Definition at line 97 of file via_dmablit.h.
| #define VIA_PCI_DMA_MAR3 0xE70 /* Memory Address Register of Channel 3 */ |
Definition at line 102 of file via_dmablit.h.
| #define VIA_PCI_DMA_MR0 0xE80 /* Mode Register of Channel 0 */ |
Definition at line 107 of file via_dmablit.h.
| #define VIA_PCI_DMA_MR1 0xE84 /* Mode Register of Channel 1 */ |
Definition at line 108 of file via_dmablit.h.
| #define VIA_PCI_DMA_MR2 0xE88 /* Mode Register of Channel 2 */ |
Definition at line 109 of file via_dmablit.h.
| #define VIA_PCI_DMA_MR3 0xE8C /* Mode Register of Channel 3 */ |
Definition at line 110 of file via_dmablit.h.
| #define VIA_PCI_DMA_PTR 0xEA0 /* Priority Type Register */ |
Definition at line 117 of file via_dmablit.h.
| typedef struct _drm_via_blitq drm_via_blitq_t |
| typedef struct _drm_via_sg_info drm_via_sg_info_t |
1.8.2