Macros
#define	CRA(blk, sub, adr) ((((blk) & 0x7) << 13) \| (((sub) & 0xf) << 9) \| (((adr) & 0xff) << 1))

#define	REG_CHIP_ID CRA(0x7,0xf,0x00) /* Chip ID */

#define	REG_BLADE_ID CRA(0x7,0xf,0x01) /* Blade ID */

#define	REG_SW_RESET CRA(0x7,0xf,0x02) /* Global Soft Reset */

#define	REG_MEM_BIST CRA(0x7,0xf,0x04) /* mem */

#define	REG_IFACE_MODE CRA(0x7,0xf,0x07) /* Interface mode */

#define	REG_MSCH CRA(0x7,0x2,0x06) /* CRC error count */

#define	REG_CRC_CNT CRA(0x7,0x2,0x0a) /* CRC error count */

#define	REG_CRC_CFG CRA(0x7,0x2,0x0b) /* CRC config */

#define	REG_SI_TRANSFER_SEL CRA(0x7,0xf,0x18) /* SI Transfer Select */

#define	REG_PLL_CLK_SPEED CRA(0x7,0xf,0x19) /* Clock Speed Selection */

#define	REG_SYS_CLK_SELECT CRA(0x7,0xf,0x1c) /* System Clock Select */

#define	REG_GPIO_CTRL CRA(0x7,0xf,0x1d) /* GPIO Control */

#define	REG_GPIO_OUT CRA(0x7,0xf,0x1e) /* GPIO Out */

#define	REG_GPIO_IN CRA(0x7,0xf,0x1f) /* GPIO In */

#define	REG_CPU_TRANSFER_SEL CRA(0x7,0xf,0x20) /* CPU Transfer Select */

#define	REG_LOCAL_DATA CRA(0x7,0xf,0xfe) /* Local CPU Data Register */

#define	REG_LOCAL_STATUS CRA(0x7,0xf,0xff) /* Local CPU Status Register */

#define	REG_AGGR_SETUP CRA(0x7,0x1,0x00) /* Aggregator Setup */

#define	REG_PMAP_TABLE CRA(0x7,0x1,0x01) /* Port map table */

#define	REG_MPLS_BIT0 CRA(0x7,0x1,0x08) /* MPLS bit0 position */

#define	REG_MPLS_BIT1 CRA(0x7,0x1,0x09) /* MPLS bit1 position */

#define	REG_MPLS_BIT2 CRA(0x7,0x1,0x0a) /* MPLS bit2 position */

#define	REG_MPLS_BIT3 CRA(0x7,0x1,0x0b) /* MPLS bit3 position */

#define	REG_MPLS_BITMASK CRA(0x7,0x1,0x0c) /* MPLS bit mask */

#define	REG_PRE_BIT0POS CRA(0x7,0x1,0x10) /* Preamble bit0 position */

#define	REG_PRE_BIT1POS CRA(0x7,0x1,0x11) /* Preamble bit1 position */

#define	REG_PRE_BIT2POS CRA(0x7,0x1,0x12) /* Preamble bit2 position */

#define	REG_PRE_BIT3POS CRA(0x7,0x1,0x13) /* Preamble bit3 position */

#define	REG_PRE_ERR_CNT CRA(0x7,0x1,0x14) /* Preamble parity error count */

#define	REG_RAM_BIST_CMD CRA(0x7,0x1,0x00) /* RAM BIST Command Register */

#define	REG_RAM_BIST_RESULT CRA(0x7,0x1,0x01) /* RAM BIST Read Status/Result */

#define	BIST_PORT_SELECT 0x00 /* BIST port select */

#define	BIST_COMMAND 0x01 /* BIST enable/disable */

#define	BIST_STATUS 0x02 /* BIST operation status */

#define	BIST_ERR_CNT_LSB 0x03 /* BIST error count lo 8b */

#define	BIST_ERR_CNT_MSB 0x04 /* BIST error count hi 8b */

#define	BIST_ERR_SEL_LSB 0x05 /* BIST error select lo 8b */

#define	BIST_ERR_SEL_MSB 0x06 /* BIST error select hi 8b */

#define	BIST_ERROR_STATE 0x07 /* BIST engine internal state */

#define	BIST_ERR_ADR0 0x08 /* BIST error address lo 8b */

#define	BIST_ERR_ADR1 0x09 /* BIST error address lomid 8b */

#define	BIST_ERR_ADR2 0x0a /* BIST error address himid 8b */

#define	BIST_ERR_ADR3 0x0b /* BIST error address hi 8b */

#define	REG_TEST(ie, fn) CRA(0x2,ie&1,0x00+fn) /* Mode & Test Register */

#define	REG_TOP_BOTTOM(ie, fn) CRA(0x2,ie&1,0x10+fn) /* FIFO Buffer Top & Bottom */

#define	REG_TAIL(ie, fn) CRA(0x2,ie&1,0x20+fn) /* FIFO Write Pointer */

#define	REG_HEAD(ie, fn) CRA(0x2,ie&1,0x30+fn) /* FIFO Read Pointer */

#define	REG_HIGH_LOW_WM(ie, fn) CRA(0x2,ie&1,0x40+fn) /* Flow Control Water Marks */

#define	REG_CT_THRHLD(ie, fn) CRA(0x2,ie&1,0x50+fn) /* Cut Through Threshold */

#define	REG_FIFO_DROP_CNT(ie, fn) CRA(0x2,ie&1,0x60+fn) /* Drop & CRC Error Counter */

#define	REG_DEBUG_BUF_CNT(ie, fn) CRA(0x2,ie&1,0x70+fn) /* Input Side Debug Counter */

#define	REG_BUCKI(fn) CRA(0x2,2,0x20+fn) /* Input Side Debug Counter */

#define	REG_BUCKE(fn) CRA(0x2,3,0x20+fn) /* Input Side Debug Counter */

#define	REG_TRAFFIC_SHAPER_BUCKET(ie, bn) CRA(0x2,ie&1,0x0a + (bn>7) \| ((bn&7)<<4))

#define	REG_TRAFFIC_SHAPER_CONTROL(ie) CRA(0x2,ie&1,0x3b)

#define	REG_SRAM_ADR(ie) CRA(0x2,ie&1,0x0e) /* FIFO SRAM address */

#define	REG_SRAM_WR_STRB(ie) CRA(0x2,ie&1,0x1e) /* FIFO SRAM write strobe */

#define	REG_SRAM_RD_STRB(ie) CRA(0x2,ie&1,0x2e) /* FIFO SRAM read strobe */

#define	REG_SRAM_DATA_0(ie) CRA(0x2,ie&1,0x3e) /* FIFO SRAM data lo 8b */

#define	REG_SRAM_DATA_1(ie) CRA(0x2,ie&1,0x4e) /* FIFO SRAM data lomid 8b */

#define	REG_SRAM_DATA_2(ie) CRA(0x2,ie&1,0x5e) /* FIFO SRAM data himid 8b */

#define	REG_SRAM_DATA_3(ie) CRA(0x2,ie&1,0x6e) /* FIFO SRAM data hi 8b */

#define	REG_SRAM_DATA_BLK_TYPE(ie) CRA(0x2,ie&1,0x7e) /* FIFO SRAM tag */

#define	REG_CONTROL(ie) CRA(0x2,ie&1,0x0f) /* FIFO control */

#define	REG_ING_CONTROL CRA(0x2,0x0,0x0f) /* Ingress control (alias) */

#define	REG_EGR_CONTROL CRA(0x2,0x1,0x0f) /* Egress control (alias) */

#define	REG_AGE_TIMER(ie) CRA(0x2,ie&1,0x1f) /* Aging timer */

#define	REG_AGE_INC(ie) CRA(0x2,ie&1,0x2f) /* Aging increment */

#define	DEBUG_OUT(ie) CRA(0x2,ie&1,0x3f) /* Output debug counter control */

#define	DEBUG_CNT(ie) CRA(0x2,ie&1,0x4f) /* Output debug counter */

#define	REG_SPI4_MISC CRA(0x5,0x0,0x00) /* Misc Register */

#define	REG_SPI4_STATUS CRA(0x5,0x0,0x01) /* CML Status */

#define	REG_SPI4_ING_SETUP0 CRA(0x5,0x0,0x02) /* Ingress Status Channel Setup */

#define	REG_SPI4_ING_SETUP1 CRA(0x5,0x0,0x03) /* Ingress Data Training Setup */

#define	REG_SPI4_ING_SETUP2 CRA(0x5,0x0,0x04) /* Ingress Data Burst Size Setup */

#define	REG_SPI4_EGR_SETUP0 CRA(0x5,0x0,0x05) /* Egress Status Channel Setup */

#define	REG_SPI4_DBG_CNT(n) CRA(0x5,0x0,0x10+n) /* Debug counters 0-9 */

#define	REG_SPI4_DBG_SETUP CRA(0x5,0x0,0x1A) /* Debug counters setup */

#define	REG_SPI4_TEST CRA(0x5,0x0,0x20) /* Test Setup Register */

#define	REG_TPGEN_UP0 CRA(0x5,0x0,0x21) /* Test Pattern generator user pattern 0 */

#define	REG_TPGEN_UP1 CRA(0x5,0x0,0x22) /* Test Pattern generator user pattern 1 */

#define	REG_TPCHK_UP0 CRA(0x5,0x0,0x23) /* Test Pattern checker user pattern 0 */

#define	REG_TPCHK_UP1 CRA(0x5,0x0,0x24) /* Test Pattern checker user pattern 1 */

#define	REG_TPSAM_P0 CRA(0x5,0x0,0x25) /* Sampled pattern 0 */

#define	REG_TPSAM_P1 CRA(0x5,0x0,0x26) /* Sampled pattern 1 */

#define	REG_TPERR_CNT CRA(0x5,0x0,0x27) /* Pattern checker error counter */

#define	REG_SPI4_STICKY CRA(0x5,0x0,0x30) /* Sticky bits register */

#define	REG_SPI4_DBG_INH CRA(0x5,0x0,0x31) /* Core egress & ingress inhibit */

#define	REG_SPI4_DBG_STATUS CRA(0x5,0x0,0x32) /* Sampled ingress status */

#define	REG_SPI4_DBG_GRANT CRA(0x5,0x0,0x33) /* Ingress cranted credit value */

#define	REG_SPI4_DESKEW CRA(0x5,0x0,0x43) /* Ingress cranted credit value */

#define	REG_MISC_10G CRA(0x1,0xa,0x00) /* Misc 10GbE setup */

#define	REG_PAUSE_10G CRA(0x1,0xa,0x01) /* Pause register */

#define	REG_NORMALIZER_10G CRA(0x1,0xa,0x05) /* 10G normalizer */

#define	REG_STICKY_RX CRA(0x1,0xa,0x06) /* RX debug register */

#define	REG_DENORM_10G CRA(0x1,0xa,0x07) /* Denormalizer */

#define	REG_STICKY_TX CRA(0x1,0xa,0x08) /* TX sticky bits */

#define	REG_MAX_RXHIGH CRA(0x1,0xa,0x0a) /* XGMII lane 0-3 debug */

#define	REG_MAX_RXLOW CRA(0x1,0xa,0x0b) /* XGMII lane 4-7 debug */

#define	REG_MAC_TX_STICKY CRA(0x1,0xa,0x0c) /* MAC Tx state sticky debug */

#define	REG_MAC_TX_RUNNING CRA(0x1,0xa,0x0d) /* MAC Tx state running debug */

#define	REG_TX_ABORT_AGE CRA(0x1,0xa,0x14) /* Aged Tx frames discarded */

#define	REG_TX_ABORT_SHORT CRA(0x1,0xa,0x15) /* Short Tx frames discarded */

#define	REG_TX_ABORT_TAXI CRA(0x1,0xa,0x16) /* Taxi error frames discarded */

#define	REG_TX_ABORT_UNDERRUN CRA(0x1,0xa,0x17) /* Tx Underrun abort counter */

#define	REG_TX_DENORM_DISCARD CRA(0x1,0xa,0x18) /* Tx denormalizer discards */

#define	REG_XAUI_STAT_A CRA(0x1,0xa,0x20) /* XAUI status A */

#define	REG_XAUI_STAT_B CRA(0x1,0xa,0x21) /* XAUI status B */

#define	REG_XAUI_STAT_C CRA(0x1,0xa,0x22) /* XAUI status C */

#define	REG_XAUI_CONF_A CRA(0x1,0xa,0x23) /* XAUI configuration A */

#define	REG_XAUI_CONF_B CRA(0x1,0xa,0x24) /* XAUI configuration B */

#define	REG_XAUI_CODE_GRP_CNT CRA(0x1,0xa,0x25) /* XAUI code group error count */

#define	REG_XAUI_CONF_TEST_A CRA(0x1,0xa,0x26) /* XAUI test register A */

#define	REG_PDERRCNT CRA(0x1,0xa,0x27) /* XAUI test register B */

#define	REG_MAX_LEN(pn) CRA(0x1,pn,0x02) /* Max length */

#define	REG_MAC_HIGH_ADDR(pn) CRA(0x1,pn,0x03) /* Upper 24 bits of MAC addr */

#define	REG_MAC_LOW_ADDR(pn) CRA(0x1,pn,0x04) /* Lower 24 bits of MAC addr */

#define	REG_MODE_CFG(pn) CRA(0x1,pn,0x00) /* Mode configuration */

#define	REG_PAUSE_CFG(pn) CRA(0x1,pn,0x01) /* Pause configuration */

#define	REG_NORMALIZER(pn) CRA(0x1,pn,0x05) /* Normalizer */

#define	REG_TBI_STATUS(pn) CRA(0x1,pn,0x06) /* TBI status */

#define	REG_PCS_STATUS_DBG(pn) CRA(0x1,pn,0x07) /* PCS status debug */

#define	REG_PCS_CTRL(pn) CRA(0x1,pn,0x08) /* PCS control */

#define	REG_TBI_CONFIG(pn) CRA(0x1,pn,0x09) /* TBI configuration */

#define	REG_STICK_BIT(pn) CRA(0x1,pn,0x0a) /* Sticky bits */

#define	REG_DEV_SETUP(pn) CRA(0x1,pn,0x0b) /* MAC clock/reset setup */

#define	REG_DROP_CNT(pn) CRA(0x1,pn,0x0c) /* Drop counter */

#define	REG_PORT_POS(pn) CRA(0x1,pn,0x0d) /* Preamble port position */

#define	REG_PORT_FAIL(pn) CRA(0x1,pn,0x0e) /* Preamble port position */

#define	REG_SERDES_CONF(pn) CRA(0x1,pn,0x0f) /* SerDes configuration */

#define	REG_SERDES_TEST(pn) CRA(0x1,pn,0x10) /* SerDes test */

#define	REG_SERDES_STAT(pn) CRA(0x1,pn,0x11) /* SerDes status */

#define	REG_SERDES_COM_CNT(pn) CRA(0x1,pn,0x12) /* SerDes comma counter */

#define	REG_DENORM(pn) CRA(0x1,pn,0x15) /* Frame denormalization */

#define	REG_DBG(pn) CRA(0x1,pn,0x16) /* Device 1G debug */

#define	REG_TX_IFG(pn) CRA(0x1,pn,0x18) /* Tx IFG config */

#define	REG_HDX(pn) CRA(0x1,pn,0x19) /* Half-duplex config */

#define	REG_RX_XGMII_PROT_ERR CRA(0x4,0xa,0x3b) /* # protocol errors detected on XGMII interface */

#define	REG_STAT_STICKY10G CRA(0x4,0xa,StatSticky1G) /* 10GbE sticky bits */

#define	REG_RX_OK_BYTES(pn) CRA(0x4,pn,RxOkBytes)

#define	REG_RX_BAD_BYTES(pn) CRA(0x4,pn,RxBadBytes)

#define	REG_TX_OK_BYTES(pn) CRA(0x4,pn,TxOkBytes)

#define	REG_MIIM_STATUS CRA(0x3,0x0,0x00) /* MII-M Status */

#define	REG_MIIM_CMD CRA(0x3,0x0,0x01) /* MII-M Command */

#define	REG_MIIM_DATA CRA(0x3,0x0,0x02) /* MII-M Data */

#define	REG_MIIM_PRESCALE CRA(0x3,0x0,0x03) /* MII-M MDC Prescale */

#define	REG_ING_FFILT_UM_EN CRA(0x2, 0, 0xd)

#define	REG_ING_FFILT_BE_EN CRA(0x2, 0, 0x1d)

#define	REG_ING_FFILT_VAL0 CRA(0x2, 0, 0x2d)

#define	REG_ING_FFILT_VAL1 CRA(0x2, 0, 0x3d)

#define	REG_ING_FFILT_MASK0 CRA(0x2, 0, 0x4d)

#define	REG_ING_FFILT_MASK1 CRA(0x2, 0, 0x5d)

#define	REG_ING_FFILT_MASK2 CRA(0x2, 0, 0x6d)

#define	REG_ING_FFILT_ETYPE CRA(0x2, 0, 0x7d)

Enumerations
enum	{ RxInBytes = 0x00, RxSymbolCarrier = 0x01, RxPause = 0x02, RxUnsupOpcode = 0x03, RxOkBytes = 0x04, RxBadBytes = 0x05, RxUnicast = 0x06, RxMulticast = 0x07, RxBroadcast = 0x08, Crc = 0x09, RxAlignment = 0x0a, RxUndersize = 0x0b, RxFragments = 0x0c, RxInRangeLengthError = 0x0d, RxOutOfRangeError = 0x0e, RxOversize = 0x0f, RxJabbers = 0x10, RxSize64 = 0x11, RxSize65To127 = 0x12, RxSize128To255 = 0x13, RxSize256To511 = 0x14, RxSize512To1023 = 0x15, RxSize1024To1518 = 0x16, RxSize1519ToMax = 0x17, TxOutBytes = 0x18, TxPause = 0x19, TxOkBytes = 0x1a, TxUnicast = 0x1b, TxMulticast = 0x1c, TxBroadcast = 0x1d, TxMultipleColl = 0x1e, TxLateColl = 0x1f, TxXcoll = 0x20, TxDefer = 0x21, TxXdefer = 0x22, TxCsense = 0x23, TxSize64 = 0x24, TxSize65To127 = 0x25, TxSize128To255 = 0x26, TxSize256To511 = 0x27, TxSize512To1023 = 0x28, TxSize1024To1518 = 0x29, TxSize1519ToMax = 0x2a, TxSingleColl = 0x2b, TxBackoff2 = 0x2c, TxBackoff3 = 0x2d, TxBackoff4 = 0x2e, TxBackoff5 = 0x2f, TxBackoff6 = 0x30, TxBackoff7 = 0x31, TxBackoff8 = 0x32, TxBackoff9 = 0x33, TxBackoff10 = 0x34, TxBackoff11 = 0x35, TxBackoff12 = 0x36, TxBackoff13 = 0x37, TxBackoff14 = 0x38, TxBackoff15 = 0x39, TxUnderrun = 0x3a, RxIpgShrink = 0x3c, StatSticky1G = 0x3e, StatInit = 0x3f }

Macro Definition Documentation

#define BIST_COMMAND 0x01 /* BIST enable/disable */

Definition at line 54 of file vsc7326_reg.h.

#define BIST_ERR_ADR0 0x08 /* BIST error address lo 8b */

Definition at line 61 of file vsc7326_reg.h.

#define BIST_ERR_ADR1 0x09 /* BIST error address lomid 8b */

Definition at line 62 of file vsc7326_reg.h.

#define BIST_ERR_ADR2 0x0a /* BIST error address himid 8b */

Definition at line 63 of file vsc7326_reg.h.

#define BIST_ERR_ADR3 0x0b /* BIST error address hi 8b */

Definition at line 64 of file vsc7326_reg.h.

#define BIST_ERR_CNT_LSB 0x03 /* BIST error count lo 8b */

Definition at line 56 of file vsc7326_reg.h.

#define BIST_ERR_CNT_MSB 0x04 /* BIST error count hi 8b */

Definition at line 57 of file vsc7326_reg.h.

#define BIST_ERR_SEL_LSB 0x05 /* BIST error select lo 8b */

Definition at line 58 of file vsc7326_reg.h.

#define BIST_ERR_SEL_MSB 0x06 /* BIST error select hi 8b */

Definition at line 59 of file vsc7326_reg.h.

#define BIST_ERROR_STATE 0x07 /* BIST engine internal state */

Definition at line 60 of file vsc7326_reg.h.

#define BIST_PORT_SELECT 0x00 /* BIST port select */

Definition at line 53 of file vsc7326_reg.h.

#define BIST_STATUS 0x02 /* BIST operation status */

Definition at line 55 of file vsc7326_reg.h.

#define CRA	(	blk,
		sub,
		adr
	)	((((blk) & 0x7) << 13) \| (((sub) & 0xf) << 9) \| (((adr) & 0xff) << 1))

Definition at line 13 of file vsc7326_reg.h.

#define DEBUG_CNT ( ie ) CRA(0x2,ie&1,0x4f) /* Output debug counter */

Definition at line 104 of file vsc7326_reg.h.

#define DEBUG_OUT ( ie ) CRA(0x2,ie&1,0x3f) /* Output debug counter control */

Definition at line 103 of file vsc7326_reg.h.

#define REG_AGE_INC ( ie ) CRA(0x2,ie&1,0x2f) /* Aging increment */

Definition at line 102 of file vsc7326_reg.h.

#define REG_AGE_TIMER ( ie ) CRA(0x2,ie&1,0x1f) /* Aging timer */

Definition at line 101 of file vsc7326_reg.h.

#define REG_AGGR_SETUP CRA(0x7,0x1,0x00) /* Aggregator Setup */

Definition at line 35 of file vsc7326_reg.h.

#define REG_BLADE_ID CRA(0x7,0xf,0x01) /* Blade ID */

Definition at line 17 of file vsc7326_reg.h.

#define REG_BUCKE ( fn ) CRA(0x2,3,0x20+fn) /* Input Side Debug Counter */

Definition at line 79 of file vsc7326_reg.h.

#define REG_BUCKI ( fn ) CRA(0x2,2,0x20+fn) /* Input Side Debug Counter */

Definition at line 78 of file vsc7326_reg.h.

#define REG_CHIP_ID CRA(0x7,0xf,0x00) /* Chip ID */

Definition at line 16 of file vsc7326_reg.h.

#define REG_CONTROL ( ie ) CRA(0x2,ie&1,0x0f) /* FIFO control */

Definition at line 98 of file vsc7326_reg.h.

#define REG_CPU_TRANSFER_SEL CRA(0x7,0xf,0x20) /* CPU Transfer Select */

Definition at line 30 of file vsc7326_reg.h.

#define REG_CRC_CFG CRA(0x7,0x2,0x0b) /* CRC config */

Definition at line 23 of file vsc7326_reg.h.

#define REG_CRC_CNT CRA(0x7,0x2,0x0a) /* CRC error count */

Definition at line 22 of file vsc7326_reg.h.

#define REG_CT_THRHLD	(	ie,
		fn
	)	CRA(0x2,ie&1,0x50+fn) /* Cut Through Threshold */

Definition at line 75 of file vsc7326_reg.h.

#define REG_DBG ( pn ) CRA(0x1,pn,0x16) /* Device 1G debug */

Definition at line 190 of file vsc7326_reg.h.

#define REG_DEBUG_BUF_CNT	(	ie,
		fn
	)	CRA(0x2,ie&1,0x70+fn) /* Input Side Debug Counter */

Definition at line 77 of file vsc7326_reg.h.

#define REG_DENORM ( pn ) CRA(0x1,pn,0x15) /* Frame denormalization */

Definition at line 189 of file vsc7326_reg.h.

#define REG_DENORM_10G CRA(0x1,0xa,0x07) /* Denormalizer */

Definition at line 144 of file vsc7326_reg.h.

#define REG_DEV_SETUP ( pn ) CRA(0x1,pn,0x0b) /* MAC clock/reset setup */

Definition at line 181 of file vsc7326_reg.h.

#define REG_DROP_CNT ( pn ) CRA(0x1,pn,0x0c) /* Drop counter */

Definition at line 182 of file vsc7326_reg.h.

#define REG_EGR_CONTROL CRA(0x2,0x1,0x0f) /* Egress control (alias) */

Definition at line 100 of file vsc7326_reg.h.

#define REG_FIFO_DROP_CNT	(	ie,
		fn
	)	CRA(0x2,ie&1,0x60+fn) /* Drop & CRC Error Counter */

Definition at line 76 of file vsc7326_reg.h.

#define REG_GPIO_CTRL CRA(0x7,0xf,0x1d) /* GPIO Control */

Definition at line 27 of file vsc7326_reg.h.

#define REG_GPIO_IN CRA(0x7,0xf,0x1f) /* GPIO In */

Definition at line 29 of file vsc7326_reg.h.

#define REG_GPIO_OUT CRA(0x7,0xf,0x1e) /* GPIO Out */

Definition at line 28 of file vsc7326_reg.h.

#define REG_HDX ( pn ) CRA(0x1,pn,0x19) /* Half-duplex config */

Definition at line 192 of file vsc7326_reg.h.

#define REG_HEAD	(	ie,
		fn
	)	CRA(0x2,ie&1,0x30+fn) /* FIFO Read Pointer */

Definition at line 73 of file vsc7326_reg.h.

#define REG_HIGH_LOW_WM	(	ie,
		fn
	)	CRA(0x2,ie&1,0x40+fn) /* Flow Control Water Marks */

Definition at line 74 of file vsc7326_reg.h.

#define REG_IFACE_MODE CRA(0x7,0xf,0x07) /* Interface mode */

Definition at line 20 of file vsc7326_reg.h.

#define REG_ING_CONTROL CRA(0x2,0x0,0x0f) /* Ingress control (alias) */

Definition at line 99 of file vsc7326_reg.h.

#define REG_ING_FFILT_BE_EN CRA(0x2, 0, 0x1d)

Definition at line 286 of file vsc7326_reg.h.

#define REG_ING_FFILT_ETYPE CRA(0x2, 0, 0x7d)

Definition at line 292 of file vsc7326_reg.h.

#define REG_ING_FFILT_MASK0 CRA(0x2, 0, 0x4d)

Definition at line 289 of file vsc7326_reg.h.

#define REG_ING_FFILT_MASK1 CRA(0x2, 0, 0x5d)

Definition at line 290 of file vsc7326_reg.h.

#define REG_ING_FFILT_MASK2 CRA(0x2, 0, 0x6d)

Definition at line 291 of file vsc7326_reg.h.

#define REG_ING_FFILT_UM_EN CRA(0x2, 0, 0xd)

Definition at line 285 of file vsc7326_reg.h.

#define REG_ING_FFILT_VAL0 CRA(0x2, 0, 0x2d)

Definition at line 287 of file vsc7326_reg.h.

#define REG_ING_FFILT_VAL1 CRA(0x2, 0, 0x3d)

Definition at line 288 of file vsc7326_reg.h.

#define REG_LOCAL_DATA CRA(0x7,0xf,0xfe) /* Local CPU Data Register */

Definition at line 31 of file vsc7326_reg.h.

#define REG_LOCAL_STATUS CRA(0x7,0xf,0xff) /* Local CPU Status Register */

Definition at line 32 of file vsc7326_reg.h.

#define REG_MAC_HIGH_ADDR ( pn ) CRA(0x1,pn,0x03) /* Upper 24 bits of MAC addr */

Definition at line 167 of file vsc7326_reg.h.

#define REG_MAC_LOW_ADDR ( pn ) CRA(0x1,pn,0x04) /* Lower 24 bits of MAC addr */

Definition at line 168 of file vsc7326_reg.h.

#define REG_MAC_TX_RUNNING CRA(0x1,0xa,0x0d) /* MAC Tx state running debug */

Definition at line 149 of file vsc7326_reg.h.

#define REG_MAC_TX_STICKY CRA(0x1,0xa,0x0c) /* MAC Tx state sticky debug */

Definition at line 148 of file vsc7326_reg.h.

#define REG_MAX_LEN ( pn ) CRA(0x1,pn,0x02) /* Max length */

Definition at line 166 of file vsc7326_reg.h.

#define REG_MAX_RXHIGH CRA(0x1,0xa,0x0a) /* XGMII lane 0-3 debug */

Definition at line 146 of file vsc7326_reg.h.

#define REG_MAX_RXLOW CRA(0x1,0xa,0x0b) /* XGMII lane 4-7 debug */

Definition at line 147 of file vsc7326_reg.h.

#define REG_MEM_BIST CRA(0x7,0xf,0x04) /* mem */

Definition at line 19 of file vsc7326_reg.h.

#define REG_MIIM_CMD CRA(0x3,0x0,0x01) /* MII-M Command */

Definition at line 281 of file vsc7326_reg.h.

#define REG_MIIM_DATA CRA(0x3,0x0,0x02) /* MII-M Data */

Definition at line 282 of file vsc7326_reg.h.

#define REG_MIIM_PRESCALE CRA(0x3,0x0,0x03) /* MII-M MDC Prescale */

Definition at line 283 of file vsc7326_reg.h.

#define REG_MIIM_STATUS CRA(0x3,0x0,0x00) /* MII-M Status */

Definition at line 280 of file vsc7326_reg.h.

#define REG_MISC_10G CRA(0x1,0xa,0x00) /* Misc 10GbE setup */

Definition at line 140 of file vsc7326_reg.h.

#define REG_MODE_CFG ( pn ) CRA(0x1,pn,0x00) /* Mode configuration */

Definition at line 173 of file vsc7326_reg.h.

#define REG_MPLS_BIT0 CRA(0x7,0x1,0x08) /* MPLS bit0 position */

Definition at line 37 of file vsc7326_reg.h.

#define REG_MPLS_BIT1 CRA(0x7,0x1,0x09) /* MPLS bit1 position */

Definition at line 38 of file vsc7326_reg.h.

#define REG_MPLS_BIT2 CRA(0x7,0x1,0x0a) /* MPLS bit2 position */

Definition at line 39 of file vsc7326_reg.h.

#define REG_MPLS_BIT3 CRA(0x7,0x1,0x0b) /* MPLS bit3 position */

Definition at line 40 of file vsc7326_reg.h.

#define REG_MPLS_BITMASK CRA(0x7,0x1,0x0c) /* MPLS bit mask */

Definition at line 41 of file vsc7326_reg.h.

#define REG_MSCH CRA(0x7,0x2,0x06) /* CRC error count */

Definition at line 21 of file vsc7326_reg.h.

#define REG_NORMALIZER ( pn ) CRA(0x1,pn,0x05) /* Normalizer */

Definition at line 175 of file vsc7326_reg.h.

#define REG_NORMALIZER_10G CRA(0x1,0xa,0x05) /* 10G normalizer */

Definition at line 142 of file vsc7326_reg.h.

#define REG_PAUSE_10G CRA(0x1,0xa,0x01) /* Pause register */

Definition at line 141 of file vsc7326_reg.h.

#define REG_PAUSE_CFG ( pn ) CRA(0x1,pn,0x01) /* Pause configuration */

Definition at line 174 of file vsc7326_reg.h.

#define REG_PCS_CTRL ( pn ) CRA(0x1,pn,0x08) /* PCS control */

Definition at line 178 of file vsc7326_reg.h.

#define REG_PCS_STATUS_DBG ( pn ) CRA(0x1,pn,0x07) /* PCS status debug */

Definition at line 177 of file vsc7326_reg.h.

#define REG_PDERRCNT CRA(0x1,0xa,0x27) /* XAUI test register B */

Definition at line 162 of file vsc7326_reg.h.

#define REG_PLL_CLK_SPEED CRA(0x7,0xf,0x19) /* Clock Speed Selection */

Definition at line 25 of file vsc7326_reg.h.

#define REG_PMAP_TABLE CRA(0x7,0x1,0x01) /* Port map table */

Definition at line 36 of file vsc7326_reg.h.

#define REG_PORT_FAIL ( pn ) CRA(0x1,pn,0x0e) /* Preamble port position */

Definition at line 184 of file vsc7326_reg.h.

#define REG_PORT_POS ( pn ) CRA(0x1,pn,0x0d) /* Preamble port position */

Definition at line 183 of file vsc7326_reg.h.

#define REG_PRE_BIT0POS CRA(0x7,0x1,0x10) /* Preamble bit0 position */

Definition at line 42 of file vsc7326_reg.h.

#define REG_PRE_BIT1POS CRA(0x7,0x1,0x11) /* Preamble bit1 position */

Definition at line 43 of file vsc7326_reg.h.

#define REG_PRE_BIT2POS CRA(0x7,0x1,0x12) /* Preamble bit2 position */

Definition at line 44 of file vsc7326_reg.h.

#define REG_PRE_BIT3POS CRA(0x7,0x1,0x13) /* Preamble bit3 position */

Definition at line 45 of file vsc7326_reg.h.

#define REG_PRE_ERR_CNT CRA(0x7,0x1,0x14) /* Preamble parity error count */

Definition at line 46 of file vsc7326_reg.h.

#define REG_RAM_BIST_CMD CRA(0x7,0x1,0x00) /* RAM BIST Command Register */

Definition at line 51 of file vsc7326_reg.h.

#define REG_RAM_BIST_RESULT CRA(0x7,0x1,0x01) /* RAM BIST Read Status/Result */

Definition at line 52 of file vsc7326_reg.h.

#define REG_RX_BAD_BYTES ( pn ) CRA(0x4,pn,RxBadBytes)

Definition at line 271 of file vsc7326_reg.h.

#define REG_RX_OK_BYTES ( pn ) CRA(0x4,pn,RxOkBytes)

Definition at line 270 of file vsc7326_reg.h.

#define REG_RX_XGMII_PROT_ERR CRA(0x4,0xa,0x3b) /* # protocol errors detected on XGMII interface */

Definition at line 267 of file vsc7326_reg.h.

#define REG_SERDES_COM_CNT ( pn ) CRA(0x1,pn,0x12) /* SerDes comma counter */

Definition at line 188 of file vsc7326_reg.h.

#define REG_SERDES_CONF ( pn ) CRA(0x1,pn,0x0f) /* SerDes configuration */

Definition at line 185 of file vsc7326_reg.h.

#define REG_SERDES_STAT ( pn ) CRA(0x1,pn,0x11) /* SerDes status */

Definition at line 187 of file vsc7326_reg.h.

#define REG_SERDES_TEST ( pn ) CRA(0x1,pn,0x10) /* SerDes test */

Definition at line 186 of file vsc7326_reg.h.

#define REG_SI_TRANSFER_SEL CRA(0x7,0xf,0x18) /* SI Transfer Select */

Definition at line 24 of file vsc7326_reg.h.

#define REG_SPI4_DBG_CNT ( n ) CRA(0x5,0x0,0x10+n) /* Debug counters 0-9 */

Definition at line 113 of file vsc7326_reg.h.

#define REG_SPI4_DBG_GRANT CRA(0x5,0x0,0x33) /* Ingress cranted credit value */

Definition at line 126 of file vsc7326_reg.h.

#define REG_SPI4_DBG_INH CRA(0x5,0x0,0x31) /* Core egress & ingress inhibit */

Definition at line 124 of file vsc7326_reg.h.

#define REG_SPI4_DBG_SETUP CRA(0x5,0x0,0x1A) /* Debug counters setup */

Definition at line 114 of file vsc7326_reg.h.

#define REG_SPI4_DBG_STATUS CRA(0x5,0x0,0x32) /* Sampled ingress status */

Definition at line 125 of file vsc7326_reg.h.

#define REG_SPI4_DESKEW CRA(0x5,0x0,0x43) /* Ingress cranted credit value */

Definition at line 128 of file vsc7326_reg.h.

#define REG_SPI4_EGR_SETUP0 CRA(0x5,0x0,0x05) /* Egress Status Channel Setup */

Definition at line 112 of file vsc7326_reg.h.

#define REG_SPI4_ING_SETUP0 CRA(0x5,0x0,0x02) /* Ingress Status Channel Setup */

Definition at line 109 of file vsc7326_reg.h.

#define REG_SPI4_ING_SETUP1 CRA(0x5,0x0,0x03) /* Ingress Data Training Setup */

Definition at line 110 of file vsc7326_reg.h.

#define REG_SPI4_ING_SETUP2 CRA(0x5,0x0,0x04) /* Ingress Data Burst Size Setup */

Definition at line 111 of file vsc7326_reg.h.

#define REG_SPI4_MISC CRA(0x5,0x0,0x00) /* Misc Register */

Definition at line 107 of file vsc7326_reg.h.

#define REG_SPI4_STATUS CRA(0x5,0x0,0x01) /* CML Status */

Definition at line 108 of file vsc7326_reg.h.

#define REG_SPI4_STICKY CRA(0x5,0x0,0x30) /* Sticky bits register */

Definition at line 123 of file vsc7326_reg.h.

#define REG_SPI4_TEST CRA(0x5,0x0,0x20) /* Test Setup Register */

Definition at line 115 of file vsc7326_reg.h.

#define REG_SRAM_ADR ( ie ) CRA(0x2,ie&1,0x0e) /* FIFO SRAM address */

Definition at line 89 of file vsc7326_reg.h.

#define REG_SRAM_DATA_0 ( ie ) CRA(0x2,ie&1,0x3e) /* FIFO SRAM data lo 8b */

Definition at line 92 of file vsc7326_reg.h.

#define REG_SRAM_DATA_1 ( ie ) CRA(0x2,ie&1,0x4e) /* FIFO SRAM data lomid 8b */

Definition at line 93 of file vsc7326_reg.h.

#define REG_SRAM_DATA_2 ( ie ) CRA(0x2,ie&1,0x5e) /* FIFO SRAM data himid 8b */

Definition at line 94 of file vsc7326_reg.h.

#define REG_SRAM_DATA_3 ( ie ) CRA(0x2,ie&1,0x6e) /* FIFO SRAM data hi 8b */

Definition at line 95 of file vsc7326_reg.h.

#define REG_SRAM_DATA_BLK_TYPE ( ie ) CRA(0x2,ie&1,0x7e) /* FIFO SRAM tag */

Definition at line 96 of file vsc7326_reg.h.

#define REG_SRAM_RD_STRB ( ie ) CRA(0x2,ie&1,0x2e) /* FIFO SRAM read strobe */

Definition at line 91 of file vsc7326_reg.h.

#define REG_SRAM_WR_STRB ( ie ) CRA(0x2,ie&1,0x1e) /* FIFO SRAM write strobe */

Definition at line 90 of file vsc7326_reg.h.

#define REG_STAT_STICKY10G CRA(0x4,0xa,StatSticky1G) /* 10GbE sticky bits */

Definition at line 268 of file vsc7326_reg.h.

#define REG_STICK_BIT ( pn ) CRA(0x1,pn,0x0a) /* Sticky bits */

Definition at line 180 of file vsc7326_reg.h.

#define REG_STICKY_RX CRA(0x1,0xa,0x06) /* RX debug register */

Definition at line 143 of file vsc7326_reg.h.

#define REG_STICKY_TX CRA(0x1,0xa,0x08) /* TX sticky bits */

Definition at line 145 of file vsc7326_reg.h.

#define REG_SW_RESET CRA(0x7,0xf,0x02) /* Global Soft Reset */

Definition at line 18 of file vsc7326_reg.h.

#define REG_SYS_CLK_SELECT CRA(0x7,0xf,0x1c) /* System Clock Select */

Definition at line 26 of file vsc7326_reg.h.

#define REG_TAIL	(	ie,
		fn
	)	CRA(0x2,ie&1,0x20+fn) /* FIFO Write Pointer */

Definition at line 72 of file vsc7326_reg.h.

#define REG_TBI_CONFIG ( pn ) CRA(0x1,pn,0x09) /* TBI configuration */

Definition at line 179 of file vsc7326_reg.h.

#define REG_TBI_STATUS ( pn ) CRA(0x1,pn,0x06) /* TBI status */

Definition at line 176 of file vsc7326_reg.h.

#define REG_TEST	(	ie,
		fn
	)	CRA(0x2,ie&1,0x00+fn) /* Mode & Test Register */

Definition at line 70 of file vsc7326_reg.h.

#define REG_TOP_BOTTOM	(	ie,
		fn
	)	CRA(0x2,ie&1,0x10+fn) /* FIFO Buffer Top & Bottom */

Definition at line 71 of file vsc7326_reg.h.

#define REG_TPCHK_UP0 CRA(0x5,0x0,0x23) /* Test Pattern checker user pattern 0 */

Definition at line 118 of file vsc7326_reg.h.

#define REG_TPCHK_UP1 CRA(0x5,0x0,0x24) /* Test Pattern checker user pattern 1 */

Definition at line 119 of file vsc7326_reg.h.

#define REG_TPERR_CNT CRA(0x5,0x0,0x27) /* Pattern checker error counter */

Definition at line 122 of file vsc7326_reg.h.

#define REG_TPGEN_UP0 CRA(0x5,0x0,0x21) /* Test Pattern generator user pattern 0 */

Definition at line 116 of file vsc7326_reg.h.

#define REG_TPGEN_UP1 CRA(0x5,0x0,0x22) /* Test Pattern generator user pattern 1 */

Definition at line 117 of file vsc7326_reg.h.

#define REG_TPSAM_P0 CRA(0x5,0x0,0x25) /* Sampled pattern 0 */

Definition at line 120 of file vsc7326_reg.h.

#define REG_TPSAM_P1 CRA(0x5,0x0,0x26) /* Sampled pattern 1 */

Definition at line 121 of file vsc7326_reg.h.

#define REG_TRAFFIC_SHAPER_BUCKET	(	ie,
		bn
	)	CRA(0x2,ie&1,0x0a + (bn>7) \| ((bn&7)<<4))

Definition at line 86 of file vsc7326_reg.h.

#define REG_TRAFFIC_SHAPER_CONTROL ( ie ) CRA(0x2,ie&1,0x3b)

Definition at line 87 of file vsc7326_reg.h.

#define REG_TX_ABORT_AGE CRA(0x1,0xa,0x14) /* Aged Tx frames discarded */

Definition at line 150 of file vsc7326_reg.h.

#define REG_TX_ABORT_SHORT CRA(0x1,0xa,0x15) /* Short Tx frames discarded */

Definition at line 151 of file vsc7326_reg.h.

#define REG_TX_ABORT_TAXI CRA(0x1,0xa,0x16) /* Taxi error frames discarded */

Definition at line 152 of file vsc7326_reg.h.

#define REG_TX_ABORT_UNDERRUN CRA(0x1,0xa,0x17) /* Tx Underrun abort counter */

Definition at line 153 of file vsc7326_reg.h.

#define REG_TX_DENORM_DISCARD CRA(0x1,0xa,0x18) /* Tx denormalizer discards */

Definition at line 154 of file vsc7326_reg.h.

#define REG_TX_IFG ( pn ) CRA(0x1,pn,0x18) /* Tx IFG config */

Definition at line 191 of file vsc7326_reg.h.

#define REG_TX_OK_BYTES ( pn ) CRA(0x4,pn,TxOkBytes)

Definition at line 272 of file vsc7326_reg.h.

#define REG_XAUI_CODE_GRP_CNT CRA(0x1,0xa,0x25) /* XAUI code group error count */

Definition at line 160 of file vsc7326_reg.h.

#define REG_XAUI_CONF_A CRA(0x1,0xa,0x23) /* XAUI configuration A */

Definition at line 158 of file vsc7326_reg.h.

#define REG_XAUI_CONF_B CRA(0x1,0xa,0x24) /* XAUI configuration B */

Definition at line 159 of file vsc7326_reg.h.

#define REG_XAUI_CONF_TEST_A CRA(0x1,0xa,0x26) /* XAUI test register A */

Definition at line 161 of file vsc7326_reg.h.

#define REG_XAUI_STAT_A CRA(0x1,0xa,0x20) /* XAUI status A */

Definition at line 155 of file vsc7326_reg.h.

#define REG_XAUI_STAT_B CRA(0x1,0xa,0x21) /* XAUI status B */

Definition at line 156 of file vsc7326_reg.h.

#define REG_XAUI_STAT_C CRA(0x1,0xa,0x22) /* XAUI status C */

Definition at line 157 of file vsc7326_reg.h.

Enumeration Type Documentation

anonymous enum

Enumerator:

RxInBytes
RxSymbolCarrier
RxPause
RxUnsupOpcode
RxOkBytes
RxBadBytes
RxUnicast
RxMulticast
RxBroadcast
Crc
RxAlignment
RxUndersize
RxFragments
RxInRangeLengthError
RxOutOfRangeError
RxOversize
RxJabbers
RxSize64
RxSize65To127
RxSize128To255
RxSize256To511
RxSize512To1023
RxSize1024To1518
RxSize1519ToMax
TxOutBytes
TxPause
TxOkBytes
TxUnicast
TxMulticast
TxBroadcast
TxMultipleColl
TxLateColl
TxXcoll
TxDefer
TxXdefer
TxCsense
TxSize64
TxSize65To127
TxSize128To255
TxSize256To511
TxSize512To1023
TxSize1024To1518
TxSize1519ToMax
TxSingleColl
TxBackoff2
TxBackoff3
TxBackoff4
TxBackoff5
TxBackoff6
TxBackoff7
TxBackoff8
TxBackoff9
TxBackoff10
TxBackoff11
TxBackoff12
TxBackoff13
TxBackoff14
TxBackoff15
TxUnderrun
RxIpgShrink
StatSticky1G
StatInit

Definition at line 199 of file vsc7326_reg.h.

Macros

Enumerations

Macro Definition Documentation

Enumeration Type Documentation