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| #define | REG_DO_FMT 0x0000 |
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| #define | REG_DOFF_CTL 0x0004 |
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| #define | REG_DOFF_ST 0x0008 |
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| #define | REG_DI_FMT 0x000C |
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| #define | REG_DIFF_CTL 0x0010 |
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| #define | REG_DIFF_ST 0x0014 |
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| #define | REG_CKG1 0x0018 |
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| #define | REG_CKG2 0x001C |
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| #define | REG_DIDT 0x0020 |
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| #define | REG_DODT 0x0024 |
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| #define | REG_MUTE_ST 0x0028 |
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| #define | REG_OUT_DMAC 0x002C |
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| #define | REG_OUT_SEL 0x0030 |
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| #define | REG_IN_DMAC 0x0038 |
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| #define | MST_CLK_RST 0x0210 |
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| #define | MST_SOFT_RST 0x0214 |
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| #define | MST_FIFO_SZ 0x0218 |
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| #define | A_MST_CTLR 0x0180 |
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| #define | B_MST_CTLR 0x01A0 |
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| #define | CPU_INT_ST 0x01F4 |
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| #define | CPU_IEMSK 0x01F8 |
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| #define | CPU_IMSK 0x01FC |
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| #define | INT_ST 0x0200 |
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| #define | IEMSK 0x0204 |
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| #define | IMSK 0x0208 |
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| #define | CR_BWS_MASK (0x3 << 20) /* FSI2 */ |
| |
| #define | CR_BWS_24 (0x0 << 20) /* FSI2 */ |
| |
| #define | CR_BWS_16 (0x1 << 20) /* FSI2 */ |
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| #define | CR_BWS_20 (0x2 << 20) /* FSI2 */ |
| |
| #define | CR_DTMD_PCM (0x0 << 8) /* FSI2 */ |
| |
| #define | CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */ |
| |
| #define | CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */ |
| |
| #define | CR_MONO (0x0 << 4) |
| |
| #define | CR_MONO_D (0x1 << 4) |
| |
| #define | CR_PCM (0x2 << 4) |
| |
| #define | CR_I2S (0x3 << 4) |
| |
| #define | CR_TDM (0x4 << 4) |
| |
| #define | CR_TDM_D (0x5 << 4) |
| |
| #define | VDMD_MASK (0x3 << 4) |
| |
| #define | VDMD_FRONT (0x0 << 4) /* Package in front */ |
| |
| #define | VDMD_BACK (0x1 << 4) /* Package in back */ |
| |
| #define | VDMD_STREAM (0x2 << 4) /* Stream mode(16bit * 2) */ |
| |
| #define | DMA_ON (0x1 << 0) |
| |
| #define | IRQ_HALF 0x00100000 |
| |
| #define | FIFO_CLR 0x00000001 |
| |
| #define | ERR_OVER 0x00000010 |
| |
| #define | ERR_UNDER 0x00000001 |
| |
| #define | ST_ERR (ERR_OVER | ERR_UNDER) |
| |
| #define | ACKMD_MASK 0x00007000 |
| |
| #define | BPFMD_MASK 0x00000700 |
| |
| #define | DIMD (1 << 4) |
| |
| #define | DOMD (1 << 0) |
| |
| #define | BP (1 << 4) /* Fix the signal of Biphase output */ |
| |
| #define | SE (1 << 0) /* Fix the master clock */ |
| |
| #define | CRB (1 << 4) |
| |
| #define | CRA (1 << 0) |
| |
| #define | BI_SHIFT 12 |
| |
| #define | BO_SHIFT 8 |
| |
| #define | AI_SHIFT 4 |
| |
| #define | AO_SHIFT 0 |
| |
| #define | AB_IO(param, shift) (param << shift) |
| |
| #define | PBSR (1 << 12) /* Port B Software Reset */ |
| |
| #define | PASR (1 << 8) /* Port A Software Reset */ |
| |
| #define | IR (1 << 4) /* Interrupt Reset */ |
| |
| #define | FSISR (1 << 0) /* Software Reset */ |
| |
| #define | DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */ |
| |
| #define | FIFO_SZ_MASK 0x7 |
| |
| #define | FSI_RATES SNDRV_PCM_RATE_8000_96000 |
| |
| #define | FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) |
| |
| #define | SHIFT_16DATA 0 |
| |
| #define | SHIFT_24DATA 4 |
| |
| #define | PACKAGE_24BITBUS_BACK 0 |
| |
| #define | PACKAGE_24BITBUS_FRONT 1 |
| |
| #define | PACKAGE_16BITBUS_STREAM 2 |
| |
| #define | BUSOP_SET(s, a) ((a) << SHIFT_ ## s ## DATA) |
| |
| #define | BUSOP_GET(s, a) (((a) >> SHIFT_ ## s ## DATA) & 0xF) |
| |
| #define | fsi_stream_handler_call(io, func, args...) |
| |
| #define | fsi_reg_write(p, r, d) __fsi_reg_write((p->base + REG_##r), d) |
| |
| #define | fsi_reg_read(p, r) __fsi_reg_read((p->base + REG_##r)) |
| |
| #define | fsi_reg_mask_set(p, r, m, d) __fsi_reg_mask_set((p->base + REG_##r), m, d) |
| |
| #define | fsi_master_read(p, r) _fsi_master_read(p, MST_##r) |
| |
| #define | fsi_core_read(p, r) _fsi_master_read(p, p->core->r) |
| |
| #define | fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d) |
| |
| #define | fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d) |
| |
| #define | fsi_stream_start(fsi, io) fsi_stream_handler_call(io, start_stop, fsi, io, 1) |
| |
| #define | fsi_stream_stop(fsi, io) fsi_stream_handler_call(io, start_stop, fsi, io, 0) |
| |
| #define | PREALLOC_BUFFER (32 * 1024) |
| |
| #define | PREALLOC_BUFFER_MAX (32 * 1024) |
| |
1.8.2