1.7.6.1Copyright © 2003-2014 University of Illinois at Urbana-Champaign. All Rights Reserved.
LLVM API Documentation
00001 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -------*- C++ -*-===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file is distributed under the University of Illinois Open Source 00006 // License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // 00011 //===----------------------------------------------------------------------===// 00012 00013 #include "AArch64Disassembler.h" 00014 #include "AArch64ExternalSymbolizer.h" 00015 #include "AArch64Subtarget.h" 00016 #include "MCTargetDesc/AArch64AddressingModes.h" 00017 #include "Utils/AArch64BaseInfo.h" 00018 #include "llvm/MC/MCFixedLenDisassembler.h" 00019 #include "llvm/MC/MCInst.h" 00020 #include "llvm/Support/Debug.h" 00021 #include "llvm/Support/ErrorHandling.h" 00022 #include "llvm/Support/MemoryObject.h" 00023 #include "llvm/Support/TargetRegistry.h" 00024 00025 using namespace llvm; 00026 00027 #define DEBUG_TYPE "aarch64-disassembler" 00028 00029 // Pull DecodeStatus and its enum values into the global namespace. 00030 typedef llvm::MCDisassembler::DecodeStatus DecodeStatus; 00031 00032 // Forward declare these because the autogenerated code will reference them. 00033 // Definitions are further down. 00034 static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst, 00035 unsigned RegNo, uint64_t Address, 00036 const void *Decoder); 00037 static DecodeStatus DecodeFPR128_loRegisterClass(llvm::MCInst &Inst, 00038 unsigned RegNo, 00039 uint64_t Address, 00040 const void *Decoder); 00041 static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 00042 uint64_t Address, 00043 const void *Decoder); 00044 static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 00045 uint64_t Address, 00046 const void *Decoder); 00047 static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 00048 uint64_t Address, 00049 const void *Decoder); 00050 static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 00051 uint64_t Address, 00052 const void *Decoder); 00053 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 00054 uint64_t Address, 00055 const void *Decoder); 00056 static DecodeStatus DecodeGPR64spRegisterClass(llvm::MCInst &Inst, 00057 unsigned RegNo, uint64_t Address, 00058 const void *Decoder); 00059 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 00060 uint64_t Address, 00061 const void *Decoder); 00062 static DecodeStatus DecodeGPR32spRegisterClass(llvm::MCInst &Inst, 00063 unsigned RegNo, uint64_t Address, 00064 const void *Decoder); 00065 static DecodeStatus DecodeQQRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 00066 uint64_t Address, 00067 const void *Decoder); 00068 static DecodeStatus DecodeQQQRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 00069 uint64_t Address, 00070 const void *Decoder); 00071 static DecodeStatus DecodeQQQQRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 00072 uint64_t Address, 00073 const void *Decoder); 00074 static DecodeStatus DecodeDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 00075 uint64_t Address, 00076 const void *Decoder); 00077 static DecodeStatus DecodeDDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 00078 uint64_t Address, 00079 const void *Decoder); 00080 static DecodeStatus DecodeDDDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 00081 uint64_t Address, 00082 const void *Decoder); 00083 00084 static DecodeStatus DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm, 00085 uint64_t Address, 00086 const void *Decoder); 00087 static DecodeStatus DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm, 00088 uint64_t Address, 00089 const void *Decoder); 00090 static DecodeStatus DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm, 00091 uint64_t Address, const void *Decoder); 00092 static DecodeStatus DecodeMemExtend(llvm::MCInst &Inst, unsigned Imm, 00093 uint64_t Address, const void *Decoder); 00094 static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm, 00095 uint64_t Address, const void *Decoder); 00096 static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm, 00097 uint64_t Address, const void *Decoder); 00098 static DecodeStatus DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst, 00099 uint32_t insn, 00100 uint64_t Address, 00101 const void *Decoder); 00102 static DecodeStatus DecodeMoveImmInstruction(llvm::MCInst &Inst, uint32_t insn, 00103 uint64_t Address, 00104 const void *Decoder); 00105 static DecodeStatus DecodeUnsignedLdStInstruction(llvm::MCInst &Inst, 00106 uint32_t insn, 00107 uint64_t Address, 00108 const void *Decoder); 00109 static DecodeStatus DecodeSignedLdStInstruction(llvm::MCInst &Inst, 00110 uint32_t insn, uint64_t Address, 00111 const void *Decoder); 00112 static DecodeStatus DecodeExclusiveLdStInstruction(llvm::MCInst &Inst, 00113 uint32_t insn, 00114 uint64_t Address, 00115 const void *Decoder); 00116 static DecodeStatus DecodePairLdStInstruction(llvm::MCInst &Inst, uint32_t insn, 00117 uint64_t Address, 00118 const void *Decoder); 00119 static DecodeStatus DecodeAddSubERegInstruction(llvm::MCInst &Inst, 00120 uint32_t insn, uint64_t Address, 00121 const void *Decoder); 00122 static DecodeStatus DecodeLogicalImmInstruction(llvm::MCInst &Inst, 00123 uint32_t insn, uint64_t Address, 00124 const void *Decoder); 00125 static DecodeStatus DecodeModImmInstruction(llvm::MCInst &Inst, uint32_t insn, 00126 uint64_t Address, 00127 const void *Decoder); 00128 static DecodeStatus DecodeModImmTiedInstruction(llvm::MCInst &Inst, 00129 uint32_t insn, uint64_t Address, 00130 const void *Decoder); 00131 static DecodeStatus DecodeAdrInstruction(llvm::MCInst &Inst, uint32_t insn, 00132 uint64_t Address, const void *Decoder); 00133 static DecodeStatus DecodeBaseAddSubImm(llvm::MCInst &Inst, uint32_t insn, 00134 uint64_t Address, const void *Decoder); 00135 static DecodeStatus DecodeUnconditionalBranch(llvm::MCInst &Inst, uint32_t insn, 00136 uint64_t Address, 00137 const void *Decoder); 00138 static DecodeStatus DecodeSystemPStateInstruction(llvm::MCInst &Inst, 00139 uint32_t insn, 00140 uint64_t Address, 00141 const void *Decoder); 00142 static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn, 00143 uint64_t Address, const void *Decoder); 00144 00145 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn, 00146 uint64_t Address, 00147 const void *Decoder); 00148 static DecodeStatus DecodeVecShiftR64Imm(llvm::MCInst &Inst, unsigned Imm, 00149 uint64_t Addr, const void *Decoder); 00150 static DecodeStatus DecodeVecShiftR64ImmNarrow(llvm::MCInst &Inst, unsigned Imm, 00151 uint64_t Addr, 00152 const void *Decoder); 00153 static DecodeStatus DecodeVecShiftR32Imm(llvm::MCInst &Inst, unsigned Imm, 00154 uint64_t Addr, const void *Decoder); 00155 static DecodeStatus DecodeVecShiftR32ImmNarrow(llvm::MCInst &Inst, unsigned Imm, 00156 uint64_t Addr, 00157 const void *Decoder); 00158 static DecodeStatus DecodeVecShiftR16Imm(llvm::MCInst &Inst, unsigned Imm, 00159 uint64_t Addr, const void *Decoder); 00160 static DecodeStatus DecodeVecShiftR16ImmNarrow(llvm::MCInst &Inst, unsigned Imm, 00161 uint64_t Addr, 00162 const void *Decoder); 00163 static DecodeStatus DecodeVecShiftR8Imm(llvm::MCInst &Inst, unsigned Imm, 00164 uint64_t Addr, const void *Decoder); 00165 static DecodeStatus DecodeVecShiftL64Imm(llvm::MCInst &Inst, unsigned Imm, 00166 uint64_t Addr, const void *Decoder); 00167 static DecodeStatus DecodeVecShiftL32Imm(llvm::MCInst &Inst, unsigned Imm, 00168 uint64_t Addr, const void *Decoder); 00169 static DecodeStatus DecodeVecShiftL16Imm(llvm::MCInst &Inst, unsigned Imm, 00170 uint64_t Addr, const void *Decoder); 00171 static DecodeStatus DecodeVecShiftL8Imm(llvm::MCInst &Inst, unsigned Imm, 00172 uint64_t Addr, const void *Decoder); 00173 00174 static bool Check(DecodeStatus &Out, DecodeStatus In) { 00175 switch (In) { 00176 case MCDisassembler::Success: 00177 // Out stays the same. 00178 return true; 00179 case MCDisassembler::SoftFail: 00180 Out = In; 00181 return true; 00182 case MCDisassembler::Fail: 00183 Out = In; 00184 return false; 00185 } 00186 llvm_unreachable("Invalid DecodeStatus!"); 00187 } 00188 00189 #include "AArch64GenDisassemblerTables.inc" 00190 #include "AArch64GenInstrInfo.inc" 00191 00192 #define Success llvm::MCDisassembler::Success 00193 #define Fail llvm::MCDisassembler::Fail 00194 #define SoftFail llvm::MCDisassembler::SoftFail 00195 00196 static MCDisassembler *createAArch64Disassembler(const Target &T, 00197 const MCSubtargetInfo &STI, 00198 MCContext &Ctx) { 00199 return new AArch64Disassembler(STI, Ctx); 00200 } 00201 00202 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, 00203 const MemoryObject &Region, 00204 uint64_t Address, 00205 raw_ostream &os, 00206 raw_ostream &cs) const { 00207 CommentStream = &cs; 00208 00209 uint8_t bytes[4]; 00210 00211 Size = 0; 00212 // We want to read exactly 4 bytes of data. 00213 if (Region.readBytes(Address, 4, (uint8_t *)bytes) == -1) 00214 return Fail; 00215 Size = 4; 00216 00217 // Encoded as a small-endian 32-bit word in the stream. 00218 uint32_t insn = 00219 (bytes[3] << 24) | (bytes[2] << 16) | (bytes[1] << 8) | (bytes[0] << 0); 00220 00221 // Calling the auto-generated decoder function. 00222 return decodeInstruction(DecoderTable32, MI, insn, Address, this, STI); 00223 } 00224 00225 static MCSymbolizer * 00226 createAArch64ExternalSymbolizer(StringRef TT, LLVMOpInfoCallback GetOpInfo, 00227 LLVMSymbolLookupCallback SymbolLookUp, 00228 void *DisInfo, MCContext *Ctx, 00229 MCRelocationInfo *RelInfo) { 00230 return new llvm::AArch64ExternalSymbolizer( 00231 *Ctx, 00232 std::unique_ptr<MCRelocationInfo>(RelInfo), 00233 GetOpInfo, SymbolLookUp, DisInfo); 00234 } 00235 00236 extern "C" void LLVMInitializeAArch64Disassembler() { 00237 TargetRegistry::RegisterMCDisassembler(TheAArch64leTarget, 00238 createAArch64Disassembler); 00239 TargetRegistry::RegisterMCDisassembler(TheAArch64beTarget, 00240 createAArch64Disassembler); 00241 TargetRegistry::RegisterMCSymbolizer(TheAArch64leTarget, 00242 createAArch64ExternalSymbolizer); 00243 TargetRegistry::RegisterMCSymbolizer(TheAArch64beTarget, 00244 createAArch64ExternalSymbolizer); 00245 00246 TargetRegistry::RegisterMCDisassembler(TheARM64Target, 00247 createAArch64Disassembler); 00248 TargetRegistry::RegisterMCSymbolizer(TheARM64Target, 00249 createAArch64ExternalSymbolizer); 00250 } 00251 00252 static const unsigned FPR128DecoderTable[] = { 00253 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 00254 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 00255 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 00256 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 00257 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 00258 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 00259 AArch64::Q30, AArch64::Q31 00260 }; 00261 00262 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, 00263 uint64_t Addr, 00264 const void *Decoder) { 00265 if (RegNo > 31) 00266 return Fail; 00267 00268 unsigned Register = FPR128DecoderTable[RegNo]; 00269 Inst.addOperand(MCOperand::CreateReg(Register)); 00270 return Success; 00271 } 00272 00273 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, 00274 uint64_t Addr, 00275 const void *Decoder) { 00276 if (RegNo > 15) 00277 return Fail; 00278 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); 00279 } 00280 00281 static const unsigned FPR64DecoderTable[] = { 00282 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, 00283 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, 00284 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, 00285 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, 00286 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, 00287 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, 00288 AArch64::D30, AArch64::D31 00289 }; 00290 00291 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 00292 uint64_t Addr, 00293 const void *Decoder) { 00294 if (RegNo > 31) 00295 return Fail; 00296 00297 unsigned Register = FPR64DecoderTable[RegNo]; 00298 Inst.addOperand(MCOperand::CreateReg(Register)); 00299 return Success; 00300 } 00301 00302 static const unsigned FPR32DecoderTable[] = { 00303 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, 00304 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, 00305 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, 00306 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, 00307 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, 00308 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, 00309 AArch64::S30, AArch64::S31 00310 }; 00311 00312 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 00313 uint64_t Addr, 00314 const void *Decoder) { 00315 if (RegNo > 31) 00316 return Fail; 00317 00318 unsigned Register = FPR32DecoderTable[RegNo]; 00319 Inst.addOperand(MCOperand::CreateReg(Register)); 00320 return Success; 00321 } 00322 00323 static const unsigned FPR16DecoderTable[] = { 00324 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, 00325 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, 00326 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, 00327 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, 00328 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, 00329 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, 00330 AArch64::H30, AArch64::H31 00331 }; 00332 00333 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 00334 uint64_t Addr, 00335 const void *Decoder) { 00336 if (RegNo > 31) 00337 return Fail; 00338 00339 unsigned Register = FPR16DecoderTable[RegNo]; 00340 Inst.addOperand(MCOperand::CreateReg(Register)); 00341 return Success; 00342 } 00343 00344 static const unsigned FPR8DecoderTable[] = { 00345 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, 00346 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, 00347 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, 00348 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, 00349 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, 00350 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, 00351 AArch64::B30, AArch64::B31 00352 }; 00353 00354 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 00355 uint64_t Addr, 00356 const void *Decoder) { 00357 if (RegNo > 31) 00358 return Fail; 00359 00360 unsigned Register = FPR8DecoderTable[RegNo]; 00361 Inst.addOperand(MCOperand::CreateReg(Register)); 00362 return Success; 00363 } 00364 00365 static const unsigned GPR64DecoderTable[] = { 00366 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, 00367 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, 00368 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, 00369 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, 00370 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, 00371 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, 00372 AArch64::LR, AArch64::XZR 00373 }; 00374 00375 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 00376 uint64_t Addr, 00377 const void *Decoder) { 00378 if (RegNo > 31) 00379 return Fail; 00380 00381 unsigned Register = GPR64DecoderTable[RegNo]; 00382 Inst.addOperand(MCOperand::CreateReg(Register)); 00383 return Success; 00384 } 00385 00386 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, 00387 uint64_t Addr, 00388 const void *Decoder) { 00389 if (RegNo > 31) 00390 return Fail; 00391 unsigned Register = GPR64DecoderTable[RegNo]; 00392 if (Register == AArch64::XZR) 00393 Register = AArch64::SP; 00394 Inst.addOperand(MCOperand::CreateReg(Register)); 00395 return Success; 00396 } 00397 00398 static const unsigned GPR32DecoderTable[] = { 00399 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, 00400 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, 00401 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, 00402 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, 00403 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, 00404 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, 00405 AArch64::W30, AArch64::WZR 00406 }; 00407 00408 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 00409 uint64_t Addr, 00410 const void *Decoder) { 00411 if (RegNo > 31) 00412 return Fail; 00413 00414 unsigned Register = GPR32DecoderTable[RegNo]; 00415 Inst.addOperand(MCOperand::CreateReg(Register)); 00416 return Success; 00417 } 00418 00419 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, 00420 uint64_t Addr, 00421 const void *Decoder) { 00422 if (RegNo > 31) 00423 return Fail; 00424 00425 unsigned Register = GPR32DecoderTable[RegNo]; 00426 if (Register == AArch64::WZR) 00427 Register = AArch64::WSP; 00428 Inst.addOperand(MCOperand::CreateReg(Register)); 00429 return Success; 00430 } 00431 00432 static const unsigned VectorDecoderTable[] = { 00433 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 00434 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 00435 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 00436 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 00437 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 00438 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 00439 AArch64::Q30, AArch64::Q31 00440 }; 00441 00442 static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo, 00443 uint64_t Addr, 00444 const void *Decoder) { 00445 if (RegNo > 31) 00446 return Fail; 00447 00448 unsigned Register = VectorDecoderTable[RegNo]; 00449 Inst.addOperand(MCOperand::CreateReg(Register)); 00450 return Success; 00451 } 00452 00453 static const unsigned QQDecoderTable[] = { 00454 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, 00455 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, 00456 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, 00457 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, 00458 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20, 00459 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24, 00460 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28, 00461 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0 00462 }; 00463 00464 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 00465 uint64_t Addr, const void *Decoder) { 00466 if (RegNo > 31) 00467 return Fail; 00468 unsigned Register = QQDecoderTable[RegNo]; 00469 Inst.addOperand(MCOperand::CreateReg(Register)); 00470 return Success; 00471 } 00472 00473 static const unsigned QQQDecoderTable[] = { 00474 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, 00475 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, 00476 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, 00477 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, 00478 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, 00479 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19, 00480 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22, 00481 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25, 00482 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28, 00483 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31, 00484 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1 00485 }; 00486 00487 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 00488 uint64_t Addr, const void *Decoder) { 00489 if (RegNo > 31) 00490 return Fail; 00491 unsigned Register = QQQDecoderTable[RegNo]; 00492 Inst.addOperand(MCOperand::CreateReg(Register)); 00493 return Success; 00494 } 00495 00496 static const unsigned QQQQDecoderTable[] = { 00497 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, 00498 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, 00499 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, 00500 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, 00501 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, 00502 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20, 00503 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23, 00504 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26, 00505 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29, 00506 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0, 00507 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2 00508 }; 00509 00510 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 00511 uint64_t Addr, 00512 const void *Decoder) { 00513 if (RegNo > 31) 00514 return Fail; 00515 unsigned Register = QQQQDecoderTable[RegNo]; 00516 Inst.addOperand(MCOperand::CreateReg(Register)); 00517 return Success; 00518 } 00519 00520 static const unsigned DDDecoderTable[] = { 00521 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, 00522 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, 00523 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, 00524 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16, 00525 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20, 00526 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24, 00527 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28, 00528 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0 00529 }; 00530 00531 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 00532 uint64_t Addr, const void *Decoder) { 00533 if (RegNo > 31) 00534 return Fail; 00535 unsigned Register = DDDecoderTable[RegNo]; 00536 Inst.addOperand(MCOperand::CreateReg(Register)); 00537 return Success; 00538 } 00539 00540 static const unsigned DDDDecoderTable[] = { 00541 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, 00542 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, 00543 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, 00544 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, 00545 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, 00546 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19, 00547 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22, 00548 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25, 00549 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28, 00550 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31, 00551 AArch64::D30_D31_D0, AArch64::D31_D0_D1 00552 }; 00553 00554 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 00555 uint64_t Addr, const void *Decoder) { 00556 if (RegNo > 31) 00557 return Fail; 00558 unsigned Register = DDDDecoderTable[RegNo]; 00559 Inst.addOperand(MCOperand::CreateReg(Register)); 00560 return Success; 00561 } 00562 00563 static const unsigned DDDDDecoderTable[] = { 00564 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, 00565 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, 00566 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, 00567 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, 00568 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, 00569 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20, 00570 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23, 00571 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26, 00572 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29, 00573 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0, 00574 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2 00575 }; 00576 00577 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 00578 uint64_t Addr, 00579 const void *Decoder) { 00580 if (RegNo > 31) 00581 return Fail; 00582 unsigned Register = DDDDDecoderTable[RegNo]; 00583 Inst.addOperand(MCOperand::CreateReg(Register)); 00584 return Success; 00585 } 00586 00587 static DecodeStatus DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm, 00588 uint64_t Addr, 00589 const void *Decoder) { 00590 // scale{5} is asserted as 1 in tblgen. 00591 Imm |= 0x20; 00592 Inst.addOperand(MCOperand::CreateImm(64 - Imm)); 00593 return Success; 00594 } 00595 00596 static DecodeStatus DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm, 00597 uint64_t Addr, 00598 const void *Decoder) { 00599 Inst.addOperand(MCOperand::CreateImm(64 - Imm)); 00600 return Success; 00601 } 00602 00603 static DecodeStatus DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm, 00604 uint64_t Addr, const void *Decoder) { 00605 int64_t ImmVal = Imm; 00606 const AArch64Disassembler *Dis = 00607 static_cast<const AArch64Disassembler *>(Decoder); 00608 00609 // Sign-extend 19-bit immediate. 00610 if (ImmVal & (1 << (19 - 1))) 00611 ImmVal |= ~((1LL << 19) - 1); 00612 00613 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr, 00614 Inst.getOpcode() != AArch64::LDRXl, 0, 4)) 00615 Inst.addOperand(MCOperand::CreateImm(ImmVal)); 00616 return Success; 00617 } 00618 00619 static DecodeStatus DecodeMemExtend(llvm::MCInst &Inst, unsigned Imm, 00620 uint64_t Address, const void *Decoder) { 00621 Inst.addOperand(MCOperand::CreateImm((Imm >> 1) & 1)); 00622 Inst.addOperand(MCOperand::CreateImm(Imm & 1)); 00623 return Success; 00624 } 00625 00626 static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm, 00627 uint64_t Address, 00628 const void *Decoder) { 00629 const AArch64Disassembler *Dis = 00630 static_cast<const AArch64Disassembler *>(Decoder); 00631 const MCSubtargetInfo &STI = Dis->getSubtargetInfo(); 00632 00633 Imm |= 0x8000; 00634 Inst.addOperand(MCOperand::CreateImm(Imm)); 00635 00636 bool ValidNamed; 00637 (void)AArch64SysReg::MRSMapper(STI.getFeatureBits()) 00638 .toString(Imm, ValidNamed); 00639 00640 return ValidNamed ? Success : Fail; 00641 } 00642 00643 static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm, 00644 uint64_t Address, 00645 const void *Decoder) { 00646 const AArch64Disassembler *Dis = 00647 static_cast<const AArch64Disassembler *>(Decoder); 00648 const MCSubtargetInfo &STI = Dis->getSubtargetInfo(); 00649 00650 Imm |= 0x8000; 00651 Inst.addOperand(MCOperand::CreateImm(Imm)); 00652 00653 bool ValidNamed; 00654 (void)AArch64SysReg::MSRMapper(STI.getFeatureBits()) 00655 .toString(Imm, ValidNamed); 00656 00657 return ValidNamed ? Success : Fail; 00658 } 00659 00660 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn, 00661 uint64_t Address, 00662 const void *Decoder) { 00663 // This decoder exists to add the dummy Lane operand to the MCInst, which must 00664 // be 1 in assembly but has no other real manifestation. 00665 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 00666 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 00667 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); 00668 00669 if (IsToVec) { 00670 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 00671 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 00672 } else { 00673 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 00674 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 00675 } 00676 00677 // Add the lane 00678 Inst.addOperand(MCOperand::CreateImm(1)); 00679 00680 return Success; 00681 } 00682 00683 static DecodeStatus DecodeVecShiftRImm(llvm::MCInst &Inst, unsigned Imm, 00684 unsigned Add) { 00685 Inst.addOperand(MCOperand::CreateImm(Add - Imm)); 00686 return Success; 00687 } 00688 00689 static DecodeStatus DecodeVecShiftLImm(llvm::MCInst &Inst, unsigned Imm, 00690 unsigned Add) { 00691 Inst.addOperand(MCOperand::CreateImm((Imm + Add) & (Add - 1))); 00692 return Success; 00693 } 00694 00695 static DecodeStatus DecodeVecShiftR64Imm(llvm::MCInst &Inst, unsigned Imm, 00696 uint64_t Addr, const void *Decoder) { 00697 return DecodeVecShiftRImm(Inst, Imm, 64); 00698 } 00699 00700 static DecodeStatus DecodeVecShiftR64ImmNarrow(llvm::MCInst &Inst, unsigned Imm, 00701 uint64_t Addr, 00702 const void *Decoder) { 00703 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64); 00704 } 00705 00706 static DecodeStatus DecodeVecShiftR32Imm(llvm::MCInst &Inst, unsigned Imm, 00707 uint64_t Addr, const void *Decoder) { 00708 return DecodeVecShiftRImm(Inst, Imm, 32); 00709 } 00710 00711 static DecodeStatus DecodeVecShiftR32ImmNarrow(llvm::MCInst &Inst, unsigned Imm, 00712 uint64_t Addr, 00713 const void *Decoder) { 00714 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32); 00715 } 00716 00717 static DecodeStatus DecodeVecShiftR16Imm(llvm::MCInst &Inst, unsigned Imm, 00718 uint64_t Addr, const void *Decoder) { 00719 return DecodeVecShiftRImm(Inst, Imm, 16); 00720 } 00721 00722 static DecodeStatus DecodeVecShiftR16ImmNarrow(llvm::MCInst &Inst, unsigned Imm, 00723 uint64_t Addr, 00724 const void *Decoder) { 00725 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16); 00726 } 00727 00728 static DecodeStatus DecodeVecShiftR8Imm(llvm::MCInst &Inst, unsigned Imm, 00729 uint64_t Addr, const void *Decoder) { 00730 return DecodeVecShiftRImm(Inst, Imm, 8); 00731 } 00732 00733 static DecodeStatus DecodeVecShiftL64Imm(llvm::MCInst &Inst, unsigned Imm, 00734 uint64_t Addr, const void *Decoder) { 00735 return DecodeVecShiftLImm(Inst, Imm, 64); 00736 } 00737 00738 static DecodeStatus DecodeVecShiftL32Imm(llvm::MCInst &Inst, unsigned Imm, 00739 uint64_t Addr, const void *Decoder) { 00740 return DecodeVecShiftLImm(Inst, Imm, 32); 00741 } 00742 00743 static DecodeStatus DecodeVecShiftL16Imm(llvm::MCInst &Inst, unsigned Imm, 00744 uint64_t Addr, const void *Decoder) { 00745 return DecodeVecShiftLImm(Inst, Imm, 16); 00746 } 00747 00748 static DecodeStatus DecodeVecShiftL8Imm(llvm::MCInst &Inst, unsigned Imm, 00749 uint64_t Addr, const void *Decoder) { 00750 return DecodeVecShiftLImm(Inst, Imm, 8); 00751 } 00752 00753 static DecodeStatus DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst, 00754 uint32_t insn, uint64_t Addr, 00755 const void *Decoder) { 00756 unsigned Rd = fieldFromInstruction(insn, 0, 5); 00757 unsigned Rn = fieldFromInstruction(insn, 5, 5); 00758 unsigned Rm = fieldFromInstruction(insn, 16, 5); 00759 unsigned shiftHi = fieldFromInstruction(insn, 22, 2); 00760 unsigned shiftLo = fieldFromInstruction(insn, 10, 6); 00761 unsigned shift = (shiftHi << 6) | shiftLo; 00762 switch (Inst.getOpcode()) { 00763 default: 00764 return Fail; 00765 case AArch64::ADDWrs: 00766 case AArch64::ADDSWrs: 00767 case AArch64::SUBWrs: 00768 case AArch64::SUBSWrs: 00769 // if shift == '11' then ReservedValue() 00770 if (shiftHi == 0x3) 00771 return Fail; 00772 // Deliberate fallthrough 00773 case AArch64::ANDWrs: 00774 case AArch64::ANDSWrs: 00775 case AArch64::BICWrs: 00776 case AArch64::BICSWrs: 00777 case AArch64::ORRWrs: 00778 case AArch64::ORNWrs: 00779 case AArch64::EORWrs: 00780 case AArch64::EONWrs: { 00781 // if sf == '0' and imm6<5> == '1' then ReservedValue() 00782 if (shiftLo >> 5 == 1) 00783 return Fail; 00784 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 00785 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 00786 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 00787 break; 00788 } 00789 case AArch64::ADDXrs: 00790 case AArch64::ADDSXrs: 00791 case AArch64::SUBXrs: 00792 case AArch64::SUBSXrs: 00793 // if shift == '11' then ReservedValue() 00794 if (shiftHi == 0x3) 00795 return Fail; 00796 // Deliberate fallthrough 00797 case AArch64::ANDXrs: 00798 case AArch64::ANDSXrs: 00799 case AArch64::BICXrs: 00800 case AArch64::BICSXrs: 00801 case AArch64::ORRXrs: 00802 case AArch64::ORNXrs: 00803 case AArch64::EORXrs: 00804 case AArch64::EONXrs: 00805 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 00806 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 00807 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 00808 break; 00809 } 00810 00811 Inst.addOperand(MCOperand::CreateImm(shift)); 00812 return Success; 00813 } 00814 00815 static DecodeStatus DecodeMoveImmInstruction(llvm::MCInst &Inst, uint32_t insn, 00816 uint64_t Addr, 00817 const void *Decoder) { 00818 unsigned Rd = fieldFromInstruction(insn, 0, 5); 00819 unsigned imm = fieldFromInstruction(insn, 5, 16); 00820 unsigned shift = fieldFromInstruction(insn, 21, 2); 00821 shift <<= 4; 00822 switch (Inst.getOpcode()) { 00823 default: 00824 return Fail; 00825 case AArch64::MOVZWi: 00826 case AArch64::MOVNWi: 00827 case AArch64::MOVKWi: 00828 if (shift & (1U << 5)) 00829 return Fail; 00830 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 00831 break; 00832 case AArch64::MOVZXi: 00833 case AArch64::MOVNXi: 00834 case AArch64::MOVKXi: 00835 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 00836 break; 00837 } 00838 00839 if (Inst.getOpcode() == AArch64::MOVKWi || 00840 Inst.getOpcode() == AArch64::MOVKXi) 00841 Inst.addOperand(Inst.getOperand(0)); 00842 00843 Inst.addOperand(MCOperand::CreateImm(imm)); 00844 Inst.addOperand(MCOperand::CreateImm(shift)); 00845 return Success; 00846 } 00847 00848 static DecodeStatus DecodeUnsignedLdStInstruction(llvm::MCInst &Inst, 00849 uint32_t insn, uint64_t Addr, 00850 const void *Decoder) { 00851 unsigned Rt = fieldFromInstruction(insn, 0, 5); 00852 unsigned Rn = fieldFromInstruction(insn, 5, 5); 00853 unsigned offset = fieldFromInstruction(insn, 10, 12); 00854 const AArch64Disassembler *Dis = 00855 static_cast<const AArch64Disassembler *>(Decoder); 00856 00857 switch (Inst.getOpcode()) { 00858 default: 00859 return Fail; 00860 case AArch64::PRFMui: 00861 // Rt is an immediate in prefetch. 00862 Inst.addOperand(MCOperand::CreateImm(Rt)); 00863 break; 00864 case AArch64::STRBBui: 00865 case AArch64::LDRBBui: 00866 case AArch64::LDRSBWui: 00867 case AArch64::STRHHui: 00868 case AArch64::LDRHHui: 00869 case AArch64::LDRSHWui: 00870 case AArch64::STRWui: 00871 case AArch64::LDRWui: 00872 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 00873 break; 00874 case AArch64::LDRSBXui: 00875 case AArch64::LDRSHXui: 00876 case AArch64::LDRSWui: 00877 case AArch64::STRXui: 00878 case AArch64::LDRXui: 00879 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 00880 break; 00881 case AArch64::LDRQui: 00882 case AArch64::STRQui: 00883 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 00884 break; 00885 case AArch64::LDRDui: 00886 case AArch64::STRDui: 00887 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 00888 break; 00889 case AArch64::LDRSui: 00890 case AArch64::STRSui: 00891 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 00892 break; 00893 case AArch64::LDRHui: 00894 case AArch64::STRHui: 00895 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 00896 break; 00897 case AArch64::LDRBui: 00898 case AArch64::STRBui: 00899 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 00900 break; 00901 } 00902 00903 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 00904 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4)) 00905 Inst.addOperand(MCOperand::CreateImm(offset)); 00906 return Success; 00907 } 00908 00909 static DecodeStatus DecodeSignedLdStInstruction(llvm::MCInst &Inst, 00910 uint32_t insn, uint64_t Addr, 00911 const void *Decoder) { 00912 unsigned Rt = fieldFromInstruction(insn, 0, 5); 00913 unsigned Rn = fieldFromInstruction(insn, 5, 5); 00914 int64_t offset = fieldFromInstruction(insn, 12, 9); 00915 00916 // offset is a 9-bit signed immediate, so sign extend it to 00917 // fill the unsigned. 00918 if (offset & (1 << (9 - 1))) 00919 offset |= ~((1LL << 9) - 1); 00920 00921 // First operand is always the writeback to the address register, if needed. 00922 switch (Inst.getOpcode()) { 00923 default: 00924 break; 00925 case AArch64::LDRSBWpre: 00926 case AArch64::LDRSHWpre: 00927 case AArch64::STRBBpre: 00928 case AArch64::LDRBBpre: 00929 case AArch64::STRHHpre: 00930 case AArch64::LDRHHpre: 00931 case AArch64::STRWpre: 00932 case AArch64::LDRWpre: 00933 case AArch64::LDRSBWpost: 00934 case AArch64::LDRSHWpost: 00935 case AArch64::STRBBpost: 00936 case AArch64::LDRBBpost: 00937 case AArch64::STRHHpost: 00938 case AArch64::LDRHHpost: 00939 case AArch64::STRWpost: 00940 case AArch64::LDRWpost: 00941 case AArch64::LDRSBXpre: 00942 case AArch64::LDRSHXpre: 00943 case AArch64::STRXpre: 00944 case AArch64::LDRSWpre: 00945 case AArch64::LDRXpre: 00946 case AArch64::LDRSBXpost: 00947 case AArch64::LDRSHXpost: 00948 case AArch64::STRXpost: 00949 case AArch64::LDRSWpost: 00950 case AArch64::LDRXpost: 00951 case AArch64::LDRQpre: 00952 case AArch64::STRQpre: 00953 case AArch64::LDRQpost: 00954 case AArch64::STRQpost: 00955 case AArch64::LDRDpre: 00956 case AArch64::STRDpre: 00957 case AArch64::LDRDpost: 00958 case AArch64::STRDpost: 00959 case AArch64::LDRSpre: 00960 case AArch64::STRSpre: 00961 case AArch64::LDRSpost: 00962 case AArch64::STRSpost: 00963 case AArch64::LDRHpre: 00964 case AArch64::STRHpre: 00965 case AArch64::LDRHpost: 00966 case AArch64::STRHpost: 00967 case AArch64::LDRBpre: 00968 case AArch64::STRBpre: 00969 case AArch64::LDRBpost: 00970 case AArch64::STRBpost: 00971 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 00972 break; 00973 } 00974 00975 switch (Inst.getOpcode()) { 00976 default: 00977 return Fail; 00978 case AArch64::PRFUMi: 00979 // Rt is an immediate in prefetch. 00980 Inst.addOperand(MCOperand::CreateImm(Rt)); 00981 break; 00982 case AArch64::STURBBi: 00983 case AArch64::LDURBBi: 00984 case AArch64::LDURSBWi: 00985 case AArch64::STURHHi: 00986 case AArch64::LDURHHi: 00987 case AArch64::LDURSHWi: 00988 case AArch64::STURWi: 00989 case AArch64::LDURWi: 00990 case AArch64::LDTRSBWi: 00991 case AArch64::LDTRSHWi: 00992 case AArch64::STTRWi: 00993 case AArch64::LDTRWi: 00994 case AArch64::STTRHi: 00995 case AArch64::LDTRHi: 00996 case AArch64::LDTRBi: 00997 case AArch64::STTRBi: 00998 case AArch64::LDRSBWpre: 00999 case AArch64::LDRSHWpre: 01000 case AArch64::STRBBpre: 01001 case AArch64::LDRBBpre: 01002 case AArch64::STRHHpre: 01003 case AArch64::LDRHHpre: 01004 case AArch64::STRWpre: 01005 case AArch64::LDRWpre: 01006 case AArch64::LDRSBWpost: 01007 case AArch64::LDRSHWpost: 01008 case AArch64::STRBBpost: 01009 case AArch64::LDRBBpost: 01010 case AArch64::STRHHpost: 01011 case AArch64::LDRHHpost: 01012 case AArch64::STRWpost: 01013 case AArch64::LDRWpost: 01014 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 01015 break; 01016 case AArch64::LDURSBXi: 01017 case AArch64::LDURSHXi: 01018 case AArch64::LDURSWi: 01019 case AArch64::STURXi: 01020 case AArch64::LDURXi: 01021 case AArch64::LDTRSBXi: 01022 case AArch64::LDTRSHXi: 01023 case AArch64::LDTRSWi: 01024 case AArch64::STTRXi: 01025 case AArch64::LDTRXi: 01026 case AArch64::LDRSBXpre: 01027 case AArch64::LDRSHXpre: 01028 case AArch64::STRXpre: 01029 case AArch64::LDRSWpre: 01030 case AArch64::LDRXpre: 01031 case AArch64::LDRSBXpost: 01032 case AArch64::LDRSHXpost: 01033 case AArch64::STRXpost: 01034 case AArch64::LDRSWpost: 01035 case AArch64::LDRXpost: 01036 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 01037 break; 01038 case AArch64::LDURQi: 01039 case AArch64::STURQi: 01040 case AArch64::LDRQpre: 01041 case AArch64::STRQpre: 01042 case AArch64::LDRQpost: 01043 case AArch64::STRQpost: 01044 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 01045 break; 01046 case AArch64::LDURDi: 01047 case AArch64::STURDi: 01048 case AArch64::LDRDpre: 01049 case AArch64::STRDpre: 01050 case AArch64::LDRDpost: 01051 case AArch64::STRDpost: 01052 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 01053 break; 01054 case AArch64::LDURSi: 01055 case AArch64::STURSi: 01056 case AArch64::LDRSpre: 01057 case AArch64::STRSpre: 01058 case AArch64::LDRSpost: 01059 case AArch64::STRSpost: 01060 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 01061 break; 01062 case AArch64::LDURHi: 01063 case AArch64::STURHi: 01064 case AArch64::LDRHpre: 01065 case AArch64::STRHpre: 01066 case AArch64::LDRHpost: 01067 case AArch64::STRHpost: 01068 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 01069 break; 01070 case AArch64::LDURBi: 01071 case AArch64::STURBi: 01072 case AArch64::LDRBpre: 01073 case AArch64::STRBpre: 01074 case AArch64::LDRBpost: 01075 case AArch64::STRBpost: 01076 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 01077 break; 01078 } 01079 01080 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 01081 Inst.addOperand(MCOperand::CreateImm(offset)); 01082 01083 bool IsLoad = fieldFromInstruction(insn, 22, 1); 01084 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0; 01085 bool IsFP = fieldFromInstruction(insn, 26, 1); 01086 01087 // Cannot write back to a transfer register (but xzr != sp). 01088 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) 01089 return SoftFail; 01090 01091 return Success; 01092 } 01093 01094 static DecodeStatus DecodeExclusiveLdStInstruction(llvm::MCInst &Inst, 01095 uint32_t insn, uint64_t Addr, 01096 const void *Decoder) { 01097 unsigned Rt = fieldFromInstruction(insn, 0, 5); 01098 unsigned Rn = fieldFromInstruction(insn, 5, 5); 01099 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 01100 unsigned Rs = fieldFromInstruction(insn, 16, 5); 01101 01102 unsigned Opcode = Inst.getOpcode(); 01103 switch (Opcode) { 01104 default: 01105 return Fail; 01106 case AArch64::STLXRW: 01107 case AArch64::STLXRB: 01108 case AArch64::STLXRH: 01109 case AArch64::STXRW: 01110 case AArch64::STXRB: 01111 case AArch64::STXRH: 01112 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 01113 // FALLTHROUGH 01114 case AArch64::LDARW: 01115 case AArch64::LDARB: 01116 case AArch64::LDARH: 01117 case AArch64::LDAXRW: 01118 case AArch64::LDAXRB: 01119 case AArch64::LDAXRH: 01120 case AArch64::LDXRW: 01121 case AArch64::LDXRB: 01122 case AArch64::LDXRH: 01123 case AArch64::STLRW: 01124 case AArch64::STLRB: 01125 case AArch64::STLRH: 01126 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 01127 break; 01128 case AArch64::STLXRX: 01129 case AArch64::STXRX: 01130 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 01131 // FALLTHROUGH 01132 case AArch64::LDARX: 01133 case AArch64::LDAXRX: 01134 case AArch64::LDXRX: 01135 case AArch64::STLRX: 01136 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 01137 break; 01138 case AArch64::STLXPW: 01139 case AArch64::STXPW: 01140 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 01141 // FALLTHROUGH 01142 case AArch64::LDAXPW: 01143 case AArch64::LDXPW: 01144 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 01145 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 01146 break; 01147 case AArch64::STLXPX: 01148 case AArch64::STXPX: 01149 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 01150 // FALLTHROUGH 01151 case AArch64::LDAXPX: 01152 case AArch64::LDXPX: 01153 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 01154 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 01155 break; 01156 } 01157 01158 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 01159 01160 // You shouldn't load to the same register twice in an instruction... 01161 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW || 01162 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) && 01163 Rt == Rt2) 01164 return SoftFail; 01165 01166 return Success; 01167 } 01168 01169 static DecodeStatus DecodePairLdStInstruction(llvm::MCInst &Inst, uint32_t insn, 01170 uint64_t Addr, 01171 const void *Decoder) { 01172 unsigned Rt = fieldFromInstruction(insn, 0, 5); 01173 unsigned Rn = fieldFromInstruction(insn, 5, 5); 01174 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 01175 int64_t offset = fieldFromInstruction(insn, 15, 7); 01176 bool IsLoad = fieldFromInstruction(insn, 22, 1); 01177 01178 // offset is a 7-bit signed immediate, so sign extend it to 01179 // fill the unsigned. 01180 if (offset & (1 << (7 - 1))) 01181 offset |= ~((1LL << 7) - 1); 01182 01183 unsigned Opcode = Inst.getOpcode(); 01184 bool NeedsDisjointWritebackTransfer = false; 01185 01186 // First operand is always writeback of base register. 01187 switch (Opcode) { 01188 default: 01189 break; 01190 case AArch64::LDPXpost: 01191 case AArch64::STPXpost: 01192 case AArch64::LDPSWpost: 01193 case AArch64::LDPXpre: 01194 case AArch64::STPXpre: 01195 case AArch64::LDPSWpre: 01196 case AArch64::LDPWpost: 01197 case AArch64::STPWpost: 01198 case AArch64::LDPWpre: 01199 case AArch64::STPWpre: 01200 case AArch64::LDPQpost: 01201 case AArch64::STPQpost: 01202 case AArch64::LDPQpre: 01203 case AArch64::STPQpre: 01204 case AArch64::LDPDpost: 01205 case AArch64::STPDpost: 01206 case AArch64::LDPDpre: 01207 case AArch64::STPDpre: 01208 case AArch64::LDPSpost: 01209 case AArch64::STPSpost: 01210 case AArch64::LDPSpre: 01211 case AArch64::STPSpre: 01212 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 01213 break; 01214 } 01215 01216 switch (Opcode) { 01217 default: 01218 return Fail; 01219 case AArch64::LDPXpost: 01220 case AArch64::STPXpost: 01221 case AArch64::LDPSWpost: 01222 case AArch64::LDPXpre: 01223 case AArch64::STPXpre: 01224 case AArch64::LDPSWpre: 01225 NeedsDisjointWritebackTransfer = true; 01226 // Fallthrough 01227 case AArch64::LDNPXi: 01228 case AArch64::STNPXi: 01229 case AArch64::LDPXi: 01230 case AArch64::STPXi: 01231 case AArch64::LDPSWi: 01232 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 01233 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 01234 break; 01235 case AArch64::LDPWpost: 01236 case AArch64::STPWpost: 01237 case AArch64::LDPWpre: 01238 case AArch64::STPWpre: 01239 NeedsDisjointWritebackTransfer = true; 01240 // Fallthrough 01241 case AArch64::LDNPWi: 01242 case AArch64::STNPWi: 01243 case AArch64::LDPWi: 01244 case AArch64::STPWi: 01245 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 01246 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 01247 break; 01248 case AArch64::LDNPQi: 01249 case AArch64::STNPQi: 01250 case AArch64::LDPQpost: 01251 case AArch64::STPQpost: 01252 case AArch64::LDPQi: 01253 case AArch64::STPQi: 01254 case AArch64::LDPQpre: 01255 case AArch64::STPQpre: 01256 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 01257 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); 01258 break; 01259 case AArch64::LDNPDi: 01260 case AArch64::STNPDi: 01261 case AArch64::LDPDpost: 01262 case AArch64::STPDpost: 01263 case AArch64::LDPDi: 01264 case AArch64::STPDi: 01265 case AArch64::LDPDpre: 01266 case AArch64::STPDpre: 01267 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 01268 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); 01269 break; 01270 case AArch64::LDNPSi: 01271 case AArch64::STNPSi: 01272 case AArch64::LDPSpost: 01273 case AArch64::STPSpost: 01274 case AArch64::LDPSi: 01275 case AArch64::STPSi: 01276 case AArch64::LDPSpre: 01277 case AArch64::STPSpre: 01278 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 01279 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); 01280 break; 01281 } 01282 01283 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 01284 Inst.addOperand(MCOperand::CreateImm(offset)); 01285 01286 // You shouldn't load to the same register twice in an instruction... 01287 if (IsLoad && Rt == Rt2) 01288 return SoftFail; 01289 01290 // ... or do any operation that writes-back to a transfer register. But note 01291 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. 01292 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn)) 01293 return SoftFail; 01294 01295 return Success; 01296 } 01297 01298 static DecodeStatus DecodeAddSubERegInstruction(llvm::MCInst &Inst, 01299 uint32_t insn, uint64_t Addr, 01300 const void *Decoder) { 01301 unsigned Rd = fieldFromInstruction(insn, 0, 5); 01302 unsigned Rn = fieldFromInstruction(insn, 5, 5); 01303 unsigned Rm = fieldFromInstruction(insn, 16, 5); 01304 unsigned extend = fieldFromInstruction(insn, 10, 6); 01305 01306 unsigned shift = extend & 0x7; 01307 if (shift > 4) 01308 return Fail; 01309 01310 switch (Inst.getOpcode()) { 01311 default: 01312 return Fail; 01313 case AArch64::ADDWrx: 01314 case AArch64::SUBWrx: 01315 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 01316 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 01317 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 01318 break; 01319 case AArch64::ADDSWrx: 01320 case AArch64::SUBSWrx: 01321 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 01322 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 01323 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 01324 break; 01325 case AArch64::ADDXrx: 01326 case AArch64::SUBXrx: 01327 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 01328 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 01329 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 01330 break; 01331 case AArch64::ADDSXrx: 01332 case AArch64::SUBSXrx: 01333 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 01334 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 01335 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 01336 break; 01337 case AArch64::ADDXrx64: 01338 case AArch64::SUBXrx64: 01339 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 01340 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 01341 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 01342 break; 01343 case AArch64::SUBSXrx64: 01344 case AArch64::ADDSXrx64: 01345 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 01346 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 01347 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 01348 break; 01349 } 01350 01351 Inst.addOperand(MCOperand::CreateImm(extend)); 01352 return Success; 01353 } 01354 01355 static DecodeStatus DecodeLogicalImmInstruction(llvm::MCInst &Inst, 01356 uint32_t insn, uint64_t Addr, 01357 const void *Decoder) { 01358 unsigned Rd = fieldFromInstruction(insn, 0, 5); 01359 unsigned Rn = fieldFromInstruction(insn, 5, 5); 01360 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 01361 unsigned imm; 01362 01363 if (Datasize) { 01364 if (Inst.getOpcode() == AArch64::ANDSXri) 01365 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 01366 else 01367 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 01368 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 01369 imm = fieldFromInstruction(insn, 10, 13); 01370 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 01371 return Fail; 01372 } else { 01373 if (Inst.getOpcode() == AArch64::ANDSWri) 01374 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 01375 else 01376 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 01377 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 01378 imm = fieldFromInstruction(insn, 10, 12); 01379 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32)) 01380 return Fail; 01381 } 01382 Inst.addOperand(MCOperand::CreateImm(imm)); 01383 return Success; 01384 } 01385 01386 static DecodeStatus DecodeModImmInstruction(llvm::MCInst &Inst, uint32_t insn, 01387 uint64_t Addr, 01388 const void *Decoder) { 01389 unsigned Rd = fieldFromInstruction(insn, 0, 5); 01390 unsigned cmode = fieldFromInstruction(insn, 12, 4); 01391 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 01392 imm |= fieldFromInstruction(insn, 5, 5); 01393 01394 if (Inst.getOpcode() == AArch64::MOVID) 01395 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); 01396 else 01397 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 01398 01399 Inst.addOperand(MCOperand::CreateImm(imm)); 01400 01401 switch (Inst.getOpcode()) { 01402 default: 01403 break; 01404 case AArch64::MOVIv4i16: 01405 case AArch64::MOVIv8i16: 01406 case AArch64::MVNIv4i16: 01407 case AArch64::MVNIv8i16: 01408 case AArch64::MOVIv2i32: 01409 case AArch64::MOVIv4i32: 01410 case AArch64::MVNIv2i32: 01411 case AArch64::MVNIv4i32: 01412 Inst.addOperand(MCOperand::CreateImm((cmode & 6) << 2)); 01413 break; 01414 case AArch64::MOVIv2s_msl: 01415 case AArch64::MOVIv4s_msl: 01416 case AArch64::MVNIv2s_msl: 01417 case AArch64::MVNIv4s_msl: 01418 Inst.addOperand(MCOperand::CreateImm(cmode & 1 ? 0x110 : 0x108)); 01419 break; 01420 } 01421 01422 return Success; 01423 } 01424 01425 static DecodeStatus DecodeModImmTiedInstruction(llvm::MCInst &Inst, 01426 uint32_t insn, uint64_t Addr, 01427 const void *Decoder) { 01428 unsigned Rd = fieldFromInstruction(insn, 0, 5); 01429 unsigned cmode = fieldFromInstruction(insn, 12, 4); 01430 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 01431 imm |= fieldFromInstruction(insn, 5, 5); 01432 01433 // Tied operands added twice. 01434 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 01435 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 01436 01437 Inst.addOperand(MCOperand::CreateImm(imm)); 01438 Inst.addOperand(MCOperand::CreateImm((cmode & 6) << 2)); 01439 01440 return Success; 01441 } 01442 01443 static DecodeStatus DecodeAdrInstruction(llvm::MCInst &Inst, uint32_t insn, 01444 uint64_t Addr, const void *Decoder) { 01445 unsigned Rd = fieldFromInstruction(insn, 0, 5); 01446 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2; 01447 imm |= fieldFromInstruction(insn, 29, 2); 01448 const AArch64Disassembler *Dis = 01449 static_cast<const AArch64Disassembler *>(Decoder); 01450 01451 // Sign-extend the 21-bit immediate. 01452 if (imm & (1 << (21 - 1))) 01453 imm |= ~((1LL << 21) - 1); 01454 01455 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 01456 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4)) 01457 Inst.addOperand(MCOperand::CreateImm(imm)); 01458 01459 return Success; 01460 } 01461 01462 static DecodeStatus DecodeBaseAddSubImm(llvm::MCInst &Inst, uint32_t insn, 01463 uint64_t Addr, const void *Decoder) { 01464 unsigned Rd = fieldFromInstruction(insn, 0, 5); 01465 unsigned Rn = fieldFromInstruction(insn, 5, 5); 01466 unsigned Imm = fieldFromInstruction(insn, 10, 14); 01467 unsigned S = fieldFromInstruction(insn, 29, 1); 01468 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 01469 01470 unsigned ShifterVal = (Imm >> 12) & 3; 01471 unsigned ImmVal = Imm & 0xFFF; 01472 const AArch64Disassembler *Dis = 01473 static_cast<const AArch64Disassembler *>(Decoder); 01474 01475 if (ShifterVal != 0 && ShifterVal != 1) 01476 return Fail; 01477 01478 if (Datasize) { 01479 if (Rd == 31 && !S) 01480 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 01481 else 01482 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 01483 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 01484 } else { 01485 if (Rd == 31 && !S) 01486 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 01487 else 01488 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 01489 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 01490 } 01491 01492 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4)) 01493 Inst.addOperand(MCOperand::CreateImm(ImmVal)); 01494 Inst.addOperand(MCOperand::CreateImm(12 * ShifterVal)); 01495 return Success; 01496 } 01497 01498 static DecodeStatus DecodeUnconditionalBranch(llvm::MCInst &Inst, uint32_t insn, 01499 uint64_t Addr, 01500 const void *Decoder) { 01501 int64_t imm = fieldFromInstruction(insn, 0, 26); 01502 const AArch64Disassembler *Dis = 01503 static_cast<const AArch64Disassembler *>(Decoder); 01504 01505 // Sign-extend the 26-bit immediate. 01506 if (imm & (1 << (26 - 1))) 01507 imm |= ~((1LL << 26) - 1); 01508 01509 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4)) 01510 Inst.addOperand(MCOperand::CreateImm(imm)); 01511 01512 return Success; 01513 } 01514 01515 static DecodeStatus DecodeSystemPStateInstruction(llvm::MCInst &Inst, 01516 uint32_t insn, uint64_t Addr, 01517 const void *Decoder) { 01518 uint64_t op1 = fieldFromInstruction(insn, 16, 3); 01519 uint64_t op2 = fieldFromInstruction(insn, 5, 3); 01520 uint64_t crm = fieldFromInstruction(insn, 8, 4); 01521 01522 uint64_t pstate_field = (op1 << 3) | op2; 01523 01524 Inst.addOperand(MCOperand::CreateImm(pstate_field)); 01525 Inst.addOperand(MCOperand::CreateImm(crm)); 01526 01527 bool ValidNamed; 01528 (void)AArch64PState::PStateMapper().toString(pstate_field, ValidNamed); 01529 01530 return ValidNamed ? Success : Fail; 01531 } 01532 01533 static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn, 01534 uint64_t Addr, const void *Decoder) { 01535 uint64_t Rt = fieldFromInstruction(insn, 0, 5); 01536 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5; 01537 bit |= fieldFromInstruction(insn, 19, 5); 01538 int64_t dst = fieldFromInstruction(insn, 5, 14); 01539 const AArch64Disassembler *Dis = 01540 static_cast<const AArch64Disassembler *>(Decoder); 01541 01542 // Sign-extend 14-bit immediate. 01543 if (dst & (1 << (14 - 1))) 01544 dst |= ~((1LL << 14) - 1); 01545 01546 if (fieldFromInstruction(insn, 31, 1) == 0) 01547 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 01548 else 01549 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 01550 Inst.addOperand(MCOperand::CreateImm(bit)); 01551 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4)) 01552 Inst.addOperand(MCOperand::CreateImm(dst)); 01553 01554 return Success; 01555 }
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