LLVM API Documentation
00001 //===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file is distributed under the University of Illinois Open Source 00006 // License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 /// \file 00011 /// \brief This file provides AMDGPU specific target descriptions. 00012 // 00013 //===----------------------------------------------------------------------===// 00014 00015 #include "AMDGPUMCTargetDesc.h" 00016 #include "AMDGPUMCAsmInfo.h" 00017 #include "InstPrinter/AMDGPUInstPrinter.h" 00018 #include "llvm/MC/MCCodeGenInfo.h" 00019 #include "llvm/MC/MCInstrInfo.h" 00020 #include "llvm/MC/MCRegisterInfo.h" 00021 #include "llvm/MC/MCStreamer.h" 00022 #include "llvm/MC/MCSubtargetInfo.h" 00023 #include "llvm/MC/MachineLocation.h" 00024 #include "llvm/Support/ErrorHandling.h" 00025 #include "llvm/Support/TargetRegistry.h" 00026 00027 using namespace llvm; 00028 00029 #define GET_INSTRINFO_MC_DESC 00030 #include "AMDGPUGenInstrInfo.inc" 00031 00032 #define GET_SUBTARGETINFO_MC_DESC 00033 #include "AMDGPUGenSubtargetInfo.inc" 00034 00035 #define GET_REGINFO_MC_DESC 00036 #include "AMDGPUGenRegisterInfo.inc" 00037 00038 static MCInstrInfo *createAMDGPUMCInstrInfo() { 00039 MCInstrInfo *X = new MCInstrInfo(); 00040 InitAMDGPUMCInstrInfo(X); 00041 return X; 00042 } 00043 00044 static MCRegisterInfo *createAMDGPUMCRegisterInfo(StringRef TT) { 00045 MCRegisterInfo *X = new MCRegisterInfo(); 00046 InitAMDGPUMCRegisterInfo(X, 0); 00047 return X; 00048 } 00049 00050 static MCSubtargetInfo *createAMDGPUMCSubtargetInfo(StringRef TT, StringRef CPU, 00051 StringRef FS) { 00052 MCSubtargetInfo * X = new MCSubtargetInfo(); 00053 InitAMDGPUMCSubtargetInfo(X, TT, CPU, FS); 00054 return X; 00055 } 00056 00057 static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(StringRef TT, Reloc::Model RM, 00058 CodeModel::Model CM, 00059 CodeGenOpt::Level OL) { 00060 MCCodeGenInfo *X = new MCCodeGenInfo(); 00061 X->InitMCCodeGenInfo(RM, CM, OL); 00062 return X; 00063 } 00064 00065 static MCInstPrinter *createAMDGPUMCInstPrinter(const Target &T, 00066 unsigned SyntaxVariant, 00067 const MCAsmInfo &MAI, 00068 const MCInstrInfo &MII, 00069 const MCRegisterInfo &MRI, 00070 const MCSubtargetInfo &STI) { 00071 return new AMDGPUInstPrinter(MAI, MII, MRI); 00072 } 00073 00074 static MCCodeEmitter *createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII, 00075 const MCRegisterInfo &MRI, 00076 const MCSubtargetInfo &STI, 00077 MCContext &Ctx) { 00078 if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) { 00079 return createSIMCCodeEmitter(MCII, MRI, STI, Ctx); 00080 } else { 00081 return createR600MCCodeEmitter(MCII, MRI, STI); 00082 } 00083 } 00084 00085 static MCStreamer *createMCStreamer(const Target &T, StringRef TT, 00086 MCContext &Ctx, MCAsmBackend &MAB, 00087 raw_ostream &_OS, 00088 MCCodeEmitter *_Emitter, 00089 const MCSubtargetInfo &STI, 00090 bool RelaxAll, 00091 bool NoExecStack) { 00092 return createELFStreamer(Ctx, MAB, _OS, _Emitter, false, false); 00093 } 00094 00095 extern "C" void LLVMInitializeR600TargetMC() { 00096 00097 RegisterMCAsmInfo<AMDGPUMCAsmInfo> Y(TheAMDGPUTarget); 00098 00099 TargetRegistry::RegisterMCCodeGenInfo(TheAMDGPUTarget, createAMDGPUMCCodeGenInfo); 00100 00101 TargetRegistry::RegisterMCInstrInfo(TheAMDGPUTarget, createAMDGPUMCInstrInfo); 00102 00103 TargetRegistry::RegisterMCRegInfo(TheAMDGPUTarget, createAMDGPUMCRegisterInfo); 00104 00105 TargetRegistry::RegisterMCSubtargetInfo(TheAMDGPUTarget, createAMDGPUMCSubtargetInfo); 00106 00107 TargetRegistry::RegisterMCInstPrinter(TheAMDGPUTarget, createAMDGPUMCInstPrinter); 00108 00109 TargetRegistry::RegisterMCCodeEmitter(TheAMDGPUTarget, createAMDGPUMCCodeEmitter); 00110 00111 TargetRegistry::RegisterMCAsmBackend(TheAMDGPUTarget, createAMDGPUAsmBackend); 00112 00113 TargetRegistry::RegisterMCObjectStreamer(TheAMDGPUTarget, createMCStreamer); 00114 }