LLVM: PPCDisassembler.cpp Source File

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00001 //===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 
00010 #include "PPC.h"
00011 #include "llvm/MC/MCDisassembler.h"
00012 #include "llvm/MC/MCFixedLenDisassembler.h"
00013 #include "llvm/MC/MCInst.h"
00014 #include "llvm/MC/MCSubtargetInfo.h"
00015 #include "llvm/Support/MemoryObject.h"
00016 #include "llvm/Support/TargetRegistry.h"
00017 
00018 using namespace llvm;
00019 
00020 #define DEBUG_TYPE "ppc-disassembler"
00021 
00022 typedef MCDisassembler::DecodeStatus DecodeStatus;
00023 
00024 namespace {
00025 class PPCDisassembler : public MCDisassembler {
00026 public:
00027   PPCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
00028     : MCDisassembler(STI, Ctx) {}
00029   virtual ~PPCDisassembler() {}
00030 
00031   // Override MCDisassembler.
00032   DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
00033                               const MemoryObject &region, uint64_t address,
00034                               raw_ostream &vStream,
00035                               raw_ostream &cStream) const override;
00036 };
00037 } // end anonymous namespace
00038 
00039 static MCDisassembler *createPPCDisassembler(const Target &T,
00040                                              const MCSubtargetInfo &STI,
00041                                              MCContext &Ctx) {
00042   return new PPCDisassembler(STI, Ctx);
00043 }
00044 
00045 extern "C" void LLVMInitializePowerPCDisassembler() {
00046   // Register the disassembler for each target.
00047   TargetRegistry::RegisterMCDisassembler(ThePPC32Target,
00048                                          createPPCDisassembler);
00049   TargetRegistry::RegisterMCDisassembler(ThePPC64Target,
00050                                          createPPCDisassembler);
00051   TargetRegistry::RegisterMCDisassembler(ThePPC64LETarget,
00052                                          createPPCDisassembler);
00053 }
00054 
00055 // FIXME: These can be generated by TableGen from the existing register
00056 // encoding values!
00057 
00058 static const unsigned CRRegs[] = {
00059   PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
00060   PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
00061 };
00062 
00063 static const unsigned CRBITRegs[] = {
00064   PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
00065   PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
00066   PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
00067   PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
00068   PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
00069   PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
00070   PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
00071   PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
00072 };
00073 
00074 static const unsigned FRegs[] = {
00075   PPC::F0, PPC::F1, PPC::F2, PPC::F3,
00076   PPC::F4, PPC::F5, PPC::F6, PPC::F7,
00077   PPC::F8, PPC::F9, PPC::F10, PPC::F11,
00078   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
00079   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
00080   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
00081   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
00082   PPC::F28, PPC::F29, PPC::F30, PPC::F31
00083 };
00084 
00085 static const unsigned VRegs[] = {
00086   PPC::V0, PPC::V1, PPC::V2, PPC::V3,
00087   PPC::V4, PPC::V5, PPC::V6, PPC::V7,
00088   PPC::V8, PPC::V9, PPC::V10, PPC::V11,
00089   PPC::V12, PPC::V13, PPC::V14, PPC::V15,
00090   PPC::V16, PPC::V17, PPC::V18, PPC::V19,
00091   PPC::V20, PPC::V21, PPC::V22, PPC::V23,
00092   PPC::V24, PPC::V25, PPC::V26, PPC::V27,
00093   PPC::V28, PPC::V29, PPC::V30, PPC::V31
00094 };
00095 
00096 static const unsigned VSRegs[] = {
00097   PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3,
00098   PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7,
00099   PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11,
00100   PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
00101   PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
00102   PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
00103   PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
00104   PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
00105 
00106   PPC::VSH0, PPC::VSH1, PPC::VSH2, PPC::VSH3,
00107   PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7,
00108   PPC::VSH8, PPC::VSH9, PPC::VSH10, PPC::VSH11,
00109   PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15,
00110   PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19,
00111   PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23,
00112   PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27,
00113   PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31
00114 };
00115 
00116 static const unsigned VSFRegs[] = {
00117   PPC::F0, PPC::F1, PPC::F2, PPC::F3,
00118   PPC::F4, PPC::F5, PPC::F6, PPC::F7,
00119   PPC::F8, PPC::F9, PPC::F10, PPC::F11,
00120   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
00121   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
00122   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
00123   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
00124   PPC::F28, PPC::F29, PPC::F30, PPC::F31,
00125 
00126   PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
00127   PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
00128   PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
00129   PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
00130   PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
00131   PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
00132   PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
00133   PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
00134 };
00135 
00136 static const unsigned GPRegs[] = {
00137   PPC::R0, PPC::R1, PPC::R2, PPC::R3,
00138   PPC::R4, PPC::R5, PPC::R6, PPC::R7,
00139   PPC::R8, PPC::R9, PPC::R10, PPC::R11,
00140   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
00141   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
00142   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
00143   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
00144   PPC::R28, PPC::R29, PPC::R30, PPC::R31
00145 };
00146 
00147 static const unsigned GP0Regs[] = {
00148   PPC::ZERO, PPC::R1, PPC::R2, PPC::R3,
00149   PPC::R4, PPC::R5, PPC::R6, PPC::R7,
00150   PPC::R8, PPC::R9, PPC::R10, PPC::R11,
00151   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
00152   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
00153   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
00154   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
00155   PPC::R28, PPC::R29, PPC::R30, PPC::R31
00156 };
00157 
00158 static const unsigned G8Regs[] = {
00159   PPC::X0, PPC::X1, PPC::X2, PPC::X3,
00160   PPC::X4, PPC::X5, PPC::X6, PPC::X7,
00161   PPC::X8, PPC::X9, PPC::X10, PPC::X11,
00162   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
00163   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
00164   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
00165   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
00166   PPC::X28, PPC::X29, PPC::X30, PPC::X31
00167 };
00168 
00169 template <std::size_t N>
00170 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
00171                                         const unsigned (&Regs)[N]) {
00172   assert(RegNo < N && "Invalid register number");
00173   Inst.addOperand(MCOperand::CreateReg(Regs[RegNo]));
00174   return MCDisassembler::Success;
00175 }
00176 
00177 static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
00178                                             uint64_t Address,
00179                                             const void *Decoder) {
00180   return decodeRegisterClass(Inst, RegNo, CRRegs);
00181 }
00182 
00183 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo,
00184                                             uint64_t Address,
00185                                             const void *Decoder) {
00186   return decodeRegisterClass(Inst, RegNo, CRBITRegs);
00187 }
00188 
00189 static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo,
00190                                             uint64_t Address,
00191                                             const void *Decoder) {
00192   return decodeRegisterClass(Inst, RegNo, FRegs);
00193 }
00194 
00195 static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
00196                                             uint64_t Address,
00197                                             const void *Decoder) {
00198   return decodeRegisterClass(Inst, RegNo, FRegs);
00199 }
00200 
00201 static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
00202                                             uint64_t Address,
00203                                             const void *Decoder) {
00204   return decodeRegisterClass(Inst, RegNo, VRegs);
00205 }
00206 
00207 static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo,
00208                                             uint64_t Address,
00209                                             const void *Decoder) {
00210   return decodeRegisterClass(Inst, RegNo, VSRegs);
00211 }
00212 
00213 static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
00214                                             uint64_t Address,
00215                                             const void *Decoder) {
00216   return decodeRegisterClass(Inst, RegNo, VSFRegs);
00217 }
00218 
00219 static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
00220                                             uint64_t Address,
00221                                             const void *Decoder) {
00222   return decodeRegisterClass(Inst, RegNo, GPRegs);
00223 }
00224 
00225 static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo,
00226                                             uint64_t Address,
00227                                             const void *Decoder) {
00228   return decodeRegisterClass(Inst, RegNo, GP0Regs);
00229 }
00230 
00231 static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
00232                                             uint64_t Address,
00233                                             const void *Decoder) {
00234   return decodeRegisterClass(Inst, RegNo, G8Regs);
00235 }
00236 
00237 #define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass
00238 #define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass
00239 
00240 template<unsigned N>
00241 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
00242                                       int64_t Address, const void *Decoder) {
00243   assert(isUInt<N>(Imm) && "Invalid immediate");
00244   Inst.addOperand(MCOperand::CreateImm(Imm));
00245   return MCDisassembler::Success;
00246 }
00247 
00248 template<unsigned N>
00249 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
00250                                       int64_t Address, const void *Decoder) {
00251   assert(isUInt<N>(Imm) && "Invalid immediate");
00252   Inst.addOperand(MCOperand::CreateImm(SignExtend64<N>(Imm)));
00253   return MCDisassembler::Success;
00254 }
00255 
00256 static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm,
00257                                         int64_t Address, const void *Decoder) {
00258   // Decode the memri field (imm, reg), which has the low 16-bits as the
00259   // displacement and the next 5 bits as the register #.
00260 
00261   uint64_t Base = Imm >> 16;
00262   uint64_t Disp = Imm & 0xFFFF;
00263 
00264   assert(Base < 32 && "Invalid base register");
00265 
00266   switch (Inst.getOpcode()) {
00267   default: break;
00268   case PPC::LBZU:
00269   case PPC::LHAU:
00270   case PPC::LHZU:
00271   case PPC::LWZU:
00272   case PPC::LFSU:
00273   case PPC::LFDU:
00274     // Add the tied output operand.
00275     Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base]));
00276     break;
00277   case PPC::STBU:
00278   case PPC::STHU:
00279   case PPC::STWU:
00280   case PPC::STFSU:
00281   case PPC::STFDU:
00282     Inst.insert(Inst.begin(), MCOperand::CreateReg(GP0Regs[Base]));
00283     break;
00284   }
00285 
00286   Inst.addOperand(MCOperand::CreateImm(SignExtend64<16>(Disp)));
00287   Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base]));
00288   return MCDisassembler::Success;
00289 }
00290 
00291 static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm,
00292                                          int64_t Address, const void *Decoder) {
00293   // Decode the memrix field (imm, reg), which has the low 14-bits as the
00294   // displacement and the next 5 bits as the register #.
00295 
00296   uint64_t Base = Imm >> 14;
00297   uint64_t Disp = Imm & 0x3FFF;
00298 
00299   assert(Base < 32 && "Invalid base register");
00300 
00301   if (Inst.getOpcode() == PPC::LDU)
00302     // Add the tied output operand.
00303     Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base]));
00304   else if (Inst.getOpcode() == PPC::STDU)
00305     Inst.insert(Inst.begin(), MCOperand::CreateReg(GP0Regs[Base]));
00306 
00307   Inst.addOperand(MCOperand::CreateImm(SignExtend64<16>(Disp << 2)));
00308   Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base]));
00309   return MCDisassembler::Success;
00310 }
00311 
00312 static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm,
00313                                         int64_t Address, const void *Decoder) {
00314   // The cr bit encoding is 0x80 >> cr_reg_num.
00315 
00316   unsigned Zeros = countTrailingZeros(Imm);
00317   assert(Zeros < 8 && "Invalid CR bit value");
00318 
00319   Inst.addOperand(MCOperand::CreateReg(CRRegs[7 - Zeros]));
00320   return MCDisassembler::Success;
00321 }
00322 
00323 #include "PPCGenDisassemblerTables.inc"
00324 
00325 DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
00326                                                  const MemoryObject &Region,
00327                                                  uint64_t Address,
00328                                                  raw_ostream &os,
00329                                                  raw_ostream &cs) const {
00330   // Get the four bytes of the instruction.
00331   uint8_t Bytes[4];
00332   Size = 4;
00333   if (Region.readBytes(Address, Size, Bytes) == -1) {
00334     Size = 0;
00335     return MCDisassembler::Fail;
00336   }
00337 
00338   // The instruction is big-endian encoded.
00339   uint32_t Inst = (Bytes[0] << 24) |
00340                   (Bytes[1] << 16) |
00341                   (Bytes[2] <<  8) |
00342                   (Bytes[3] <<  0);
00343 
00344   return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI);
00345 }
00346
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