LLVM API Documentation
00001 //===-- PPCRegisterInfo.h - PowerPC Register Information Impl ---*- C++ -*-===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file is distributed under the University of Illinois Open Source 00006 // License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file contains the PowerPC implementation of the TargetRegisterInfo 00011 // class. 00012 // 00013 //===----------------------------------------------------------------------===// 00014 00015 #ifndef LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H 00016 #define LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H 00017 00018 #include "PPC.h" 00019 #include "llvm/ADT/DenseMap.h" 00020 00021 #define GET_REGINFO_HEADER 00022 #include "PPCGenRegisterInfo.inc" 00023 00024 namespace llvm { 00025 class PPCSubtarget; 00026 class TargetInstrInfo; 00027 class Type; 00028 00029 class PPCRegisterInfo : public PPCGenRegisterInfo { 00030 DenseMap<unsigned, unsigned> ImmToIdxMap; 00031 const PPCSubtarget &Subtarget; 00032 public: 00033 PPCRegisterInfo(const PPCSubtarget &SubTarget); 00034 00035 /// getPointerRegClass - Return the register class to use to hold pointers. 00036 /// This is used for addressing modes. 00037 const TargetRegisterClass * 00038 getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override; 00039 00040 unsigned getRegPressureLimit(const TargetRegisterClass *RC, 00041 MachineFunction &MF) const override; 00042 00043 const TargetRegisterClass* 00044 getLargestLegalSuperClass(const TargetRegisterClass *RC) const override; 00045 00046 /// Code Generation virtual methods... 00047 const MCPhysReg * 00048 getCalleeSavedRegs(const MachineFunction* MF =nullptr) const override; 00049 const uint32_t *getCallPreservedMask(CallingConv::ID CC) const override; 00050 const uint32_t *getNoPreservedMask() const; 00051 00052 BitVector getReservedRegs(const MachineFunction &MF) const override; 00053 00054 /// We require the register scavenger. 00055 bool requiresRegisterScavenging(const MachineFunction &MF) const override { 00056 return true; 00057 } 00058 00059 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override { 00060 return true; 00061 } 00062 00063 bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override { 00064 return true; 00065 } 00066 00067 bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override { 00068 return true; 00069 } 00070 00071 void lowerDynamicAlloc(MachineBasicBlock::iterator II) const; 00072 void lowerCRSpilling(MachineBasicBlock::iterator II, 00073 unsigned FrameIndex) const; 00074 void lowerCRRestore(MachineBasicBlock::iterator II, 00075 unsigned FrameIndex) const; 00076 void lowerCRBitSpilling(MachineBasicBlock::iterator II, 00077 unsigned FrameIndex) const; 00078 void lowerCRBitRestore(MachineBasicBlock::iterator II, 00079 unsigned FrameIndex) const; 00080 void lowerVRSAVESpilling(MachineBasicBlock::iterator II, 00081 unsigned FrameIndex) const; 00082 void lowerVRSAVERestore(MachineBasicBlock::iterator II, 00083 unsigned FrameIndex) const; 00084 00085 bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, 00086 int &FrameIdx) const override; 00087 void eliminateFrameIndex(MachineBasicBlock::iterator II, 00088 int SPAdj, unsigned FIOperandNum, 00089 RegScavenger *RS = nullptr) const override; 00090 00091 // Support for virtual base registers. 00092 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override; 00093 void materializeFrameBaseRegister(MachineBasicBlock *MBB, 00094 unsigned BaseReg, int FrameIdx, 00095 int64_t Offset) const override; 00096 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 00097 int64_t Offset) const override; 00098 bool isFrameOffsetLegal(const MachineInstr *MI, 00099 int64_t Offset) const override; 00100 00101 // Debug information queries. 00102 unsigned getFrameRegister(const MachineFunction &MF) const override; 00103 00104 // Base pointer (stack realignment) support. 00105 unsigned getBaseRegister(const MachineFunction &MF) const; 00106 bool hasBasePointer(const MachineFunction &MF) const; 00107 bool canRealignStack(const MachineFunction &MF) const; 00108 bool needsStackRealignment(const MachineFunction &MF) const override; 00109 }; 00110 00111 } // end namespace llvm 00112 00113 #endif