#include <TargetRegisterInfo.h>
Detailed Description
Definition at line 36 of file TargetRegisterInfo.h.
Member Typedef Documentation
Definition at line 39 of file TargetRegisterInfo.h.
Definition at line 38 of file TargetRegisterInfo.h.
Definition at line 41 of file TargetRegisterInfo.h.
Definition at line 40 of file TargetRegisterInfo.h.
Member Function Documentation
| iterator llvm::TargetRegisterClass::begin | ( | ) | const [inline] |
begin/end - Return all of the registers in this class.
Definition at line 61 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::begin(), and MC.
Referenced by llvm::PPCInstrInfo::DefinesPredicate(), llvm::RegScavenger::FindUnusedReg(), findUnusedVGPR(), getRawAllocationOrder(), llvm::TargetLowering::getRegForInlineAsmConstraint(), GetRegistersForValue(), llvm::RegScavenger::getRegsAvailable(), and llvm::ARMBaseRegisterInfo::getReservedRegs().
| bool llvm::TargetRegisterClass::contains | ( | unsigned | Reg | ) | const [inline] |
contains - Return true if the specified register is included in this register class. This does not include virtual registers.
Definition at line 76 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::contains(), and MC.
Referenced by llvm::MachineFunction::addLiveIn(), canFoldCopy(), llvm::SystemZInstrInfo::convertToThreeAddress(), copyHint(), llvm::PPCInstrInfo::DefinesPredicate(), llvm::AMDGPUInstrInfo::getIndirectIndexBegin(), llvm::TargetRegisterInfo::getMinimalPhysRegClass(), llvm::PPCInstrInfo::insertSelect(), llvm::CoalescerPair::setRegisters(), UpdateOperandRegClass(), and llvm::SIInstrInfo::verifyInstruction().
| bool llvm::TargetRegisterClass::contains | ( | unsigned | Reg1, |
| unsigned | Reg2 | ||
| ) | const [inline] |
contains - Return true if both registers are in this class.
Definition at line 81 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::contains(), and MC.
| iterator llvm::TargetRegisterClass::end | ( | ) | const [inline] |
Definition at line 62 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::end(), and MC.
Referenced by llvm::PPCInstrInfo::DefinesPredicate(), llvm::RegScavenger::FindUnusedReg(), findUnusedVGPR(), llvm::TargetLowering::getRegForInlineAsmConstraint(), GetRegistersForValue(), llvm::RegScavenger::getRegsAvailable(), and llvm::ARMBaseRegisterInfo::getReservedRegs().
| unsigned llvm::TargetRegisterClass::getAlignment | ( | ) | const [inline] |
getAlignment - Return the minimum required alignment for a register of this class.
Definition at line 91 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::getAlignment(), and MC.
Referenced by llvm::PPCFrameLowering::addScavengingSpillSlot(), llvm::X86FrameLowering::assignCalleeSavedSpillSlots(), llvm::XCoreFunctionInfo::createEHSpillSlot(), llvm::XCoreFunctionInfo::createFPSpillSlot(), llvm::XCoreFunctionInfo::createLRSpillSlot(), llvm::MipsFunctionInfo::getMoveF64ViaSpillFI(), llvm::MipsSEFrameLowering::processFunctionBeforeCalleeSavedScan(), llvm::ARMFrameLowering::processFunctionBeforeCalleeSavedScan(), llvm::AArch64FrameLowering::processFunctionBeforeCalleeSavedScan(), and llvm::XCoreFrameLowering::processFunctionBeforeFrameFinalized().
| int llvm::TargetRegisterClass::getCopyCost | ( | ) | const [inline] |
getCopyCost - Return the cost of copying a value between two registers in this class. A negative number means the register class is very expensive to copy e.g. status flag register classes.
Definition at line 96 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::getCopyCost(), and MC.
Referenced by CheckForPhysRegDependency().
| unsigned llvm::TargetRegisterClass::getID | ( | ) | const [inline] |
getID() - Return the register class ID number.
Definition at line 53 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::getID(), and MC.
Referenced by llvm::ARMBaseRegisterInfo::avoidWriteAfterWrite(), GetCostForDef(), llvm::ARMBaseRegisterInfo::getLargestLegalSuperClass(), llvm::PPCRegisterInfo::getRegPressureLimit(), llvm::MipsRegisterInfo::getRegPressureLimit(), llvm::AArch64RegisterInfo::getRegPressureLimit(), llvm::ARMBaseRegisterInfo::getRegPressureLimit(), hasSubClassEq(), INITIALIZE_PASS(), llvm::ResourcePriorityQueue::rawRegPressureDelta(), llvm::SIRegisterInfo::regClassCanUseImmediate(), llvm::ResourcePriorityQueue::regPressureDelta(), and llvm::ResourcePriorityQueue::scheduledNode().
| const char* llvm::TargetRegisterClass::getName | ( | ) | const [inline] |
getName() - Return the register class name for debugging.
Definition at line 57 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::getName(), and MC.
Referenced by llvm::RegAllocBase::allocatePhysRegs(), llvm::LiveRangeEdit::calculateRegClassAndHint(), llvm::LiveStacks::print(), llvm::VirtRegMap::print(), and llvm::MachineInstr::print().
| unsigned llvm::TargetRegisterClass::getNumRegs | ( | ) | const [inline] |
getNumRegs - Return the number of registers in this class.
Definition at line 66 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::getNumRegs(), and MC.
Referenced by llvm::RegisterClassInfo::computePSetLimit(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::AMDGPUInstrInfo::getIndirectIndexBegin(), getRawAllocationOrder(), and llvm::SIRegisterInfo::getRegPressureLimit().
| ArrayRef<MCPhysReg> llvm::TargetRegisterClass::getRawAllocationOrder | ( | const MachineFunction & | MF | ) | const [inline] |
getRawAllocationOrder - Returns the preferred order for allocating registers from this register class in MF. The raw order comes directly from the .td file and may include reserved registers that are not allocatable. Register allocators should also make sure to allocate callee-saved registers only after all the volatiles are used. The RegisterClassInfo class provides filtered allocation orders with callee-saved registers moved to the end.
The MachineFunction argument can be used to tune the allocatable registers based on the characteristics of the function, subtarget, or other criteria.
By default, this method returns all registers in the class.
Definition at line 194 of file TargetRegisterInfo.h.
References begin(), getNumRegs(), llvm::makeArrayRef(), and OrderFunc.
Referenced by llvm::PBQPBuilder::build(), and getAllocatableSetForRC().
| unsigned llvm::TargetRegisterClass::getRegister | ( | unsigned | i | ) | const [inline] |
getRegister - Return the specified register in the class.
Definition at line 70 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::getRegister(), and MC.
Referenced by llvm::AMDGPUInstrInfo::expandPostRAPseudo(), llvm::AMDGPUInstrInfo::getIndirectIndexBegin(), and llvm::SIRegisterInfo::getPhysRegSubReg().
| unsigned llvm::TargetRegisterClass::getSize | ( | ) | const [inline] |
getSize - Return the size of the register in bytes, which is also the size of a stack slot allocated to hold a spilled copy of this register.
Definition at line 87 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::getSize(), and MC.
Referenced by llvm::PPCFrameLowering::addScavengingSpillSlot(), llvm::X86FrameLowering::assignCalleeSavedSpillSlots(), llvm::XCoreFunctionInfo::createEHSpillSlot(), llvm::XCoreFunctionInfo::createFPSpillSlot(), llvm::XCoreFunctionInfo::createLRSpillSlot(), llvm::MipsFrameLowering::estimateStackSize(), llvm::TargetLoweringBase::findRepresentativeClass(), llvm::TargetRegisterInfo::getCommonSuperRegClass(), llvm::SIInstrInfo::getLdStBaseRegImmOfs(), getLoadStoreRegOpcode(), llvm::MipsFunctionInfo::getMoveF64ViaSpillFI(), llvm::TargetInstrInfo::getStackSlotRange(), llvm::SIInstrInfo::loadRegFromStackSlot(), llvm::AArch64InstrInfo::loadRegFromStackSlot(), llvm::ARMBaseInstrInfo::loadRegFromStackSlot(), llvm::MipsSEFrameLowering::processFunctionBeforeCalleeSavedScan(), llvm::ARMFrameLowering::processFunctionBeforeCalleeSavedScan(), llvm::AArch64FrameLowering::processFunctionBeforeCalleeSavedScan(), llvm::XCoreFrameLowering::processFunctionBeforeFrameFinalized(), llvm::ARMBaseRegisterInfo::shouldCoalesce(), llvm::SIInstrInfo::splitSMRD(), llvm::SIInstrInfo::storeRegToStackSlot(), llvm::AArch64InstrInfo::storeRegToStackSlot(), and llvm::ARMBaseInstrInfo::storeRegToStackSlot().
| const uint32_t* llvm::TargetRegisterClass::getSubClassMask | ( | ) | const [inline] |
getSubClassMask - Returns a bit vector of subclasses, including this one. The vector is indexed by class IDs, see hasSubClassEq() above for how to use it.
Definition at line 151 of file TargetRegisterInfo.h.
References SubClassMask.
Referenced by llvm::TargetRegisterInfo::getAllocatableClass(), llvm::TargetRegisterInfo::getCommonSubClass(), and llvm::TargetRegisterInfo::getMatchingSuperRegClass().
| sc_iterator llvm::TargetRegisterClass::getSuperClasses | ( | ) | const [inline] |
getSuperClasses - Returns a NULL terminated list of super-classes. The classes are ordered by ID which is also a topological ordering from large to small classes. The list does NOT include the current class.
Definition at line 170 of file TargetRegisterInfo.h.
References SuperClasses.
Referenced by llvm::ARMBaseRegisterInfo::getLargestLegalSuperClass().
| const uint16_t* llvm::TargetRegisterClass::getSuperRegIndices | ( | ) | const [inline] |
getSuperRegIndices - Returns a 0-terminated list of sub-register indices that project some super-register class into this register class. The list has an entry for each Idx such that:
There exists SuperRC where: For all Reg in SuperRC: this->contains(Reg:Idx)
Definition at line 163 of file TargetRegisterInfo.h.
References SuperRegIndices.
| bool llvm::TargetRegisterClass::hasSubClass | ( | const TargetRegisterClass * | RC | ) | const [inline] |
hasSubClass - return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.
Definition at line 125 of file TargetRegisterInfo.h.
References hasSubClassEq().
Referenced by llvm::TargetRegisterInfo::getMinimalPhysRegClass(), and hasSuperClass().
| bool llvm::TargetRegisterClass::hasSubClassEq | ( | const TargetRegisterClass * | RC | ) | const [inline] |
hasSubClassEq - Returns true if RC is a sub-class of or equal to this class.
Definition at line 131 of file TargetRegisterInfo.h.
References getID(), and SubClassMask.
Referenced by llvm::MachineFunction::addLiveIn(), canFoldCopy(), hasSubClass(), hasSuperClassEq(), and UpdateOperandRegClass().
| bool llvm::TargetRegisterClass::hasSuperClass | ( | const TargetRegisterClass * | RC | ) | const [inline] |
hasSuperClass - return true if the specified TargetRegisterClass is a proper super-class of this TargetRegisterClass.
Definition at line 138 of file TargetRegisterInfo.h.
References hasSubClass().
| bool llvm::TargetRegisterClass::hasSuperClassEq | ( | const TargetRegisterClass * | RC | ) | const [inline] |
hasSuperClassEq - Returns true if RC is a super-class of or equal to this class.
Definition at line 144 of file TargetRegisterInfo.h.
References hasSubClassEq().
Referenced by llvm::PPCInstrInfo::getOperandLatency(), isFPR64(), and isGPR64().
| bool llvm::TargetRegisterClass::hasType | ( | EVT | vt | ) | const [inline] |
hasType - return true if this TargetRegisterClass has the ValueType vt.
Definition at line 104 of file TargetRegisterInfo.h.
References llvm::MVT::Other, and VTs.
Referenced by llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::TargetRegisterInfo::getMinimalPhysRegClass(), llvm::TargetLowering::getRegForInlineAsmConstraint(), llvm::MipsSEInstrInfo::loadRegFromStack(), and llvm::MipsSEInstrInfo::storeRegToStack().
| bool llvm::TargetRegisterClass::isAllocatable | ( | ) | const [inline] |
isAllocatable - Return true if this register class may be used to create virtual registers.
Definition at line 100 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::isAllocatable(), and MC.
Referenced by llvm::MachineRegisterInfo::createVirtualRegister(), llvm::TargetRegisterInfo::getAllocatableClass(), getAllocatableSetForRC(), and llvm::MachineRegisterInfo::setRegClass().
| bool llvm::TargetRegisterClass::isASubClass | ( | ) | const [inline] |
isASubClass - return true if this TargetRegisterClass is a subset class of at least one other TargetRegisterClass.
Definition at line 176 of file TargetRegisterInfo.h.
References SuperClasses.
| vt_iterator llvm::TargetRegisterClass::vt_begin | ( | ) | const [inline] |
vt_begin / vt_end - Loop over all of the value types that can be represented by values in this register class.
Definition at line 113 of file TargetRegisterInfo.h.
References VTs.
Referenced by GetRegistersForValue(), getRegTy(), and llvm::TargetLoweringBase::isLegalRC().
| vt_iterator llvm::TargetRegisterClass::vt_end | ( | ) | const [inline] |
Definition at line 117 of file TargetRegisterInfo.h.
References I, llvm::MVT::Other, and VTs.
Referenced by getRegTy(), and llvm::TargetLoweringBase::isLegalRC().
Member Data Documentation
Definition at line 44 of file TargetRegisterInfo.h.
Referenced by begin(), contains(), end(), getAlignment(), getCopyCost(), getID(), llvm::TargetRegisterInfo::getMatchingSuperReg(), getName(), getNumRegs(), getRegister(), getSize(), and isAllocatable().
Definition at line 49 of file TargetRegisterInfo.h.
Referenced by getRawAllocationOrder().
| const uint32_t* llvm::TargetRegisterClass::SubClassMask |
Definition at line 46 of file TargetRegisterInfo.h.
Referenced by getSubClassMask(), and hasSubClassEq().
Definition at line 48 of file TargetRegisterInfo.h.
Referenced by getSuperClasses(), and isASubClass().
Definition at line 47 of file TargetRegisterInfo.h.
Referenced by getSuperRegIndices().
Definition at line 45 of file TargetRegisterInfo.h.
Referenced by hasType(), vt_begin(), and vt_end().
The documentation for this class was generated from the following file:
1.7.6.1