LLVM API Documentation
00001 //===-- SystemZDisassembler.cpp - Disassembler for SystemZ ------*- C++ -*-===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file is distributed under the University of Illinois Open Source 00006 // License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 00010 #include "SystemZ.h" 00011 #include "llvm/MC/MCDisassembler.h" 00012 #include "llvm/MC/MCFixedLenDisassembler.h" 00013 #include "llvm/MC/MCInst.h" 00014 #include "llvm/MC/MCSubtargetInfo.h" 00015 #include "llvm/Support/MemoryObject.h" 00016 #include "llvm/Support/TargetRegistry.h" 00017 00018 using namespace llvm; 00019 00020 #define DEBUG_TYPE "systemz-disassembler" 00021 00022 typedef MCDisassembler::DecodeStatus DecodeStatus; 00023 00024 namespace { 00025 class SystemZDisassembler : public MCDisassembler { 00026 public: 00027 SystemZDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) 00028 : MCDisassembler(STI, Ctx) {} 00029 virtual ~SystemZDisassembler() {} 00030 00031 // Override MCDisassembler. 00032 DecodeStatus getInstruction(MCInst &instr, uint64_t &size, 00033 const MemoryObject ®ion, uint64_t address, 00034 raw_ostream &vStream, 00035 raw_ostream &cStream) const override; 00036 }; 00037 } // end anonymous namespace 00038 00039 static MCDisassembler *createSystemZDisassembler(const Target &T, 00040 const MCSubtargetInfo &STI, 00041 MCContext &Ctx) { 00042 return new SystemZDisassembler(STI, Ctx); 00043 } 00044 00045 extern "C" void LLVMInitializeSystemZDisassembler() { 00046 // Register the disassembler. 00047 TargetRegistry::RegisterMCDisassembler(TheSystemZTarget, 00048 createSystemZDisassembler); 00049 } 00050 00051 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, 00052 const unsigned *Regs) { 00053 assert(RegNo < 16 && "Invalid register"); 00054 RegNo = Regs[RegNo]; 00055 if (RegNo == 0) 00056 return MCDisassembler::Fail; 00057 Inst.addOperand(MCOperand::CreateReg(RegNo)); 00058 return MCDisassembler::Success; 00059 } 00060 00061 static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, 00062 uint64_t Address, 00063 const void *Decoder) { 00064 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs); 00065 } 00066 00067 static DecodeStatus DecodeGRH32BitRegisterClass(MCInst &Inst, uint64_t RegNo, 00068 uint64_t Address, 00069 const void *Decoder) { 00070 return decodeRegisterClass(Inst, RegNo, SystemZMC::GRH32Regs); 00071 } 00072 00073 static DecodeStatus DecodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, 00074 uint64_t Address, 00075 const void *Decoder) { 00076 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs); 00077 } 00078 00079 static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo, 00080 uint64_t Address, 00081 const void *Decoder) { 00082 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR128Regs); 00083 } 00084 00085 static DecodeStatus DecodeADDR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, 00086 uint64_t Address, 00087 const void *Decoder) { 00088 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs); 00089 } 00090 00091 static DecodeStatus DecodeFP32BitRegisterClass(MCInst &Inst, uint64_t RegNo, 00092 uint64_t Address, 00093 const void *Decoder) { 00094 return decodeRegisterClass(Inst, RegNo, SystemZMC::FP32Regs); 00095 } 00096 00097 static DecodeStatus DecodeFP64BitRegisterClass(MCInst &Inst, uint64_t RegNo, 00098 uint64_t Address, 00099 const void *Decoder) { 00100 return decodeRegisterClass(Inst, RegNo, SystemZMC::FP64Regs); 00101 } 00102 00103 static DecodeStatus DecodeFP128BitRegisterClass(MCInst &Inst, uint64_t RegNo, 00104 uint64_t Address, 00105 const void *Decoder) { 00106 return decodeRegisterClass(Inst, RegNo, SystemZMC::FP128Regs); 00107 } 00108 00109 template<unsigned N> 00110 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) { 00111 assert(isUInt<N>(Imm) && "Invalid immediate"); 00112 Inst.addOperand(MCOperand::CreateImm(Imm)); 00113 return MCDisassembler::Success; 00114 } 00115 00116 template<unsigned N> 00117 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm) { 00118 assert(isUInt<N>(Imm) && "Invalid immediate"); 00119 Inst.addOperand(MCOperand::CreateImm(SignExtend64<N>(Imm))); 00120 return MCDisassembler::Success; 00121 } 00122 00123 static DecodeStatus decodeAccessRegOperand(MCInst &Inst, uint64_t Imm, 00124 uint64_t Address, 00125 const void *Decoder) { 00126 return decodeUImmOperand<4>(Inst, Imm); 00127 } 00128 00129 static DecodeStatus decodeU4ImmOperand(MCInst &Inst, uint64_t Imm, 00130 uint64_t Address, const void *Decoder) { 00131 return decodeUImmOperand<4>(Inst, Imm); 00132 } 00133 00134 static DecodeStatus decodeU6ImmOperand(MCInst &Inst, uint64_t Imm, 00135 uint64_t Address, const void *Decoder) { 00136 return decodeUImmOperand<6>(Inst, Imm); 00137 } 00138 00139 static DecodeStatus decodeU8ImmOperand(MCInst &Inst, uint64_t Imm, 00140 uint64_t Address, const void *Decoder) { 00141 return decodeUImmOperand<8>(Inst, Imm); 00142 } 00143 00144 static DecodeStatus decodeU16ImmOperand(MCInst &Inst, uint64_t Imm, 00145 uint64_t Address, const void *Decoder) { 00146 return decodeUImmOperand<16>(Inst, Imm); 00147 } 00148 00149 static DecodeStatus decodeU32ImmOperand(MCInst &Inst, uint64_t Imm, 00150 uint64_t Address, const void *Decoder) { 00151 return decodeUImmOperand<32>(Inst, Imm); 00152 } 00153 00154 static DecodeStatus decodeS8ImmOperand(MCInst &Inst, uint64_t Imm, 00155 uint64_t Address, const void *Decoder) { 00156 return decodeSImmOperand<8>(Inst, Imm); 00157 } 00158 00159 static DecodeStatus decodeS16ImmOperand(MCInst &Inst, uint64_t Imm, 00160 uint64_t Address, const void *Decoder) { 00161 return decodeSImmOperand<16>(Inst, Imm); 00162 } 00163 00164 static DecodeStatus decodeS32ImmOperand(MCInst &Inst, uint64_t Imm, 00165 uint64_t Address, const void *Decoder) { 00166 return decodeSImmOperand<32>(Inst, Imm); 00167 } 00168 00169 template<unsigned N> 00170 static DecodeStatus decodePCDBLOperand(MCInst &Inst, uint64_t Imm, 00171 uint64_t Address) { 00172 assert(isUInt<N>(Imm) && "Invalid PC-relative offset"); 00173 Inst.addOperand(MCOperand::CreateImm(SignExtend64<N>(Imm) * 2 + Address)); 00174 return MCDisassembler::Success; 00175 } 00176 00177 static DecodeStatus decodePC16DBLOperand(MCInst &Inst, uint64_t Imm, 00178 uint64_t Address, 00179 const void *Decoder) { 00180 return decodePCDBLOperand<16>(Inst, Imm, Address); 00181 } 00182 00183 static DecodeStatus decodePC32DBLOperand(MCInst &Inst, uint64_t Imm, 00184 uint64_t Address, 00185 const void *Decoder) { 00186 return decodePCDBLOperand<32>(Inst, Imm, Address); 00187 } 00188 00189 static DecodeStatus decodeBDAddr12Operand(MCInst &Inst, uint64_t Field, 00190 const unsigned *Regs) { 00191 uint64_t Base = Field >> 12; 00192 uint64_t Disp = Field & 0xfff; 00193 assert(Base < 16 && "Invalid BDAddr12"); 00194 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); 00195 Inst.addOperand(MCOperand::CreateImm(Disp)); 00196 return MCDisassembler::Success; 00197 } 00198 00199 static DecodeStatus decodeBDAddr20Operand(MCInst &Inst, uint64_t Field, 00200 const unsigned *Regs) { 00201 uint64_t Base = Field >> 20; 00202 uint64_t Disp = ((Field << 12) & 0xff000) | ((Field >> 8) & 0xfff); 00203 assert(Base < 16 && "Invalid BDAddr20"); 00204 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); 00205 Inst.addOperand(MCOperand::CreateImm(SignExtend64<20>(Disp))); 00206 return MCDisassembler::Success; 00207 } 00208 00209 static DecodeStatus decodeBDXAddr12Operand(MCInst &Inst, uint64_t Field, 00210 const unsigned *Regs) { 00211 uint64_t Index = Field >> 16; 00212 uint64_t Base = (Field >> 12) & 0xf; 00213 uint64_t Disp = Field & 0xfff; 00214 assert(Index < 16 && "Invalid BDXAddr12"); 00215 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); 00216 Inst.addOperand(MCOperand::CreateImm(Disp)); 00217 Inst.addOperand(MCOperand::CreateReg(Index == 0 ? 0 : Regs[Index])); 00218 return MCDisassembler::Success; 00219 } 00220 00221 static DecodeStatus decodeBDXAddr20Operand(MCInst &Inst, uint64_t Field, 00222 const unsigned *Regs) { 00223 uint64_t Index = Field >> 24; 00224 uint64_t Base = (Field >> 20) & 0xf; 00225 uint64_t Disp = ((Field & 0xfff00) >> 8) | ((Field & 0xff) << 12); 00226 assert(Index < 16 && "Invalid BDXAddr20"); 00227 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); 00228 Inst.addOperand(MCOperand::CreateImm(SignExtend64<20>(Disp))); 00229 Inst.addOperand(MCOperand::CreateReg(Index == 0 ? 0 : Regs[Index])); 00230 return MCDisassembler::Success; 00231 } 00232 00233 static DecodeStatus decodeBDLAddr12Len8Operand(MCInst &Inst, uint64_t Field, 00234 const unsigned *Regs) { 00235 uint64_t Length = Field >> 16; 00236 uint64_t Base = (Field >> 12) & 0xf; 00237 uint64_t Disp = Field & 0xfff; 00238 assert(Length < 256 && "Invalid BDLAddr12Len8"); 00239 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); 00240 Inst.addOperand(MCOperand::CreateImm(Disp)); 00241 Inst.addOperand(MCOperand::CreateImm(Length + 1)); 00242 return MCDisassembler::Success; 00243 } 00244 00245 static DecodeStatus decodeBDAddr32Disp12Operand(MCInst &Inst, uint64_t Field, 00246 uint64_t Address, 00247 const void *Decoder) { 00248 return decodeBDAddr12Operand(Inst, Field, SystemZMC::GR32Regs); 00249 } 00250 00251 static DecodeStatus decodeBDAddr32Disp20Operand(MCInst &Inst, uint64_t Field, 00252 uint64_t Address, 00253 const void *Decoder) { 00254 return decodeBDAddr20Operand(Inst, Field, SystemZMC::GR32Regs); 00255 } 00256 00257 static DecodeStatus decodeBDAddr64Disp12Operand(MCInst &Inst, uint64_t Field, 00258 uint64_t Address, 00259 const void *Decoder) { 00260 return decodeBDAddr12Operand(Inst, Field, SystemZMC::GR64Regs); 00261 } 00262 00263 static DecodeStatus decodeBDAddr64Disp20Operand(MCInst &Inst, uint64_t Field, 00264 uint64_t Address, 00265 const void *Decoder) { 00266 return decodeBDAddr20Operand(Inst, Field, SystemZMC::GR64Regs); 00267 } 00268 00269 static DecodeStatus decodeBDXAddr64Disp12Operand(MCInst &Inst, uint64_t Field, 00270 uint64_t Address, 00271 const void *Decoder) { 00272 return decodeBDXAddr12Operand(Inst, Field, SystemZMC::GR64Regs); 00273 } 00274 00275 static DecodeStatus decodeBDXAddr64Disp20Operand(MCInst &Inst, uint64_t Field, 00276 uint64_t Address, 00277 const void *Decoder) { 00278 return decodeBDXAddr20Operand(Inst, Field, SystemZMC::GR64Regs); 00279 } 00280 00281 static DecodeStatus decodeBDLAddr64Disp12Len8Operand(MCInst &Inst, 00282 uint64_t Field, 00283 uint64_t Address, 00284 const void *Decoder) { 00285 return decodeBDLAddr12Len8Operand(Inst, Field, SystemZMC::GR64Regs); 00286 } 00287 00288 #include "SystemZGenDisassemblerTables.inc" 00289 00290 DecodeStatus SystemZDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 00291 const MemoryObject &Region, 00292 uint64_t Address, 00293 raw_ostream &os, 00294 raw_ostream &cs) const { 00295 // Get the first two bytes of the instruction. 00296 uint8_t Bytes[6]; 00297 Size = 0; 00298 if (Region.readBytes(Address, 2, Bytes) == -1) 00299 return MCDisassembler::Fail; 00300 00301 // The top 2 bits of the first byte specify the size. 00302 const uint8_t *Table; 00303 if (Bytes[0] < 0x40) { 00304 Size = 2; 00305 Table = DecoderTable16; 00306 } else if (Bytes[0] < 0xc0) { 00307 Size = 4; 00308 Table = DecoderTable32; 00309 } else { 00310 Size = 6; 00311 Table = DecoderTable48; 00312 } 00313 00314 // Read any remaining bytes. 00315 if (Size > 2 && Region.readBytes(Address + 2, Size - 2, Bytes + 2) == -1) 00316 return MCDisassembler::Fail; 00317 00318 // Construct the instruction. 00319 uint64_t Inst = 0; 00320 for (uint64_t I = 0; I < Size; ++I) 00321 Inst = (Inst << 8) | Bytes[I]; 00322 00323 return decodeInstruction(Table, MI, Inst, Address, this, STI); 00324 }