llvm::SIInstrInfo Member List

This is the complete list of members for llvm::SIInstrInfo, including all inherited members.

AMDGPUInstrInfo(const AMDGPUSubtarget &st)	llvm::AMDGPUInstrInfo	[explicit]
areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override	llvm::SIInstrInfo
buildIndirectRead(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const override	llvm::SIInstrInfo	[virtual]
buildIndirectWrite(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const override	llvm::SIInstrInfo	[virtual]
buildMovInstr(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const override	llvm::SIInstrInfo	[virtual]
calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const override	llvm::SIInstrInfo	[virtual]
canFoldMemoryOperand(const MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops) const override	llvm::AMDGPUInstrInfo
canFoldOffset(unsigned OffsetSize, unsigned AS) LLVM_READNONE	llvm::SIInstrInfo	[static]
canReadVGPR(const MachineInstr &MI, unsigned OpNo) const	llvm::SIInstrInfo
commuteInstruction(MachineInstr *MI, bool NewMI=false) const override	llvm::SIInstrInfo
commuteOpcode(unsigned Opcode) const	llvm::SIInstrInfo
convertToThreeAddress(MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const override	llvm::AMDGPUInstrInfo
copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override	llvm::SIInstrInfo
DefinesPredicate(MachineInstr *MI, std::vector< MachineOperand > &Pred) const override	llvm::AMDGPUInstrInfo
enableClusterLoads() const override	llvm::AMDGPUInstrInfo
expandPostRAPseudo(MachineBasicBlock::iterator MI) const override	llvm::SIInstrInfo
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops, int FrameIndex) const override	llvm::AMDGPUInstrInfo	[protected]
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops, MachineInstr *LoadMI) const override	llvm::AMDGPUInstrInfo	[protected]
getIndirectAddrRegClass() const override	llvm::SIInstrInfo	[virtual]
getIndirectIndexBegin(const MachineFunction &MF) const	llvm::AMDGPUInstrInfo
getIndirectIndexEnd(const MachineFunction &MF) const	llvm::AMDGPUInstrInfo
getLdStBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg, unsigned &Offset, const TargetRegisterInfo *TRI) const final	llvm::SIInstrInfo
getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const	llvm::AMDGPUInstrInfo
getNamedOperand(MachineInstr &MI, unsigned OperandName) const	llvm::SIInstrInfo
getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const override	llvm::AMDGPUInstrInfo
getOpRegClass(const MachineInstr &MI, unsigned OpNo) const	llvm::SIInstrInfo
getRegisterInfo() const override	llvm::SIInstrInfo	[inline, virtual]
getVALUOp(const MachineInstr &MI)	llvm::SIInstrInfo	[static]
hasLoadFromStackSlot(const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const override	llvm::AMDGPUInstrInfo
hasModifiers(unsigned Opcode) const	llvm::SIInstrInfo
hasStoreFromStackSlot(const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const	llvm::AMDGPUInstrInfo
hasVALU32BitEncoding(unsigned Opcode) const	llvm::SIInstrInfo
insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override	llvm::AMDGPUInstrInfo
insertNOPs(MachineBasicBlock::iterator MI, int Count) const	llvm::SIInstrInfo
isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override	llvm::AMDGPUInstrInfo
isDS(uint16_t Opcode) const	llvm::SIInstrInfo
isFLAT(uint16_t Opcode) const	llvm::SIInstrInfo
isImmOperandLegal(const MachineInstr *MI, unsigned OpNo, const MachineOperand &MO) const	llvm::SIInstrInfo
isInlineConstant(const APInt &Imm) const	llvm::SIInstrInfo
isInlineConstant(const MachineOperand &MO) const	llvm::SIInstrInfo
isLiteralConstant(const MachineOperand &MO) const	llvm::SIInstrInfo
isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const override	llvm::AMDGPUInstrInfo
isLoadFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const override	llvm::AMDGPUInstrInfo
isMIMG(uint16_t Opcode) const	llvm::SIInstrInfo
isMov(unsigned Opcode) const override	llvm::SIInstrInfo	[virtual]
isMTBUF(uint16_t Opcode) const	llvm::SIInstrInfo
isMUBUF(uint16_t Opcode) const	llvm::SIInstrInfo
isOperandLegal(const MachineInstr *MI, unsigned OpIdx, const MachineOperand *MO=nullptr) const	llvm::SIInstrInfo
isPredicable(MachineInstr *MI) const override	llvm::AMDGPUInstrInfo
isPredicated(const MachineInstr *MI) const override	llvm::AMDGPUInstrInfo
isRegisterLoad(const MachineInstr &MI) const	llvm::AMDGPUInstrInfo
isRegisterStore(const MachineInstr &MI) const	llvm::AMDGPUInstrInfo
isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override	llvm::SIInstrInfo
isSALUInstr(const MachineInstr &MI) const	llvm::SIInstrInfo
isSALUOpSupportedOnVALU(const MachineInstr &MI) const	llvm::SIInstrInfo
isSMRD(uint16_t Opcode) const	llvm::SIInstrInfo
isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const	llvm::AMDGPUInstrInfo
isStoreFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const	llvm::AMDGPUInstrInfo
isTriviallyReMaterializable(const MachineInstr *MI, AliasAnalysis *AA=nullptr) const	llvm::SIInstrInfo
isVOP1(uint16_t Opcode) const	llvm::SIInstrInfo
isVOP2(uint16_t Opcode) const	llvm::SIInstrInfo
isVOP3(uint16_t Opcode) const	llvm::SIInstrInfo
isVOPC(uint16_t Opcode) const	llvm::SIInstrInfo
legalizeOperands(MachineInstr *MI) const	llvm::SIInstrInfo
legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const	llvm::SIInstrInfo
LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I, unsigned SavReg, unsigned IndexReg) const	llvm::SIInstrInfo
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override	llvm::SIInstrInfo
moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const	llvm::SIInstrInfo
moveToVALU(MachineInstr &MI) const	llvm::SIInstrInfo
reserveIndirectRegisters(BitVector &Reserved, const MachineFunction &MF) const	llvm::SIInstrInfo
ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override	llvm::AMDGPUInstrInfo
shouldClusterLoads(MachineInstr *FirstLdSt, MachineInstr *SecondLdSt, unsigned NumLoads) const final	llvm::SIInstrInfo
shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override	llvm::AMDGPUInstrInfo
SIInstrInfo(const AMDGPUSubtarget &st)	llvm::SIInstrInfo	[explicit]
splitSMRD(MachineInstr *MI, const TargetRegisterClass *HalfRC, unsigned HalfImmOp, unsigned HalfSGPROp, MachineInstr *&Lo, MachineInstr *&Hi) const	llvm::SIInstrInfo
ST	llvm::AMDGPUInstrInfo	[protected]
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override	llvm::SIInstrInfo
SubsumesPredicate(const SmallVectorImpl< MachineOperand > &Pred1, const SmallVectorImpl< MachineOperand > &Pred2) const override	llvm::AMDGPUInstrInfo
unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const override	llvm::AMDGPUInstrInfo
unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode * > &NewNodes) const override	llvm::AMDGPUInstrInfo
verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const override	llvm::SIInstrInfo