LLVM API Documentation

llvm::SystemZTargetLowering Member List
This is the complete list of members for llvm::SystemZTargetLowering, including all inherited members.
addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth)llvm::TargetLoweringBase [inline, protected]
AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)llvm::TargetLoweringBase [inline, protected]
addRegisterClass(MVT VT, const TargetRegisterClass *RC)llvm::TargetLoweringBase [inline, protected]
AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const llvm::TargetLowering [virtual]
allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align, bool *Fast) const overridellvm::SystemZTargetLowering [virtual]
allowTruncateForTailCall(Type *, Type *) const overridellvm::SystemZTargetLowering [virtual]
ArgListTy typedefllvm::TargetLowering
AsmOperandInfoVector typedefllvm::TargetLowering
BooleanContent enum namellvm::TargetLoweringBase
BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl, SelectionDAG &DAG) const llvm::TargetLowering
BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const llvm::TargetLowering
BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, std::vector< SDNode * > *Created) const llvm::TargetLowering [inline, virtual]
BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const llvm::TargetLowering
C_Memory enum valuellvm::TargetLowering
C_Other enum valuellvm::TargetLowering
C_Register enum valuellvm::TargetLowering
C_RegisterClass enum valuellvm::TargetLowering
C_Unknown enum valuellvm::TargetLowering
CanLowerReturn(CallingConv::ID, MachineFunction &, bool, const SmallVectorImpl< ISD::OutputArg > &, LLVMContext &) const llvm::TargetLowering [inline, virtual]
canOpTrap(unsigned Op, EVT VT) const llvm::TargetLoweringBase [virtual]
clearOperationActions()llvm::TargetLoweringBase [inline, protected]
clearRegisterClasses()llvm::TargetLoweringBase [inline, protected]
ComputeConstraintToUse(AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const llvm::TargetLowering [virtual]
computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const llvm::TargetLowering [virtual]
ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG, unsigned Depth=0) const llvm::TargetLowering [virtual]
computeRegisterProperties()llvm::TargetLoweringBase [protected]
ConstraintType enum namellvm::TargetLowering
ConstraintWeight enum namellvm::TargetLowering
createFastISel(FunctionLoweringInfo &, const TargetLibraryInfo *) const llvm::TargetLowering [inline, virtual]
Custom enum valuellvm::TargetLoweringBase
CW_Best enum valuellvm::TargetLowering
CW_Better enum valuellvm::TargetLowering
CW_Constant enum valuellvm::TargetLowering
CW_Default enum valuellvm::TargetLowering
CW_Good enum valuellvm::TargetLowering
CW_Invalid enum valuellvm::TargetLowering
CW_Memory enum valuellvm::TargetLowering
CW_Okay enum valuellvm::TargetLowering
CW_Register enum valuellvm::TargetLowering
CW_SpecificReg enum valuellvm::TargetLowering
EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) const overridellvm::SystemZTargetLowering [virtual]
emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord, bool IsStore, bool IsLoad) const llvm::TargetLoweringBase [inline, virtual]
emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const llvm::TargetLoweringBase [inline, virtual]
emitPatchPoint(MachineInstr *MI, MachineBasicBlock *MBB) const llvm::TargetLoweringBase [protected]
emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const llvm::TargetLoweringBase [inline, virtual]
emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord, bool IsStore, bool IsLoad) const llvm::TargetLoweringBase [inline, virtual]
Expand enum valuellvm::TargetLoweringBase
expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const llvm::TargetLowering
ExpandInlineAsm(CallInst *) const llvm::TargetLowering [inline, virtual]
expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const llvm::TargetLowering
findRepresentativeClass(MVT VT) const llvm::TargetLoweringBase [protected, virtual]
functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const llvm::TargetLowering [inline, virtual]
GetAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value * > &, Type *&) const llvm::TargetLoweringBase [inline, virtual]
getBooleanContents(bool isVec, bool isFloat) const llvm::TargetLoweringBase [inline]
getBooleanContents(EVT Type) const llvm::TargetLoweringBase [inline]
getBypassSlowDivWidths() const llvm::TargetLoweringBase [inline]
getByValTypeAlignment(Type *Ty) const llvm::TargetLoweringBase [virtual]
getClearCacheBuiltinName() const llvm::TargetLowering [inline, virtual]
getCmpLibcallCC(RTLIB::Libcall Call) const llvm::TargetLoweringBase [inline]
getCmpLibcallReturnType() const llvm::TargetLoweringBase [virtual]
getCondCodeAction(ISD::CondCode CC, MVT VT) const llvm::TargetLoweringBase [inline]
getConstraintType(const std::string &Constraint) const overridellvm::SystemZTargetLowering [virtual]
getDataLayout() const llvm::TargetLoweringBase [inline]
getExceptionPointerRegister() const llvm::TargetLoweringBase [inline]
getExceptionSelectorRegister() const llvm::TargetLoweringBase [inline]
getExtendForContent(BooleanContent Content)llvm::TargetLoweringBase [inline, static]
getIndexedLoadAction(unsigned IdxMode, MVT VT) const llvm::TargetLoweringBase [inline]
getIndexedStoreAction(unsigned IdxMode, MVT VT) const llvm::TargetLoweringBase [inline]
getInsertFencesForAtomic() const llvm::TargetLoweringBase [inline]
getJumpBufAlignment() const llvm::TargetLoweringBase [inline]
getJumpBufSize() const llvm::TargetLoweringBase [inline]
getJumpTableEncoding() const llvm::TargetLowering [virtual]
getLibcallCallingConv(RTLIB::Libcall Call) const llvm::TargetLoweringBase [inline]
getLibcallName(RTLIB::Libcall Call) const llvm::TargetLoweringBase [inline]
getLoadExtAction(unsigned ExtType, EVT VT) const llvm::TargetLoweringBase [inline]
getMaximalGlobalOffset() const llvm::TargetLoweringBase [inline, virtual]
getMaxStoresPerMemcpy(bool OptSize) const llvm::TargetLoweringBase [inline]
getMaxStoresPerMemmove(bool OptSize) const llvm::TargetLoweringBase [inline]
getMaxStoresPerMemset(bool OptSize) const llvm::TargetLoweringBase [inline]
getMinFunctionAlignment() const llvm::TargetLoweringBase [inline]
getMinimumJumpTableEntries() const llvm::TargetLoweringBase [inline]
getMinStackArgumentAlignment() const llvm::TargetLoweringBase [inline]
getMultipleConstraintMatchWeight(AsmOperandInfo &info, int maIndex) const llvm::TargetLowering [virtual]
getNumRegisters(LLVMContext &Context, EVT VT) const llvm::TargetLoweringBase [inline]
getObjFileLowering() const llvm::TargetLoweringBase [inline]
getOperationAction(unsigned Op, EVT VT) const llvm::TargetLoweringBase [inline]
getOptimalMemOpType(uint64_t, unsigned, unsigned, bool, bool, bool, MachineFunction &) const llvm::TargetLoweringBase [inline, virtual]
getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const llvm::TargetLowering [virtual]
getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const llvm::TargetLowering [virtual]
getPointerSizeInBits(uint32_t AS=0) const llvm::TargetLoweringBase
getPointerTy(uint32_t=0) const llvm::TargetLoweringBase [virtual]
getPointerTypeSizeInBits(Type *Ty) const llvm::TargetLoweringBase
getPostIndexedAddressParts(SDNode *, SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const llvm::TargetLowering [inline, virtual]
getPreferredVectorAction(EVT VT) const llvm::TargetLoweringBase [inline, virtual]
getPrefFunctionAlignment() const llvm::TargetLoweringBase [inline]
getPrefLoopAlignment() const llvm::TargetLoweringBase [inline]
getPreIndexedAddressParts(SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const llvm::TargetLowering [inline, virtual]
getRegClassFor(MVT VT) const llvm::TargetLoweringBase [inline, virtual]
getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const overridellvm::SystemZTargetLowering [virtual]
getRegisterByName(const char *RegName, EVT VT) const llvm::TargetLowering [inline, virtual]
getRegisterType(MVT VT) const llvm::TargetLoweringBase [inline]
getRegisterType(LLVMContext &Context, EVT VT) const llvm::TargetLoweringBase [inline]
getRepRegClassCostFor(MVT VT) const llvm::TargetLoweringBase [inline, virtual]
getRepRegClassFor(MVT VT) const llvm::TargetLoweringBase [inline, virtual]
getScalarShiftAmountTy(EVT LHSTy) const overridellvm::SystemZTargetLowering [inline, virtual]
getScalingFactorCost(const AddrMode &AM, Type *Ty) const llvm::TargetLoweringBase [inline, virtual]
getSchedulingPreference() const llvm::TargetLoweringBase [inline]
getSchedulingPreference(SDNode *) const llvm::TargetLoweringBase [inline, virtual]
getScratchRegisters(CallingConv::ID CC) const llvm::TargetLowering [inline, virtual]
getSetCCResultType(LLVMContext &, EVT) const overridellvm::SystemZTargetLowering [virtual]
getShiftAmountTy(EVT LHSTy) const llvm::TargetLoweringBase
getSimpleValueType(Type *Ty, bool AllowUnknown=false) const llvm::TargetLoweringBase [inline]
getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const overridellvm::SystemZTargetLowering [virtual]
getStackCookieLocation(unsigned &, unsigned &) const llvm::TargetLoweringBase [inline, virtual]
getStackPointerRegisterToSaveRestore() const llvm::TargetLoweringBase [inline]
getTargetMachine() const llvm::TargetLoweringBase [inline]
getTargetNodeName(unsigned Opcode) const overridellvm::SystemZTargetLowering [virtual]
getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, unsigned) const llvm::TargetLoweringBase [inline, virtual]
getTruncStoreAction(EVT ValVT, EVT MemVT) const llvm::TargetLoweringBase [inline]
getTypeAction(LLVMContext &Context, EVT VT) const llvm::TargetLoweringBase [inline]
getTypeAction(MVT VT) const llvm::TargetLoweringBase [inline]
getTypeConversion(LLVMContext &Context, EVT VT) const llvm::TargetLoweringBase [inline]
getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const llvm::TargetLowering [inline, virtual]
getTypeLegalizationCost(Type *Ty) const llvm::TargetLoweringBase
getTypeToExpandTo(LLVMContext &Context, EVT VT) const llvm::TargetLoweringBase [inline]
getTypeToPromoteTo(unsigned Op, MVT VT) const llvm::TargetLoweringBase [inline]
getTypeToTransformTo(LLVMContext &Context, EVT VT) const llvm::TargetLoweringBase [inline]
getValueType(Type *Ty, bool AllowUnknown=false) const llvm::TargetLoweringBase [inline]
getValueTypeActions() const llvm::TargetLoweringBase [inline]
getVectorIdxTy() const llvm::TargetLoweringBase [inline, virtual]
getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const llvm::TargetLoweringBase
HandleByVal(CCState *, unsigned &, unsigned) const llvm::TargetLowering [inline, virtual]
hasBigEndianPartOrdering(EVT VT) const llvm::TargetLoweringBase [inline]
hasExtractBitsInsn() const llvm::TargetLoweringBase [inline]
hasFloatingPointExceptions() const llvm::TargetLoweringBase [inline]
hasLoadLinkedStoreConditional() const llvm::TargetLoweringBase [inline, virtual]
hasMultipleConditionRegisters() const llvm::TargetLoweringBase [inline]
hasPairedLoad(Type *, unsigned &) const llvm::TargetLoweringBase [inline, virtual]
hasPairedLoad(EVT, unsigned &) const llvm::TargetLoweringBase [inline, virtual]
hasTargetDAGCombine(ISD::NodeType NT) const llvm::TargetLoweringBase [inline]
initActions()llvm::TargetLoweringBase [protected]
InstructionOpcodeToISD(unsigned Opcode) const llvm::TargetLoweringBase
isBigEndian() const llvm::TargetLoweringBase [inline]
isCondCodeLegal(ISD::CondCode CC, MVT VT) const llvm::TargetLoweringBase [inline]
isConstFalseVal(const SDNode *N) const llvm::TargetLowering
isConstTrueVal(const SDNode *N) const llvm::TargetLowering
isDesirableToCommuteWithShift(const SDNode *N) const llvm::TargetLowering [inline, virtual]
IsDesirableToPromoteOp(SDValue, EVT &) const llvm::TargetLowering [inline, virtual]
isDesirableToTransformToIntegerOp(unsigned, EVT) const llvm::TargetLowering [inline, virtual]
isFAbsFree(EVT VT) const llvm::TargetLoweringBase [inline, virtual]
isFMAFasterThanFMulAndFAdd(EVT VT) const overridellvm::SystemZTargetLowering [virtual]
isFNegFree(EVT VT) const llvm::TargetLoweringBase [inline, virtual]
isFPImmLegal(const APFloat &Imm, EVT VT) const overridellvm::SystemZTargetLowering [virtual]
isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) const llvm::TargetLowering [virtual]
isIndexedLoadLegal(unsigned IdxMode, EVT VT) const llvm::TargetLoweringBase [inline]
isIndexedStoreLegal(unsigned IdxMode, EVT VT) const llvm::TargetLoweringBase [inline]
isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const llvm::TargetLowering
isIntDivCheap() const llvm::TargetLoweringBase [inline]
isJumpExpensive() const llvm::TargetLoweringBase [inline]
isLegalAddImmediate(int64_t) const llvm::TargetLoweringBase [inline, virtual]
isLegalAddressingMode(const AddrMode &AM, Type *Ty) const overridellvm::SystemZTargetLowering [virtual]
isLegalICmpImmediate(int64_t) const llvm::TargetLoweringBase [inline, virtual]
isLegalRC(const TargetRegisterClass *RC) const llvm::TargetLoweringBase [protected]
isLittleEndian() const llvm::TargetLoweringBase [inline]
isLoadBitCastBeneficial(EVT, EVT) const llvm::TargetLoweringBase [inline, virtual]
isLoadExtLegal(unsigned ExtType, EVT VT) const llvm::TargetLoweringBase [inline]
isMaskAndBranchFoldingLegal() const llvm::TargetLoweringBase [inline]
isNarrowingProfitable(EVT, EVT) const llvm::TargetLoweringBase [inline, virtual]
isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const llvm::TargetLoweringBase [inline, virtual]
isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const llvm::TargetLowering [virtual]
isOperationExpand(unsigned Op, EVT VT) const llvm::TargetLoweringBase [inline]
isOperationLegal(unsigned Op, EVT VT) const llvm::TargetLoweringBase [inline]
isOperationLegalOrCustom(unsigned Op, EVT VT) const llvm::TargetLoweringBase [inline]
isOperationLegalOrPromote(unsigned Op, EVT VT) const llvm::TargetLoweringBase [inline]
isPow2SDivCheap() const llvm::TargetLoweringBase [inline]
isPredictableSelectExpensive() const llvm::TargetLoweringBase [inline]
isSafeMemOpType(MVT) const llvm::TargetLoweringBase [inline, virtual]
isSelectExpensive() const llvm::TargetLoweringBase [inline]
isSelectSupported(SelectSupportKind) const llvm::TargetLoweringBase [inline, virtual]
isShuffleMaskLegal(const SmallVectorImpl< int > &, EVT) const llvm::TargetLoweringBase [inline, virtual]
isSlowDivBypassed() const llvm::TargetLoweringBase [inline]
isTruncateFree(Type *, Type *) const overridellvm::SystemZTargetLowering [virtual]
isTruncateFree(EVT, EVT) const overridellvm::SystemZTargetLowering [virtual]
isTruncStoreLegal(EVT ValVT, EVT MemVT) const llvm::TargetLoweringBase [inline]
isTypeDesirableForOp(unsigned, EVT VT) const llvm::TargetLowering [inline, virtual]
isTypeLegal(EVT VT) const llvm::TargetLoweringBase [inline]
isUsedByReturnOnly(SDNode *, SDValue &) const llvm::TargetLowering [inline, virtual]
isVectorClearMaskLegal(const SmallVectorImpl< int > &, EVT) const llvm::TargetLoweringBase [inline, virtual]
isVectorShiftByScalarCheap(Type *Ty) const llvm::TargetLoweringBase [inline, virtual]
isZExtFree(Type *, Type *) const llvm::TargetLoweringBase [inline, virtual]
isZExtFree(EVT, EVT) const llvm::TargetLoweringBase [inline, virtual]
isZExtFree(SDValue Val, EVT VT2) const llvm::TargetLoweringBase [inline, virtual]
Legal enum valuellvm::TargetLoweringBase
LegalizeAction enum namellvm::TargetLoweringBase
LegalizeKind typedefllvm::TargetLoweringBase
LegalizeTypeAction enum namellvm::TargetLoweringBase
LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const overridellvm::SystemZTargetLowering [virtual]
LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const overridellvm::SystemZTargetLowering [virtual]
LowerCallTo(CallLoweringInfo &CLI) const llvm::TargetLowering
LowerCustomJumpTableEntry(const MachineJumpTableInfo *, const MachineBasicBlock *, unsigned, MCContext &) const llvm::TargetLowering [inline, virtual]
LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const overridellvm::SystemZTargetLowering [virtual]
LowerOperation(SDValue Op, SelectionDAG &DAG) const overridellvm::SystemZTargetLowering [virtual]
LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const llvm::TargetLowering [virtual]
LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, SDLoc DL, SelectionDAG &DAG) const overridellvm::SystemZTargetLowering [virtual]
LowerXConstraint(EVT ConstraintVT) const llvm::TargetLowering [virtual]
makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const llvm::TargetLowering
MaskAndBranchFoldingIsLegalllvm::TargetLoweringBase [protected]
MaxStoresPerMemcpyllvm::TargetLoweringBase [protected]
MaxStoresPerMemcpyOptSizellvm::TargetLoweringBase [protected]
MaxStoresPerMemmovellvm::TargetLoweringBase [protected]
MaxStoresPerMemmoveOptSizellvm::TargetLoweringBase [protected]
MaxStoresPerMemsetllvm::TargetLoweringBase [protected]
MaxStoresPerMemsetOptSizellvm::TargetLoweringBase [protected]
mayBeEmittedAsTailCall(CallInst *CI) const overridellvm::SystemZTargetLowering [virtual]
ParseConstraints(ImmutableCallSite CS) const llvm::TargetLowering [virtual]
PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const overridellvm::SystemZTargetLowering [virtual]
PredictableSelectIsExpensivellvm::TargetLoweringBase [protected]
prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL, SelectionDAG &DAG) const overridellvm::SystemZTargetLowering [virtual]
Promote enum valuellvm::TargetLoweringBase
ReplaceNodeResults(SDNode *, SmallVectorImpl< SDValue > &, SelectionDAG &) const llvm::TargetLowering [inline, virtual]
resetOperationActions()llvm::TargetLoweringBase [inline, virtual]
ScalarCondVectorVal enum valuellvm::TargetLoweringBase
ScalarValSelect enum valuellvm::TargetLoweringBase
SelectSupportKind enum namellvm::TargetLoweringBase
setBooleanContents(BooleanContent Ty)llvm::TargetLoweringBase [inline, protected]
setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy)llvm::TargetLoweringBase [inline, protected]
setBooleanVectorContents(BooleanContent Ty)llvm::TargetLoweringBase [inline, protected]
setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC)llvm::TargetLoweringBase [inline]
setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)llvm::TargetLoweringBase [inline, protected]
setExceptionPointerRegister(unsigned R)llvm::TargetLoweringBase [inline, protected]
setExceptionSelectorRegister(unsigned R)llvm::TargetLoweringBase [inline, protected]
setHasExtractBitsInsn(bool hasExtractInsn=true)llvm::TargetLoweringBase [inline, protected]
setHasFloatingPointExceptions(bool FPExceptions=true)llvm::TargetLoweringBase [inline, protected]
setHasMultipleConditionRegisters(bool hasManyRegs=true)llvm::TargetLoweringBase [inline, protected]
setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)llvm::TargetLoweringBase [inline, protected]
setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)llvm::TargetLoweringBase [inline, protected]
setInsertFencesForAtomic(bool fence)llvm::TargetLoweringBase [inline, protected]
setIntDivIsCheap(bool isCheap=true)llvm::TargetLoweringBase [inline, protected]
setJumpBufAlignment(unsigned Align)llvm::TargetLoweringBase [inline, protected]
setJumpBufSize(unsigned Size)llvm::TargetLoweringBase [inline, protected]
setJumpIsExpensive(bool isExpensive=true)llvm::TargetLoweringBase [inline, protected]
setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)llvm::TargetLoweringBase [inline]
setLibcallName(RTLIB::Libcall Call, const char *Name)llvm::TargetLoweringBase [inline]
setLoadExtAction(unsigned ExtType, MVT VT, LegalizeAction Action)llvm::TargetLoweringBase [inline, protected]
setMinFunctionAlignment(unsigned Align)llvm::TargetLoweringBase [inline, protected]
setMinimumJumpTableEntries(int Val)llvm::TargetLoweringBase [inline, protected]
setMinStackArgumentAlignment(unsigned Align)llvm::TargetLoweringBase [inline, protected]
setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)llvm::TargetLoweringBase [inline, protected]
setPow2SDivIsCheap(bool isCheap=true)llvm::TargetLoweringBase [inline, protected]
setPrefFunctionAlignment(unsigned Align)llvm::TargetLoweringBase [inline, protected]
setPrefLoopAlignment(unsigned Align)llvm::TargetLoweringBase [inline, protected]
setSchedulingPreference(Sched::Preference Pref)llvm::TargetLoweringBase [inline, protected]
setSelectIsExpensive(bool isExpensive=true)llvm::TargetLoweringBase [inline, protected]
setStackPointerRegisterToSaveRestore(unsigned R)llvm::TargetLoweringBase [inline, protected]
setTargetDAGCombine(ISD::NodeType NT)llvm::TargetLoweringBase [inline, protected]
setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)llvm::TargetLoweringBase [inline, protected]
setUseUnderscoreLongJmp(bool Val)llvm::TargetLoweringBase [inline, protected]
setUseUnderscoreSetJmp(bool Val)llvm::TargetLoweringBase [inline, protected]
shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const llvm::TargetLoweringBase [inline, virtual]
shouldExpandAtomicLoadInIR(LoadInst *LI) const llvm::TargetLoweringBase [inline, virtual]
shouldExpandAtomicRMWInIR(AtomicRMWInst *RMWI) const llvm::TargetLoweringBase [inline, virtual]
shouldExpandAtomicStoreInIR(StoreInst *SI) const llvm::TargetLoweringBase [inline, virtual]
shouldExpandBuildVectorWithShuffles(EVT, unsigned DefinedValues) const llvm::TargetLoweringBase [inline, virtual]
ShouldShrinkFPConstant(EVT) const llvm::TargetLoweringBase [inline, virtual]
SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, APInt &KnownZero, APInt &KnownOne, TargetLoweringOpt &TLO, unsigned Depth=0) const llvm::TargetLowering
SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, SDLoc dl) const llvm::TargetLowering
softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, SDLoc DL) const llvm::TargetLowering
SystemZTargetLowering(const TargetMachine &TM)llvm::SystemZTargetLowering [explicit]
TargetLowering(const TargetMachine &TM, const TargetLoweringObjectFile *TLOF)llvm::TargetLowering [explicit]
TargetLoweringBase(const TargetMachine &TM, const TargetLoweringObjectFile *TLOF)llvm::TargetLoweringBase [explicit]
TypeExpandFloat enum valuellvm::TargetLoweringBase
TypeExpandInteger enum valuellvm::TargetLoweringBase
TypeLegal enum valuellvm::TargetLoweringBase
TypePromoteInteger enum valuellvm::TargetLoweringBase
TypeScalarizeVector enum valuellvm::TargetLoweringBase
TypeSoftenFloat enum valuellvm::TargetLoweringBase
TypeSplitVector enum valuellvm::TargetLoweringBase
TypeWidenVector enum valuellvm::TargetLoweringBase
UndefinedBooleanContent enum valuellvm::TargetLoweringBase
useLoadStackGuardNode() const llvm::TargetLowering [inline, virtual]
usesUnderscoreLongJmp() const llvm::TargetLoweringBase [inline]
usesUnderscoreSetJmp() const llvm::TargetLoweringBase [inline]
VectorMaskSelect enum valuellvm::TargetLoweringBase
verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const llvm::TargetLowering
ZeroOrNegativeOneBooleanContent enum valuellvm::TargetLoweringBase
ZeroOrOneBooleanContent enum valuellvm::TargetLoweringBase
~TargetLoweringBase()llvm::TargetLoweringBase [virtual]

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