llvm::TargetRegisterInfo Member List

This is the complete list of members for llvm::TargetRegisterInfo, including all inherited members.

avoidWriteAfterWrite(const TargetRegisterClass *RC) const	llvm::TargetRegisterInfo	[inline, virtual]
composeSubRegIndices(unsigned a, unsigned b) const	llvm::TargetRegisterInfo	[inline]
composeSubRegIndicesImpl(unsigned, unsigned) const	llvm::TargetRegisterInfo	[inline, protected, virtual]
eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const =0	llvm::TargetRegisterInfo	[pure virtual]
get(unsigned RegNo) const	llvm::MCRegisterInfo	[inline]
getAllocatableClass(const TargetRegisterClass *RC) const	llvm::TargetRegisterInfo
getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const	llvm::TargetRegisterInfo
getCalleeSavedRegs(const MachineFunction *MF=nullptr) const =0	llvm::TargetRegisterInfo	[pure virtual]
getCallPreservedMask(CallingConv::ID) const	llvm::TargetRegisterInfo	[inline, virtual]
getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const	llvm::TargetRegisterInfo
getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) const	llvm::TargetRegisterInfo
getCostPerUse(unsigned RegNo) const	llvm::TargetRegisterInfo	[inline]
getCoveringLanes() const	llvm::TargetRegisterInfo	[inline]
getCrossCopyRegClass(const TargetRegisterClass *RC) const	llvm::TargetRegisterInfo	[inline, virtual]
getCSRFirstUseCost() const	llvm::TargetRegisterInfo	[inline, virtual]
getDwarfRegNum(unsigned RegNum, bool isEH) const	llvm::MCRegisterInfo
getEncodingValue(unsigned RegNo) const	llvm::MCRegisterInfo	[inline]
getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const	llvm::TargetRegisterInfo	[inline, virtual]
getFrameRegister(const MachineFunction &MF) const =0	llvm::TargetRegisterInfo	[pure virtual]
getLargestLegalSuperClass(const TargetRegisterClass *RC) const	llvm::TargetRegisterInfo	[inline, virtual]
getLLVMRegNum(unsigned RegNum, bool isEH) const	llvm::MCRegisterInfo
getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) const	llvm::TargetRegisterInfo	[inline]
llvm::MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC) const	llvm::MCRegisterInfo
getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const	llvm::TargetRegisterInfo	[virtual]
getMinimalPhysRegClass(unsigned Reg, EVT VT=MVT::Other) const	llvm::TargetRegisterInfo
getName(unsigned RegNo) const	llvm::MCRegisterInfo	[inline]
getNumRegClasses() const	llvm::TargetRegisterInfo	[inline]
getNumRegPressureSets() const =0	llvm::TargetRegisterInfo	[pure virtual]
getNumRegs() const	llvm::MCRegisterInfo	[inline]
getNumRegUnits() const	llvm::MCRegisterInfo	[inline]
getNumSubRegIndices() const	llvm::MCRegisterInfo	[inline]
getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const	llvm::TargetRegisterInfo	[inline, virtual]
getProgramCounter() const	llvm::MCRegisterInfo	[inline]
getRARegister() const	llvm::MCRegisterInfo	[inline]
getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr) const	llvm::TargetRegisterInfo	[virtual]
getRegClass(unsigned i) const	llvm::TargetRegisterInfo	[inline]
getRegClassPressureSets(const TargetRegisterClass *RC) const =0	llvm::TargetRegisterInfo	[pure virtual]
getRegClassWeight(const TargetRegisterClass *RC) const =0	llvm::TargetRegisterInfo	[pure virtual]
getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const	llvm::TargetRegisterInfo	[inline, virtual]
getRegPressureSetLimit(unsigned Idx) const =0	llvm::TargetRegisterInfo	[pure virtual]
getRegPressureSetName(unsigned Idx) const =0	llvm::TargetRegisterInfo	[pure virtual]
getRegUnitPressureSets(unsigned RegUnit) const =0	llvm::TargetRegisterInfo	[pure virtual]
getRegUnitWeight(unsigned RegUnit) const =0	llvm::TargetRegisterInfo	[pure virtual]
getReservedRegs(const MachineFunction &MF) const =0	llvm::TargetRegisterInfo	[pure virtual]
getSEHRegNum(unsigned RegNum) const	llvm::MCRegisterInfo
getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const	llvm::TargetRegisterInfo	[inline, virtual]
getSubReg(unsigned Reg, unsigned Idx) const	llvm::MCRegisterInfo
getSubRegIdxOffset(unsigned Idx) const	llvm::MCRegisterInfo
getSubRegIdxSize(unsigned Idx) const	llvm::MCRegisterInfo
getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const	llvm::MCRegisterInfo
getSubRegIndexLaneMask(unsigned SubIdx) const	llvm::TargetRegisterInfo	[inline]
getSubRegIndexName(unsigned SubIdx) const	llvm::TargetRegisterInfo	[inline]
hasRegUnit(unsigned Reg, unsigned RegUnit) const	llvm::TargetRegisterInfo	[inline]
hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const	llvm::TargetRegisterInfo	[inline, virtual]
index2StackSlot(int FI)	llvm::TargetRegisterInfo	[inline, static]
index2VirtReg(unsigned Index)	llvm::TargetRegisterInfo	[inline, static]
InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, unsigned PC, const MCRegisterClass *C, unsigned NC, const MCPhysReg(*RURoots)[2], unsigned NRU, const MCPhysReg *DL, const char *Strings, const uint16_t *SubIndices, unsigned NumIndices, const SubRegCoveredBits *SubIdxRanges, const uint16_t *RET)	llvm::MCRegisterInfo	[inline]
isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const	llvm::TargetRegisterInfo	[inline, virtual]
isInAllocatableClass(unsigned RegNo) const	llvm::TargetRegisterInfo	[inline]
isPhysicalRegister(unsigned Reg)	llvm::TargetRegisterInfo	[inline, static]
isStackSlot(unsigned Reg)	llvm::TargetRegisterInfo	[inline, static]
isSubRegister(unsigned RegA, unsigned RegB) const	llvm::MCRegisterInfo	[inline]
isSubRegisterEq(unsigned RegA, unsigned RegB) const	llvm::MCRegisterInfo	[inline]
isSuperRegister(unsigned RegA, unsigned RegB) const	llvm::MCRegisterInfo	[inline]
isSuperRegisterEq(unsigned RegA, unsigned RegB) const	llvm::MCRegisterInfo	[inline]
isVirtualRegister(unsigned Reg)	llvm::TargetRegisterInfo	[inline, static]
mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size, bool isEH)	llvm::MCRegisterInfo	[inline]
mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size, bool isEH)	llvm::MCRegisterInfo	[inline]
mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg)	llvm::MCRegisterInfo	[inline]
materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const	llvm::TargetRegisterInfo	[inline, virtual]
mayOverrideLocalAssignment() const	llvm::TargetRegisterInfo	[inline, virtual]
MCRegUnitIterator class	llvm::MCRegisterInfo	[friend]
MCRegUnitRootIterator class	llvm::MCRegisterInfo	[friend]
MCSubRegIterator class	llvm::MCRegisterInfo	[friend]
MCSuperRegIterator class	llvm::MCRegisterInfo	[friend]
needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const	llvm::TargetRegisterInfo	[inline, virtual]
needsStackRealignment(const MachineFunction &MF) const	llvm::TargetRegisterInfo	[inline, virtual]
operator[](unsigned RegNo) const	llvm::MCRegisterInfo	[inline]
regclass_begin() const	llvm::TargetRegisterInfo	[inline]
regclass_end() const	llvm::TargetRegisterInfo	[inline]
regclass_iterator typedef	llvm::TargetRegisterInfo
regsOverlap(unsigned regA, unsigned regB) const	llvm::TargetRegisterInfo	[inline]
requiresFrameIndexScavenging(const MachineFunction &MF) const	llvm::TargetRegisterInfo	[inline, virtual]
requiresRegisterScavenging(const MachineFunction &MF) const	llvm::TargetRegisterInfo	[inline, virtual]
requiresVirtualBaseRegisters(const MachineFunction &MF) const	llvm::TargetRegisterInfo	[inline, virtual]
resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const	llvm::TargetRegisterInfo	[inline, virtual]
reverseLocalAssignment() const	llvm::TargetRegisterInfo	[inline, virtual]
saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, unsigned Reg) const	llvm::TargetRegisterInfo	[inline, virtual]
shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC) const	llvm::TargetRegisterInfo	[inline, virtual]
stackSlot2Index(unsigned Reg)	llvm::TargetRegisterInfo	[inline, static]
TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RegClassBegin, regclass_iterator RegClassEnd, const char *const *SRINames, const unsigned *SRILaneMasks, unsigned CoveringLanes)	llvm::TargetRegisterInfo	[protected]
trackLivenessAfterRegAlloc(const MachineFunction &MF) const	llvm::TargetRegisterInfo	[inline, virtual]
UpdateRegAllocHint(unsigned Reg, unsigned NewReg, MachineFunction &MF) const	llvm::TargetRegisterInfo	[inline, virtual]
useFPForScavengingIndex(const MachineFunction &MF) const	llvm::TargetRegisterInfo	[inline, virtual]
virtReg2Index(unsigned Reg)	llvm::TargetRegisterInfo	[inline, static]
~TargetRegisterInfo()	llvm::TargetRegisterInfo	[protected, virtual]