llvm::TargetSubtargetInfo Member List

This is the complete list of members for llvm::TargetSubtargetInfo, including all inherited members.

adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const	llvm::TargetSubtargetInfo	[inline, virtual]
ANTIDEP_ALL enum value	llvm::TargetSubtargetInfo
ANTIDEP_CRITICAL enum value	llvm::TargetSubtargetInfo
ANTIDEP_NONE enum value	llvm::TargetSubtargetInfo
AntiDepBreakMode enum name	llvm::TargetSubtargetInfo
enableAtomicExpand() const	llvm::TargetSubtargetInfo	[virtual]
enableEarlyIfConversion() const	llvm::TargetSubtargetInfo	[inline, virtual]
enableMachineScheduler() const	llvm::TargetSubtargetInfo	[virtual]
enablePostMachineScheduler() const	llvm::TargetSubtargetInfo	[virtual]
enableRALocalReassignment(CodeGenOpt::Level OptLevel) const	llvm::TargetSubtargetInfo	[virtual]
getAntiDepBreakMode() const	llvm::TargetSubtargetInfo	[inline, virtual]
getCriticalPathRCs(RegClassVector &CriticalPathRCs) const	llvm::TargetSubtargetInfo	[inline, virtual]
getDataLayout() const	llvm::TargetSubtargetInfo	[inline, virtual]
getFeatureBits() const	llvm::MCSubtargetInfo	[inline]
getFrameLowering() const	llvm::TargetSubtargetInfo	[inline, virtual]
getInstrInfo() const	llvm::TargetSubtargetInfo	[inline, virtual]
getInstrItineraryData() const	llvm::TargetSubtargetInfo	[inline, virtual]
getInstrItineraryForCPU(StringRef CPU) const	llvm::MCSubtargetInfo
getOptLevelToEnablePostRAScheduler() const	llvm::TargetSubtargetInfo	[inline, virtual]
getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, unsigned WriteResID) const	llvm::MCSubtargetInfo	[inline]
getRegisterInfo() const	llvm::TargetSubtargetInfo	[inline, virtual]
getSchedModel() const	llvm::MCSubtargetInfo	[inline]
getSchedModelForCPU(StringRef CPU) const	llvm::MCSubtargetInfo
getSelectionDAGInfo() const	llvm::TargetSubtargetInfo	[inline, virtual]
getTargetLowering() const	llvm::TargetSubtargetInfo	[inline, virtual]
getTargetTriple() const	llvm::MCSubtargetInfo	[inline]
getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const	llvm::MCSubtargetInfo	[inline]
getWriteProcResBegin(const MCSchedClassDesc *SC) const	llvm::MCSubtargetInfo	[inline]
getWriteProcResEnd(const MCSchedClassDesc *SC) const	llvm::MCSubtargetInfo	[inline]
InitCPUSchedModel(StringRef CPU)	llvm::MCSubtargetInfo
initInstrItins(InstrItineraryData &InstrItins) const	llvm::MCSubtargetInfo
InitMCProcessorInfo(StringRef CPU, StringRef FS)	llvm::MCSubtargetInfo
InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS, ArrayRef< SubtargetFeatureKV > PF, ArrayRef< SubtargetFeatureKV > PD, const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP)	llvm::MCSubtargetInfo
overrideSchedPolicy(MachineSchedPolicy &Policy, MachineInstr *begin, MachineInstr *end, unsigned NumRegionInstrs) const	llvm::TargetSubtargetInfo	[inline, virtual]
RegClassVector typedef	llvm::TargetSubtargetInfo
resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const	llvm::TargetSubtargetInfo	[inline, virtual]
setFeatureBits(uint64_t FeatureBits_)	llvm::MCSubtargetInfo	[inline]
TargetSubtargetInfo()	llvm::TargetSubtargetInfo	[protected]
ToggleFeature(uint64_t FB)	llvm::MCSubtargetInfo
ToggleFeature(StringRef FS)	llvm::MCSubtargetInfo
useAA() const	llvm::TargetSubtargetInfo	[virtual]
useMachineScheduler() const	llvm::TargetSubtargetInfo
~TargetSubtargetInfo()	llvm::TargetSubtargetInfo	[virtual]