Enumerations

enum NodeType {
FIRST_NUMBER = ISD::BUILTIN_OP_END, BSF, BSR, SHLD,
SHRD, FAND, FOR, FXOR,
FANDN, FSRL, CALL, RDTSC_DAG,
RDTSCP_DAG, RDPMC_DAG, CMP, COMI,
UCOMI, BT, SETCC, SELECT,
SETCC_CARRY, FSETCC, FGETSIGNx86, CMOV,
BRCOND, RET_FLAG, REP_STOS, REP_MOVS,
GlobalBaseReg, Wrapper, WrapperRIP, MOVDQ2Q,
MMX_MOVD2W, PEXTRB, PEXTRW, INSERTPS,
PINSRB, PINSRW, MMX_PINSRW, PSHUFB,
ANDNP, PSIGN, BLENDV, BLENDI,
ADDSUB, SUBUS, HADD, HSUB,
FHADD, FHSUB, UMAX, UMIN,
SMAX, SMIN, FMAX, FMIN,
FMAXC, FMINC, FRSQRT, FRCP,
TLSADDR, TLSBASEADDR, TLSCALL, EH_RETURN,
EH_SJLJ_SETJMP, EH_SJLJ_LONGJMP, TC_RETURN, VZEXT_MOVL,
VZEXT, VSEXT, VTRUNC, VTRUNCM,
VFPEXT, VFPROUND, VSHLDQ, VSRLDQ,
VSHL, VSRL, VSRA, VSHLI,
VSRLI, VSRAI, CMPP, PCMPEQ,
PCMPGT, PCMPEQM, PCMPGTM, CMPM,
CMPMU, ADD, SUB, ADC,
SBB, SMUL, INC, DEC,
OR, XOR, AND, BEXTR,
UMUL, MUL_IMM, PTEST, TESTP,
TESTM, TESTNM, KORTEST, PACKSS,
PACKUS, PALIGNR, VALIGN, PSHUFD,
PSHUFHW, PSHUFLW, SHUFP, MOVDDUP,
MOVSHDUP, MOVSLDUP, MOVLHPS, MOVLHPD,
MOVHLPS, MOVLPS, MOVLPD, MOVSD,
MOVSS, UNPCKL, UNPCKH, VPERMILP,
VPERMV, VPERMV3, VPERMIV3, VPERMI,
VPERM2X128, VBROADCAST, VBROADCASTM, VINSERT,
VEXTRACT, PMULUDQ, PMULDQ, FMADD,
FNMADD, FMSUB, FNMSUB, FMADDSUB,
FMSUBADD, VASTART_SAVE_XMM_REGS, WIN_ALLOCA, SEG_ALLOCA,
WIN_FTOL, MEMBARRIER, MFENCE, SFENCE,
LFENCE, FNSTSW16r, SAHF, RDRAND,
RDSEED, PCMPISTRI, PCMPESTRI, XTEST,
LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE, LCMPXCHG8_DAG, LCMPXCHG16_DAG, VZEXT_LOAD,
FNSTCW16m, FP_TO_INT16_IN_MEM, FP_TO_INT32_IN_MEM, FP_TO_INT64_IN_MEM,
FILD, FILD_FLAG, FLD, FST,
VAARG_64
}

Enumeration Type Documentation

enum llvm::X86ISD::NodeType

Enumerator:

FIRST_NUMBER
BSF	BSF - Bit scan forward. BSR - Bit scan reverse.
BSR
SHLD	SHLD, SHRD - Double shift instructions. These correspond to X86::SHLDxx and X86::SHRDxx instructions.
SHRD
FAND	FAND - Bitwise logical AND of floating point values. This corresponds to X86::ANDPS or X86::ANDPD.
FOR	FOR - Bitwise logical OR of floating point values. This corresponds to X86::ORPS or X86::ORPD.
FXOR	FXOR - Bitwise logical XOR of floating point values. This corresponds to X86::XORPS or X86::XORPD.
FANDN	FANDN - Bitwise logical ANDNOT of floating point values. This corresponds to X86::ANDNPS or X86::ANDNPD.
FSRL	FSRL - Bitwise logical right shift of floating point values. These corresponds to X86::PSRLDQ.
CALL	CALL - These operations represent an abstract X86 call instruction, which includes a bunch of information. In particular the operands of these node are: #0 - The incoming token chain #1 - The callee #2 - The number of arg bytes the caller pushes on the stack. #3 - The number of arg bytes the callee pops off the stack. #4 - The value to pass in AL/AX/EAX (optional) #5 - The value to pass in DL/DX/EDX (optional) The result values of these nodes are: #0 - The outgoing token chain #1 - The first register result value (optional) #2 - The second register result value (optional)
RDTSC_DAG	RDTSC_DAG - This operation implements the lowering for readcyclecounter
RDTSCP_DAG	X86 Read Time-Stamp Counter and Processor ID.
RDPMC_DAG	X86 Read Performance Monitoring Counters.
CMP	X86 compare and logical compare instructions.
COMI
UCOMI
BT	X86 bit-test instructions.
SETCC	X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS operand, usually produced by a CMP instruction.
SELECT	X86 Select.
SETCC_CARRY
FSETCC	X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD. Operands are two FP values to compare; result is a mask of 0s or 1s. Generally DTRT for C/C++ with NaNs.
FGETSIGNx86	X86 MOVMSK{pd\|ps}, extracts sign bits of two or four FP values, result in an integer GPR. Needs masking for scalar result.
CMOV	X86 conditional moves. Operand 0 and operand 1 are the two values to select from. Operand 2 is the condition code, and operand 3 is the flag operand produced by a CMP or TEST instruction. It also writes a flag result.
BRCOND	X86 conditional branches. Operand 0 is the chain operand, operand 1 is the block to branch if condition is true, operand 2 is the condition code, and operand 3 is the flag operand produced by a CMP or TEST instruction.
RET_FLAG	Return with a flag operand. Operand 0 is the chain operand, operand 1 is the number of bytes of stack to pop.
REP_STOS	REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
REP_MOVS	REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
GlobalBaseReg	GlobalBaseReg - On Darwin, this node represents the result of the popl at function entry, used for PIC code.
Wrapper	Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
WrapperRIP	WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP relative displacements.
MOVDQ2Q	MOVDQ2Q - Copies a 64-bit value from the low word of an XMM vector to an MMX vector. If you think this is too close to the previous mnemonic, so do I; blame Intel.
MMX_MOVD2W	MMX_MOVD2W - Copies a 32-bit value from the low word of a MMX vector to a GPR.
PEXTRB	PEXTRB - Extract an 8-bit value from a vector and zero extend it to i32, corresponds to X86::PEXTRB.
PEXTRW	PEXTRW - Extract a 16-bit value from a vector and zero extend it to i32, corresponds to X86::PEXTRW.
INSERTPS	INSERTPS - Insert any element of a 4 x float vector into any element of a destination 4 x floatvector.
PINSRB	PINSRB - Insert the lower 8-bits of a 32-bit value to a vector, corresponds to X86::PINSRB.
PINSRW	PINSRW - Insert the lower 16-bits of a 32-bit value to a vector, corresponds to X86::PINSRW.
MMX_PINSRW
PSHUFB	PSHUFB - Shuffle 16 8-bit values within a vector.
ANDNP	ANDNP - Bitwise Logical AND NOT of Packed FP values.
PSIGN	PSIGN - Copy integer sign.
BLENDV	BLENDV - Blend where the selector is a register.
BLENDI	BLENDI - Blend where the selector is an immediate.
ADDSUB	ADDSUB - Combined add and sub on an FP vector.
SUBUS
HADD	HADD - Integer horizontal add.
HSUB	HSUB - Integer horizontal sub.
FHADD	FHADD - Floating point horizontal add.
FHSUB	FHSUB - Floating point horizontal sub.
UMAX	UMAX, UMIN - Unsigned integer max and min.
UMIN
SMAX	SMAX, SMIN - Signed integer max and min.
SMIN
FMAX	FMAX, FMIN - Floating point max and min.
FMIN
FMAXC	FMAXC, FMINC - Commutative FMIN and FMAX.
FMINC
FRSQRT	FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal approximation. Note that these typically require refinement in order to obtain suitable precision.
FRCP
TLSADDR
TLSBASEADDR
TLSCALL
EH_RETURN
EH_SJLJ_SETJMP
EH_SJLJ_LONGJMP
TC_RETURN	TC_RETURN - Tail call return. See X86TargetLowering::LowerCall for the list of operands.
VZEXT_MOVL
VZEXT
VSEXT
VTRUNC
VTRUNCM
VFPEXT
VFPROUND
VSHLDQ
VSRLDQ
VSHL
VSRL
VSRA
VSHLI
VSRLI
VSRAI
CMPP
PCMPEQ
PCMPGT
PCMPEQM
PCMPGTM
CMPM	CMPM, CMPMU - Vector comparison generating mask bits for fp and integer signed and unsigned data types.
CMPMU
ADD
SUB
ADC
SBB
SMUL
INC
DEC
OR
XOR
AND
BEXTR
UMUL
MUL_IMM
PTEST
TESTP
TESTM
TESTNM
KORTEST
PACKSS
PACKUS
PALIGNR
VALIGN
PSHUFD
PSHUFHW
PSHUFLW
SHUFP
MOVDDUP
MOVSHDUP
MOVSLDUP
MOVLHPS
MOVLHPD
MOVHLPS
MOVLPS
MOVLPD
MOVSD
MOVSS
UNPCKL
UNPCKH
VPERMILP
VPERMV
VPERMV3
VPERMIV3
VPERMI
VPERM2X128
VBROADCAST
VBROADCASTM
VINSERT
VEXTRACT
PMULUDQ
PMULDQ
FMADD
FNMADD
FMSUB
FNMSUB
FMADDSUB
FMSUBADD
VASTART_SAVE_XMM_REGS
WIN_ALLOCA
SEG_ALLOCA
WIN_FTOL
MEMBARRIER
MFENCE
SFENCE
LFENCE
FNSTSW16r
SAHF
RDRAND
RDSEED
PCMPISTRI
PCMPESTRI
XTEST
LCMPXCHG_DAG
LCMPXCHG8_DAG
LCMPXCHG16_DAG
VZEXT_LOAD
FNSTCW16m
FP_TO_INT16_IN_MEM	FP_TO_INT_IN_MEM - This instruction implements FP_TO_SINT with the integer destination in memory and a FP reg source. This corresponds to the X86::FISTm instructions and the rounding mode change stuff. It has two inputs (token chain and address) and two outputs (int value and token chain).
FP_TO_INT32_IN_MEM
FP_TO_INT64_IN_MEM
FILD	FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the integer source in memory and FP reg result. This corresponds to the X86::FILD*m instructions. It has three inputs (token chain, address, and source type) and two outputs (FP value and token chain). FILD_FLAG also produces a flag).
FILD_FLAG
FLD	FLD - This instruction implements an extending load to FP stack slots. This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain operand, ptr to load from, and a ValueType node indicating the type to load to.
FST	FST - This instruction implements a truncating store to FP stack slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a chain operand, value to store, address, and a ValueType to store it as.
VAARG_64	VAARG_64 - This instruction grabs the address of the next argument from a va_list. (reads and modifies the va_list in memory)

Definition at line 29 of file X86ISelLowering.h.