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3945.h
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1 /******************************************************************************
2  *
3  * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of version 2 of the GNU General Public License as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17  *
18  * The full GNU General Public License is included in this distribution in the
19  * file called LICENSE.
20  *
21  * Contact Information:
22  * Intel Linux Wireless <[email protected]>
23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24  *
25  *****************************************************************************/
26 
27 #ifndef __il_3945_h__
28 #define __il_3945_h__
29 
30 #include <linux/pci.h> /* for struct pci_device_id */
31 #include <linux/kernel.h>
32 #include <net/ieee80211_radiotap.h>
33 
34 /* Hardware specific file defines the PCI IDs table for that hardware module */
35 extern const struct pci_device_id il3945_hw_card_ids[];
36 
37 #include "common.h"
38 
39 extern const struct il_ops il3945_ops;
40 
41 /* Highest firmware API version supported */
42 #define IL3945_UCODE_API_MAX 2
43 
44 /* Lowest firmware API version supported */
45 #define IL3945_UCODE_API_MIN 1
46 
47 #define IL3945_FW_PRE "iwlwifi-3945-"
48 #define _IL3945_MODULE_FIRMWARE(api) IL3945_FW_PRE #api ".ucode"
49 #define IL3945_MODULE_FIRMWARE(api) _IL3945_MODULE_FIRMWARE(api)
50 
51 /* Default noise level to report when noise measurement is not available.
52  * This may be because we're:
53  * 1) Not associated (4965, no beacon stats being sent to driver)
54  * 2) Scanning (noise measurement does not apply to associated channel)
55  * 3) Receiving CCK (3945 delivers noise info only for OFDM frames)
56  * Use default noise value of -127 ... this is below the range of measurable
57  * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
58  * Also, -127 works better than 0 when averaging frames with/without
59  * noise info (e.g. averaging might be done in app); measured dBm values are
60  * always negative ... using a negative value as the default keeps all
61  * averages within an s8's (used in some apps) range of negative values. */
62 #define IL_NOISE_MEAS_NOT_AVAILABLE (-127)
63 
64 /* Module parameters accessible from iwl-*.c */
65 extern struct il_mod_params il3945_mod_params;
66 
73  unsigned long stamp;
74 };
75 
76 struct il3945_rs_sta {
78  struct il_priv *il;
80  unsigned long last_partial_flush;
81  unsigned long last_flush;
90 #ifdef CONFIG_MAC80211_DEBUGFS
91  struct dentry *rs_sta_dbgfs_stats_table_file;
92 #endif
93 
94  /* used to be in sta_info */
96 };
97 
98 /*
99  * The common struct MUST be first because it is shared between
100  * 3945 and 4965!
101  */
105 };
106 
111 };
112 
113 /*
114  * RTS threshold here is total size [2347] minus 4 FCS bytes
115  * Per spec:
116  * a value of 0 means RTS on all data/management packets
117  * a value > max MSDU size means no RTS
118  * else RTS for data/management frames where MPDU is larger
119  * than RTS value.
120  */
121 #define DEFAULT_RTS_THRESHOLD 2347U
122 #define MIN_RTS_THRESHOLD 0U
123 #define MAX_RTS_THRESHOLD 2347U
124 #define MAX_MSDU_SIZE 2304U
125 #define MAX_MPDU_SIZE 2346U
126 #define DEFAULT_BEACON_INTERVAL 100U
127 #define DEFAULT_SHORT_RETRY_LIMIT 7U
128 #define DEFAULT_LONG_RETRY_LIMIT 4U
129 
130 #define IL_TX_FIFO_AC0 0
131 #define IL_TX_FIFO_AC1 1
132 #define IL_TX_FIFO_AC2 2
133 #define IL_TX_FIFO_AC3 3
134 #define IL_TX_FIFO_HCCA_1 5
135 #define IL_TX_FIFO_HCCA_2 6
136 #define IL_TX_FIFO_NONE 7
137 
138 #define IEEE80211_DATA_LEN 2304
139 #define IEEE80211_4ADDR_LEN 30
140 #define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
141 #define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
142 
143 struct il3945_frame {
144  union {
148  u8 cmd[360];
149  } u;
150  struct list_head list;
151 };
152 
153 #define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
154 #define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
155 #define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
156 
157 #define SUP_RATE_11A_MAX_NUM_CHANNELS 8
158 #define SUP_RATE_11B_MAX_NUM_CHANNELS 4
159 #define SUP_RATE_11G_MAX_NUM_CHANNELS 12
160 
161 #define IL_SUPPORTED_RATES_IE_LEN 8
162 
163 #define SCAN_INTERVAL 100
164 
165 #define MAX_TID_COUNT 9
166 
167 #define IL_INVALID_RATE 0xFF
168 #define IL_INVALID_VALUE -1
169 
170 #define STA_PS_STATUS_WAKE 0
171 #define STA_PS_STATUS_SLEEP 1
172 
177  unsigned long packet_time;
178  struct list_head list;
179 };
180 
181 #define IL_RX_HDR(x) ((struct il3945_rx_frame_hdr *)(\
182  x->u.rx_frame.stats.payload + \
183  x->u.rx_frame.stats.phy_count))
184 #define IL_RX_END(x) ((struct il3945_rx_frame_end *)(\
185  IL_RX_HDR(x)->payload + \
186  le16_to_cpu(IL_RX_HDR(x)->len)))
187 #define IL_RX_STATS(x) (&x->u.rx_frame.stats)
188 #define IL_RX_DATA(x) (IL_RX_HDR(x)->payload)
189 
190 /******************************************************************************
191  *
192  * Functions implemented in iwl3945-base.c which are forward declared here
193  * for use by iwl-*.c
194  *
195  *****************************************************************************/
196 extern int il3945_calc_db_from_ratio(int sig_ratio);
197 extern void il3945_rx_replenish(void *data);
198 extern void il3945_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq);
199 extern unsigned int il3945_fill_beacon_frame(struct il_priv *il,
200  struct ieee80211_hdr *hdr,
201  int left);
202 extern int il3945_dump_nic_event_log(struct il_priv *il, bool full_log,
203  char **buf, bool display);
204 extern void il3945_dump_nic_error_log(struct il_priv *il);
205 
206 /******************************************************************************
207  *
208  * Functions implemented in iwl-[34]*.c which are forward declared here
209  * for use by iwl3945-base.c
210  *
211  * NOTE: The implementation of these functions are hardware specific
212  * which is why they are in the hardware specific files (vs. iwl-base.c)
213  *
214  * Naming convention --
215  * il3945_ <-- Its part of iwlwifi (should be changed to il3945_)
216  * il3945_hw_ <-- Hardware specific (implemented in iwl-XXXX.c by all HW)
217  * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
218  * il3945_bg_ <-- Called from work queue context
219  * il3945_mac_ <-- mac80211 callback
220  *
221  ****************************************************************************/
222 extern void il3945_hw_handler_setup(struct il_priv *il);
223 extern void il3945_hw_setup_deferred_work(struct il_priv *il);
224 extern void il3945_hw_cancel_deferred_work(struct il_priv *il);
225 extern int il3945_hw_rxq_stop(struct il_priv *il);
226 extern int il3945_hw_set_hw_params(struct il_priv *il);
227 extern int il3945_hw_nic_init(struct il_priv *il);
228 extern int il3945_hw_nic_stop_master(struct il_priv *il);
229 extern void il3945_hw_txq_ctx_free(struct il_priv *il);
230 extern void il3945_hw_txq_ctx_stop(struct il_priv *il);
231 extern int il3945_hw_nic_reset(struct il_priv *il);
232 extern int il3945_hw_txq_attach_buf_to_tfd(struct il_priv *il,
233  struct il_tx_queue *txq,
234  dma_addr_t addr, u16 len, u8 reset,
235  u8 pad);
236 extern void il3945_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq);
237 extern int il3945_hw_get_temperature(struct il_priv *il);
238 extern int il3945_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq);
239 extern unsigned int il3945_hw_get_beacon_cmd(struct il_priv *il,
240  struct il3945_frame *frame,
241  u8 rate);
242 void il3945_hw_build_tx_cmd_rate(struct il_priv *il, struct il_device_cmd *cmd,
243  struct ieee80211_tx_info *info,
244  struct ieee80211_hdr *hdr, int sta_id);
245 extern int il3945_hw_reg_send_txpower(struct il_priv *il);
246 extern int il3945_hw_reg_set_txpower(struct il_priv *il, s8 power);
247 extern void il3945_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb);
248 void il3945_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb);
249 extern void il3945_disable_events(struct il_priv *il);
250 extern int il4965_get_temperature(const struct il_priv *il);
251 extern void il3945_post_associate(struct il_priv *il);
252 extern void il3945_config_ap(struct il_priv *il);
253 
254 extern int il3945_commit_rxon(struct il_priv *il);
255 
264 extern u8 il3945_hw_find_station(struct il_priv *il, const u8 * bssid);
265 
266 extern __le32 il3945_get_antenna_flags(const struct il_priv *il);
267 extern int il3945_init_hw_rate_table(struct il_priv *il);
268 extern void il3945_reg_txpower_periodic(struct il_priv *il);
269 extern int il3945_txpower_set_from_eeprom(struct il_priv *il);
270 
271 extern int il3945_rs_next_rate(struct il_priv *il, int rate);
272 
273 /* scanning */
274 int il3945_request_scan(struct il_priv *il, struct ieee80211_vif *vif);
275 void il3945_post_scan(struct il_priv *il);
276 
277 /* rates */
278 extern const struct il3945_rate_info il3945_rates[RATE_COUNT_3945];
279 
280 /* RSSI to dBm */
281 #define IL39_RSSI_OFFSET 95
282 
283 /*
284  * EEPROM related constants, enums, and structures.
285  */
286 #define EEPROM_SKU_CAP_OP_MODE_MRC (1 << 7)
287 
288 /*
289  * Mapping of a Tx power level, at factory calibration temperature,
290  * to a radio/DSP gain table idx.
291  * One for each of 5 "sample" power levels in each band.
292  * v_det is measured at the factory, using the 3945's built-in power amplifier
293  * (PA) output voltage detector. This same detector is used during Tx of
294  * long packets in normal operation to provide feedback as to proper output
295  * level.
296  * Data copied from EEPROM.
297  * DO NOT ALTER THIS STRUCTURE!!!
298  */
300  u8 gain_idx; /* idx into power (gain) setup table ... */
301  s8 power; /* ... for this pwr level for this chnl group */
302  u16 v_det; /* PA output voltage */
303 } __packed;
304 
305 /*
306  * Mappings of Tx power levels -> nominal radio/DSP gain table idxes.
307  * One for each channel group (a.k.a. "band") (1 for BG, 4 for A).
308  * Tx power setup code interpolates between the 5 "sample" power levels
309  * to determine the nominal setup for a requested power level.
310  * Data copied from EEPROM.
311  * DO NOT ALTER THIS STRUCTURE!!!
312  */
314  struct il3945_eeprom_txpower_sample samples[5]; /* 5 power levels */
315  s32 a, b, c, d, e; /* coefficients for voltage->power
316  * formula (signed) */
317  s32 Fa, Fb, Fc, Fd, Fe; /* these modify coeffs based on
318  * frequency (signed) */
319  s8 saturation_power; /* highest power possible by h/w in this
320  * band */
321  u8 group_channel; /* "representative" channel # in this band */
322  s16 temperature; /* h/w temperature at factory calib this band
323  * (signed) */
324 } __packed;
325 
326 /*
327  * Temperature-based Tx-power compensation data, not band-specific.
328  * These coefficients are use to modify a/b/c/d/e coeffs based on
329  * difference between current temperature and factory calib temperature.
330  * Data copied from EEPROM.
331  */
338 } __packed;
339 
340 /*
341  * EEPROM map
342  */
345  u16 device_id; /* abs.ofs: 16 */
347  u16 pmc; /* abs.ofs: 20 */
349  u8 mac_address[6]; /* abs.ofs: 42 */
351  u16 board_revision; /* abs.ofs: 106 */
353  u8 board_pba_number[9]; /* abs.ofs: 119 */
355  u16 version; /* abs.ofs: 136 */
356  u8 sku_cap; /* abs.ofs: 138 */
357  u8 leds_mode; /* abs.ofs: 139 */
359  u16 wowlan_mode; /* abs.ofs: 142 */
360  u16 leds_time_interval; /* abs.ofs: 144 */
361  u8 leds_off_time; /* abs.ofs: 146 */
362  u8 leds_on_time; /* abs.ofs: 147 */
363  u8 almgor_m_version; /* abs.ofs: 148 */
364  u8 antenna_switch_type; /* abs.ofs: 149 */
366  u8 sku_id[4]; /* abs.ofs: 192 */
367 
368 /*
369  * Per-channel regulatory data.
370  *
371  * Each channel that *might* be supported by 3945 has a fixed location
372  * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory
373  * txpower (MSB).
374  *
375  * Entries immediately below are for 20 MHz channel width.
376  *
377  * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
378  */
379  u16 band_1_count; /* abs.ofs: 196 */
380  struct il_eeprom_channel band_1_channels[14]; /* abs.ofs: 198 */
381 
382 /*
383  * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196,
384  * 5.0 GHz channels 7, 8, 11, 12, 16
385  * (4915-5080MHz) (none of these is ever supported)
386  */
387  u16 band_2_count; /* abs.ofs: 226 */
388  struct il_eeprom_channel band_2_channels[13]; /* abs.ofs: 228 */
389 
390 /*
391  * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
392  * (5170-5320MHz)
393  */
394  u16 band_3_count; /* abs.ofs: 254 */
395  struct il_eeprom_channel band_3_channels[12]; /* abs.ofs: 256 */
396 
397 /*
398  * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
399  * (5500-5700MHz)
400  */
401  u16 band_4_count; /* abs.ofs: 280 */
402  struct il_eeprom_channel band_4_channels[11]; /* abs.ofs: 282 */
403 
404 /*
405  * 5.7 GHz channels 145, 149, 153, 157, 161, 165
406  * (5725-5825MHz)
407  */
408  u16 band_5_count; /* abs.ofs: 304 */
409  struct il_eeprom_channel band_5_channels[6]; /* abs.ofs: 306 */
410 
411  u8 reserved9[194];
412 
413 /*
414  * 3945 Txpower calibration data.
415  */
416 #define IL_NUM_TX_CALIB_GROUPS 5
418 /* abs.ofs: 512 */
419  struct il3945_eeprom_temperature_corr corrections; /* abs.ofs: 832 */
420  u8 reserved16[172]; /* fill out to full 1024 byte block */
421 } __packed;
422 
423 #define IL3945_EEPROM_IMG_SIZE 1024
424 
425 /* End of EEPROM */
426 
427 #define PCI_CFG_REV_ID_BIT_BASIC_SKU (0x40) /* bit 6 */
428 #define PCI_CFG_REV_ID_BIT_RTP (0x80) /* bit 7 */
429 
430 /* 4 DATA + 1 CMD. There are 2 HCCA queues that are not used. */
431 #define IL39_NUM_QUEUES 5
432 #define IL39_CMD_QUEUE_NUM 4
433 
434 #define IL_DEFAULT_TX_RETRY 15
435 
436 /*********************************************/
437 
438 #define RFD_SIZE 4
439 #define NUM_TFD_CHUNKS 4
440 
441 #define TFD_CTL_COUNT_SET(n) (n << 24)
442 #define TFD_CTL_COUNT_GET(ctl) ((ctl >> 24) & 7)
443 #define TFD_CTL_PAD_SET(n) (n << 28)
444 #define TFD_CTL_PAD_GET(ctl) (ctl >> 28)
445 
446 /* Sizes and addresses for instruction and data memory (SRAM) in
447  * 3945's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */
448 #define IL39_RTC_INST_LOWER_BOUND (0x000000)
449 #define IL39_RTC_INST_UPPER_BOUND (0x014000)
450 
451 #define IL39_RTC_DATA_LOWER_BOUND (0x800000)
452 #define IL39_RTC_DATA_UPPER_BOUND (0x808000)
453 
454 #define IL39_RTC_INST_SIZE (IL39_RTC_INST_UPPER_BOUND - \
455  IL39_RTC_INST_LOWER_BOUND)
456 #define IL39_RTC_DATA_SIZE (IL39_RTC_DATA_UPPER_BOUND - \
457  IL39_RTC_DATA_LOWER_BOUND)
458 
459 #define IL39_MAX_INST_SIZE IL39_RTC_INST_SIZE
460 #define IL39_MAX_DATA_SIZE IL39_RTC_DATA_SIZE
461 
462 /* Size of uCode instruction memory in bootstrap state machine */
463 #define IL39_MAX_BSM_SIZE IL39_RTC_INST_SIZE
464 
465 static inline int
466 il3945_hw_valid_rtc_data_addr(u32 addr)
467 {
468  return (addr >= IL39_RTC_DATA_LOWER_BOUND &&
470 }
471 
472 /* Base physical address of il3945_shared is provided to FH39_TSSR_CBB_BASE
473  * and &il3945_shared.rx_read_ptr[0] is provided to FH39_RCSR_RPTR_ADDR(0) */
476 } __packed;
477 
478 /************************************/
479 /* iwl3945 Flow Handler Definitions */
480 /************************************/
481 
486 #define FH39_MEM_LOWER_BOUND (0x0800)
487 #define FH39_MEM_UPPER_BOUND (0x1000)
488 
489 #define FH39_CBCC_TBL (FH39_MEM_LOWER_BOUND + 0x140)
490 #define FH39_TFDB_TBL (FH39_MEM_LOWER_BOUND + 0x180)
491 #define FH39_RCSR_TBL (FH39_MEM_LOWER_BOUND + 0x400)
492 #define FH39_RSSR_TBL (FH39_MEM_LOWER_BOUND + 0x4c0)
493 #define FH39_TCSR_TBL (FH39_MEM_LOWER_BOUND + 0x500)
494 #define FH39_TSSR_TBL (FH39_MEM_LOWER_BOUND + 0x680)
495 
496 /* TFDB (Transmit Frame Buffer Descriptor) */
497 #define FH39_TFDB(_ch, buf) (FH39_TFDB_TBL + \
498  ((_ch) * 2 + (buf)) * 0x28)
499 #define FH39_TFDB_CHNL_BUF_CTRL_REG(_ch) (FH39_TFDB_TBL + 0x50 * (_ch))
500 
501 /* CBCC channel is [0,2] */
502 #define FH39_CBCC(_ch) (FH39_CBCC_TBL + (_ch) * 0x8)
503 #define FH39_CBCC_CTRL(_ch) (FH39_CBCC(_ch) + 0x00)
504 #define FH39_CBCC_BASE(_ch) (FH39_CBCC(_ch) + 0x04)
505 
506 /* RCSR channel is [0,2] */
507 #define FH39_RCSR(_ch) (FH39_RCSR_TBL + (_ch) * 0x40)
508 #define FH39_RCSR_CONFIG(_ch) (FH39_RCSR(_ch) + 0x00)
509 #define FH39_RCSR_RBD_BASE(_ch) (FH39_RCSR(_ch) + 0x04)
510 #define FH39_RCSR_WPTR(_ch) (FH39_RCSR(_ch) + 0x20)
511 #define FH39_RCSR_RPTR_ADDR(_ch) (FH39_RCSR(_ch) + 0x24)
512 
513 #define FH39_RSCSR_CHNL0_WPTR (FH39_RCSR_WPTR(0))
514 
515 /* RSSR */
516 #define FH39_RSSR_CTRL (FH39_RSSR_TBL + 0x000)
517 #define FH39_RSSR_STATUS (FH39_RSSR_TBL + 0x004)
518 
519 /* TCSR */
520 #define FH39_TCSR(_ch) (FH39_TCSR_TBL + (_ch) * 0x20)
521 #define FH39_TCSR_CONFIG(_ch) (FH39_TCSR(_ch) + 0x00)
522 #define FH39_TCSR_CREDIT(_ch) (FH39_TCSR(_ch) + 0x04)
523 #define FH39_TCSR_BUFF_STTS(_ch) (FH39_TCSR(_ch) + 0x08)
524 
525 /* TSSR */
526 #define FH39_TSSR_CBB_BASE (FH39_TSSR_TBL + 0x000)
527 #define FH39_TSSR_MSG_CONFIG (FH39_TSSR_TBL + 0x008)
528 #define FH39_TSSR_TX_STATUS (FH39_TSSR_TBL + 0x010)
529 
530 /* DBM */
531 
532 #define FH39_SRVC_CHNL (6)
533 
534 #define FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE (20)
535 #define FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH (4)
536 
537 #define FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN (0x08000000)
538 
539 #define FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE (0x80000000)
540 
541 #define FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE (0x20000000)
542 
543 #define FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 (0x01000000)
544 
545 #define FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST (0x00001000)
546 
547 #define FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH (0x00000000)
548 
549 #define FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
550 #define FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER (0x00000001)
551 
552 #define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000)
553 #define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008)
554 
555 #define FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
556 
557 #define FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
558 
559 #define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
560 #define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
561 
562 #define FH39_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00004000)
563 
564 #define FH39_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR (0x00000001)
565 
566 #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON (0xFF000000)
567 #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON (0x00FF0000)
568 
569 #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B (0x00000400)
570 
571 #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON (0x00000100)
572 #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON (0x00000080)
573 
574 #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH (0x00000020)
575 #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH (0x00000005)
576 
577 #define FH39_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_ch) (BIT(_ch) << 24)
578 #define FH39_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_ch) (BIT(_ch) << 16)
579 
580 #define FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_ch) \
581  (FH39_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_ch) | \
582  FH39_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_ch))
583 
584 #define FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
585 
589 } __packed;
590 
591 struct il3945_tfd {
593  struct il3945_tfd_tb tbs[4];
594  u8 __pad[28];
595 } __packed;
596 
597 #ifdef CONFIG_IWLEGACY_DEBUGFS
598 extern const struct il_debugfs_ops il3945_debugfs_ops;
599 #endif
600 
601 #endif