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Linux Kernel
3.7.1
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All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
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Linux Kernel
3.7.1
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#include <mach-omap2/powerdomain.h>#include <mach-omap2/clockdomain.h>#include <mach-omap2/cm2xxx_3xxx.h>#include <mach-omap2/prm-regbits-34xx.h>#include <mach-omap2/cm-regbits-34xx.h>#include <dspbridge/devdefs.h>#include <hw_defs.h>#include <dspbridge/dspioctl.h>#include <dspbridge/sync.h>#include <dspbridge/clk.h>Go to the source code of this file.
Data Structures | |
| struct | map_l4_peripheral |
| struct | bpwr_clk_t |
| struct | bridge_dev_context |
Macros | |
| #define | ARM_MAILBOX_START 0xfffcf000 |
| #define | ARM_MAILBOX_LENGTH 0x800 |
| #define | TESTBLOCK_ID_START 0xfffed400 |
| #define | TESTBLOCK_ID_LENGTH 0xff |
| #define | TBC_ID_VALUE 0xB47002F |
| #define | SPACE_LENGTH 0x2000 |
| #define | API_CLKM_DPLL_DMA 0xfffec000 |
| #define | ARM_INTERRUPT_OFFSET 0xb00 |
| #define | BIOS24XX |
| #define | L4_PERIPHERAL_NULL 0x0 |
| #define | DSPVA_PERIPHERAL_NULL 0x0 |
| #define | MAX_LOCK_TLB_ENTRIES 15 |
| #define | L4_PERIPHERAL_PRM 0x48306000 /*PRM L4 Peripheral */ |
| #define | DSPVA_PERIPHERAL_PRM 0x1181e000 |
| #define | L4_PERIPHERAL_SCM 0x48002000 /*SCM L4 Peripheral */ |
| #define | DSPVA_PERIPHERAL_SCM 0x1181f000 |
| #define | L4_PERIPHERAL_MMU 0x5D000000 /*MMU L4 Peripheral */ |
| #define | DSPVA_PERIPHERAL_MMU 0x11820000 |
| #define | L4_PERIPHERAL_CM 0x48004000 /* Core L4, Clock Management */ |
| #define | DSPVA_PERIPHERAL_CM 0x1181c000 |
| #define | L4_PERIPHERAL_PER 0x48005000 /* PER */ |
| #define | DSPVA_PERIPHERAL_PER 0x1181d000 |
| #define | L4_PERIPHERAL_GPIO1 0x48310000 |
| #define | DSPVA_PERIPHERAL_GPIO1 0x11809000 |
| #define | L4_PERIPHERAL_GPIO2 0x49050000 |
| #define | DSPVA_PERIPHERAL_GPIO2 0x1180a000 |
| #define | L4_PERIPHERAL_GPIO3 0x49052000 |
| #define | DSPVA_PERIPHERAL_GPIO3 0x1180b000 |
| #define | L4_PERIPHERAL_GPIO4 0x49054000 |
| #define | DSPVA_PERIPHERAL_GPIO4 0x1180c000 |
| #define | L4_PERIPHERAL_GPIO5 0x49056000 |
| #define | DSPVA_PERIPHERAL_GPIO5 0x1180d000 |
| #define | L4_PERIPHERAL_IVA2WDT 0x49030000 |
| #define | DSPVA_PERIPHERAL_IVA2WDT 0x1180e000 |
| #define | L4_PERIPHERAL_DISPLAY 0x48050000 |
| #define | DSPVA_PERIPHERAL_DISPLAY 0x1180f000 |
| #define | L4_PERIPHERAL_SSI 0x48058000 |
| #define | DSPVA_PERIPHERAL_SSI 0x11804000 |
| #define | L4_PERIPHERAL_GDD 0x48059000 |
| #define | DSPVA_PERIPHERAL_GDD 0x11805000 |
| #define | L4_PERIPHERAL_SS1 0x4805a000 |
| #define | DSPVA_PERIPHERAL_SS1 0x11806000 |
| #define | L4_PERIPHERAL_SS2 0x4805b000 |
| #define | DSPVA_PERIPHERAL_SS2 0x11807000 |
| #define | L4_PERIPHERAL_CAMERA 0x480BC000 |
| #define | DSPVA_PERIPHERAL_CAMERA 0x11819000 |
| #define | L4_PERIPHERAL_SDMA 0x48056000 |
| #define | DSPVA_PERIPHERAL_SDMA 0x11810000 /* 0x1181d000 conflict w/ PER */ |
| #define | L4_PERIPHERAL_UART1 0x4806a000 |
| #define | DSPVA_PERIPHERAL_UART1 0x11811000 |
| #define | L4_PERIPHERAL_UART2 0x4806c000 |
| #define | DSPVA_PERIPHERAL_UART2 0x11812000 |
| #define | L4_PERIPHERAL_UART3 0x49020000 |
| #define | DSPVA_PERIPHERAL_UART3 0x11813000 |
| #define | L4_PERIPHERAL_MCBSP1 0x48074000 |
| #define | DSPVA_PERIPHERAL_MCBSP1 0x11814000 |
| #define | L4_PERIPHERAL_MCBSP2 0x49022000 |
| #define | DSPVA_PERIPHERAL_MCBSP2 0x11815000 |
| #define | L4_PERIPHERAL_MCBSP3 0x49024000 |
| #define | DSPVA_PERIPHERAL_MCBSP3 0x11816000 |
| #define | L4_PERIPHERAL_MCBSP4 0x49026000 |
| #define | DSPVA_PERIPHERAL_MCBSP4 0x11817000 |
| #define | L4_PERIPHERAL_MCBSP5 0x48096000 |
| #define | DSPVA_PERIPHERAL_MCBSP5 0x11818000 |
| #define | L4_PERIPHERAL_GPTIMER5 0x49038000 |
| #define | DSPVA_PERIPHERAL_GPTIMER5 0x11800000 |
| #define | L4_PERIPHERAL_GPTIMER6 0x4903a000 |
| #define | DSPVA_PERIPHERAL_GPTIMER6 0x11801000 |
| #define | L4_PERIPHERAL_GPTIMER7 0x4903c000 |
| #define | DSPVA_PERIPHERAL_GPTIMER7 0x11802000 |
| #define | L4_PERIPHERAL_GPTIMER8 0x4903e000 |
| #define | DSPVA_PERIPHERAL_GPTIMER8 0x11803000 |
| #define | L4_PERIPHERAL_SPI1 0x48098000 |
| #define | DSPVA_PERIPHERAL_SPI1 0x1181a000 |
| #define | L4_PERIPHERAL_SPI2 0x4809a000 |
| #define | DSPVA_PERIPHERAL_SPI2 0x1181b000 |
| #define | L4_PERIPHERAL_MBOX 0x48094000 |
| #define | DSPVA_PERIPHERAL_MBOX 0x11808000 |
| #define | PM_GRPSEL_BASE 0x48307000 |
| #define | DSPVA_GRPSEL_BASE 0x11821000 |
| #define | L4_PERIPHERAL_SIDETONE_MCBSP2 0x49028000 |
| #define | DSPVA_PERIPHERAL_SIDETONE_MCBSP2 0x11824000 |
| #define | L4_PERIPHERAL_SIDETONE_MCBSP3 0x4902a000 |
| #define | DSPVA_PERIPHERAL_SIDETONE_MCBSP3 0x11825000 |
| #define | MBX_PM_CLK_IDMASK 0x7F |
| #define | MBX_PM_CLK_CMDSHIFT 7 |
| #define | MBX_PM_CLK_CMDMASK 7 |
| #define | MBX_CORE1_RESOURCES 7 |
| #define | MBX_CORE2_RESOURCES 1 |
| #define | MBX_PM_MAX_RESOURCES 11 |
| #define | BPWR_DISABLE_CLOCK 0 |
| #define | BPWR_ENABLE_CLOCK 1 |
| #define | INTH_IT_REG_OFFSET 0x00 /* Interrupt register offset */ |
| #define | INTH_MASK_IT_REG_OFFSET 0x04 /* Mask Interrupt reg offset */ |
| #define | DSP_MAILBOX1_INT 10 |
| #define | MB_ARM2DSP1_REG_OFFSET 0x00 |
| #define | MB_ARM2DSP1B_REG_OFFSET 0x04 |
| #define | MB_DSP2ARM1B_REG_OFFSET 0x0C |
| #define | MB_ARM2DSP1_FLAG_REG_OFFSET 0x18 |
| #define | MB_ARM2DSP_FLAG 0x0001 |
| #define | MBOX_ARM2DSP HW_MBOX_ID0 |
| #define | MBOX_DSP2ARM HW_MBOX_ID1 |
| #define | MBOX_ARM HW_MBOX_U0_ARM |
| #define | MBOX_DSP HW_MBOX_U1_DSP1 |
| #define | ENABLE true |
| #define | DISABLE false |
| #define | HIGH_LEVEL true |
| #define | LOW_LEVEL false |
| #define | CLEAR_BIT(reg, mask) (reg &= ~mask) |
| #define | SET_BIT(reg, mask) (reg |= mask) |
| #define | SET_GROUP_BITS16(reg, position, width, value) |
| #define | CLEAR_BIT_INDEX(reg, index) (reg &= ~(1 << (index))) |
Enumerations | |
| enum | bpwr_ext_clock_id { BPWR_GP_TIMER5 = 0x10, BPWR_GP_TIMER6, BPWR_GP_TIMER7, BPWR_GP_TIMER8, BPWR_WD_TIMER3, BPWR_MCBSP1, BPWR_MCBSP2, BPWR_MCBSP3, BPWR_MCBSP4, BPWR_MCBSP5, BPWR_SSI = 0x20 } |
Functions | |
| int | sm_interrupt_dsp (struct bridge_dev_context *dev_context, u16 mb_val) |
Variables | |
| s32 | dsp_debug |
| #define DSPVA_PERIPHERAL_SDMA 0x11810000 /* 0x1181d000 conflict w/ PER */ |
| #define INTH_IT_REG_OFFSET 0x00 /* Interrupt register offset */ |
| #define INTH_MASK_IT_REG_OFFSET 0x04 /* Mask Interrupt reg offset */ |
| #define L4_PERIPHERAL_CM 0x48004000 /* Core L4, Clock Management */ |
| #define L4_PERIPHERAL_MMU 0x5D000000 /*MMU L4 Peripheral */ |
| #define L4_PERIPHERAL_PRM 0x48306000 /*PRM L4 Peripheral */ |
| #define L4_PERIPHERAL_SCM 0x48002000 /*SCM L4 Peripheral */ |
| enum bpwr_ext_clock_id |
| int sm_interrupt_dsp | ( | struct bridge_dev_context * | dev_context, |
| u16 | mb_val | ||
| ) |
Definition at line 369 of file tiomap_io.c.
| s32 dsp_debug |
Definition at line 184 of file dsp_core.c.
1.8.2